diff options
Diffstat (limited to 'arch/arm')
69 files changed, 3249 insertions, 525 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4dfc2c6309..20dbc2ff84 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -93,7 +93,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-vyasa.dtb dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb + rk3328-evb.dtb \ + rk3328-rock64.dtb dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ @@ -536,15 +537,14 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-bk4r1.dtb dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ - imx53-kp.dtb + imx53-kp.dtb \ + imx53-m53menlo.dtb dtb-$(CONFIG_MX6Q) += \ imx6-apalis.dtb \ imx6q-display5.dtb \ imx6q-logicpd.dtb \ - imx6q-novena.dtb - -dtb-$(CONFIG_TARGET_TBS2910) += \ + imx6q-novena.dtb \ imx6q-tbs2910.dtb dtb-$(CONFIG_MX6QDL) += \ @@ -552,19 +552,19 @@ dtb-$(CONFIG_MX6QDL) += \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ imx6dl-mamoj.dtb \ + imx6dl-sabreauto.dtb \ + imx6dl-sabresd.dtb \ + imx6dl-wandboard-revb1.dtb \ imx6q-cm-fx6.dtb \ imx6q-icore.dtb \ imx6q-icore-mipi.dtb \ imx6q-icore-rqs.dtb \ imx6q-sabreauto.dtb \ imx6q-sabresd.dtb \ - imx6dl-sabreauto.dtb \ - imx6dl-sabresd.dtb \ + imx6q-wandboard-revb1.dtb \ imx6qp-sabreauto.dtb \ - imx6qp-sabresd.dtb - -dtb-$(CONFIG_TARGET_WANDBOARD) += \ - imx6dl-wandboard-revb1.dtb + imx6qp-sabresd.dtb \ + imx6qp-wandboard-revd1.dtb dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb @@ -737,14 +737,19 @@ dtb-$(CONFIG_TARGET_VINCO) += \ at91-vinco.dtb dtb-$(CONFIG_ARCH_BCM283X) += \ - bcm2835-rpi-a-plus.dtb \ bcm2835-rpi-a.dtb \ + bcm2835-rpi-a-plus.dtb \ + bcm2835-rpi-b.dtb \ bcm2835-rpi-b-plus.dtb \ bcm2835-rpi-b-rev2.dtb \ - bcm2835-rpi-b.dtb \ - bcm2835-rpi-zero-w.dtb \ + bcm2835-rpi-cm1-io1.dtb \ + bcm2835-rpi-zero.dtb \ + bcm2835-rpi-zero-w.dtb\ bcm2836-rpi-2-b.dtb \ - bcm2837-rpi-3-b.dtb + bcm2837-rpi-3-a-plus.dtb \ + bcm2837-rpi-3-b.dtb \ + bcm2837-rpi-3-b-plus.dtb \ + bcm2837-rpi-cm3-io3.dtb dtb-$(CONFIG_ARCH_BCM63158) += \ bcm963158.dtb diff --git a/arch/arm/dts/bcm2835-rpi-a-plus.dts b/arch/arm/dts/bcm2835-rpi-a-plus.dts index 9f866491ef..db8a6017f2 100644 --- a/arch/arm/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/dts/bcm2835-rpi-a-plus.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" @@ -9,12 +10,12 @@ leds { act { - gpios = <&gpio 47 0>; + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; pwr { label = "PWR"; - gpios = <&gpio 35 0>; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; linux,default-trigger = "default-on"; }; @@ -30,8 +31,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "SDA0", - "SCL0", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", @@ -100,6 +101,12 @@ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2835-rpi-a.dts b/arch/arm/dts/bcm2835-rpi-a.dts index 4b1af06c8d..067d1f07a2 100644 --- a/arch/arm/dts/bcm2835-rpi-a.dts +++ b/arch/arm/dts/bcm2835-rpi-a.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" @@ -9,7 +10,7 @@ leds { act { - gpios = <&gpio 16 1>; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; }; @@ -95,6 +96,12 @@ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2835-rpi-b-plus.dts b/arch/arm/dts/bcm2835-rpi-b-plus.dts index a846f1e781..1e40d672b0 100644 --- a/arch/arm/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/dts/bcm2835-rpi-b-plus.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" @@ -10,12 +11,12 @@ leds { act { - gpios = <&gpio 47 0>; + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; pwr { label = "PWR"; - gpios = <&gpio 35 0>; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; linux,default-trigger = "default-on"; }; @@ -32,8 +33,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "SDA0", - "SCL0", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", @@ -102,6 +103,12 @@ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/dts/bcm2835-rpi-b-rev2.dts index e860964e39..28e7513ce6 100644 --- a/arch/arm/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/dts/bcm2835-rpi-b-rev2.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" @@ -10,7 +11,7 @@ leds { act { - gpios = <&gpio 16 1>; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; }; @@ -92,7 +93,13 @@ }; &hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; }; &uart0 { diff --git a/arch/arm/dts/bcm2835-rpi-b.dts b/arch/arm/dts/bcm2835-rpi-b.dts index 5d77f3f8c4..31ff602e2c 100644 --- a/arch/arm/dts/bcm2835-rpi-b.dts +++ b/arch/arm/dts/bcm2835-rpi-b.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" @@ -10,7 +11,7 @@ leds { act { - gpios = <&gpio 16 1>; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; }; @@ -90,6 +91,12 @@ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/dts/bcm2835-rpi-cm1-io1.dts new file mode 100644 index 0000000000..4764a25585 --- /dev/null +++ b/arch/arm/dts/bcm2835-rpi-cm1-io1.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835-rpi-cm1.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,compute-module", "brcm,bcm2835"; + model = "Raspberry Pi Compute Module IO board rev1"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "GPIO40", + "GPIO41", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45", + "HDMI_HPD_N", + /* Also used as ACT LED */ + "EMMC_EN_N", + /* Used by eMMC */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/dts/bcm2835-rpi-cm1.dtsi new file mode 100644 index 0000000000..ef22c2da78 --- /dev/null +++ b/arch/arm/dts/bcm2835-rpi-cm1.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" + +/ { + leds { + act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + }; + + reg_3v3: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1v8: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&sdhost { + non-removable; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_1v8>; +}; diff --git a/arch/arm/dts/bcm2835-rpi-zero-w.dts b/arch/arm/dts/bcm2835-rpi-zero-w.dts index 7817054775..ba0167df6c 100644 --- a/arch/arm/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/dts/bcm2835-rpi-zero-w.dts @@ -1,26 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com> + */ + /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-smsc9512.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" +#include "bcm283x-rpi-usb-otg.dtsi" / { compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; model = "Raspberry Pi Zero W"; + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + leds { act { - gpios = <&gpio 47 0>; + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; + }; }; -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "CAM_GPIO1", /* GPIO40 */ + "WL_ON", /* GPIO41 */ + "NC", /* GPIO42 */ + "WIFI_CLK", /* GPIO43 */ + "CAM_GPIO0", /* GPIO44 */ + "BT_ON", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED_N", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; }; &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; }; + +&sdhci { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/dts/bcm2835-rpi-zero.dts b/arch/arm/dts/bcm2835-rpi-zero.dts new file mode 100644 index 0000000000..3b35a8a4a5 --- /dev/null +++ b/arch/arm/dts/bcm2835-rpi-zero.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Stefan Wahren <stefan.wahren@i2se.com> + */ + +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-usb-otg.dtsi" + +/ { + compatible = "raspberrypi,model-zero", "brcm,bcm2835"; + model = "Raspberry Pi Zero"; + + leds { + act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "NC", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "NC", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED_N", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = <BCM2835_FSEL_ALT0>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/dts/bcm2835-rpi.dtsi b/arch/arm/dts/bcm2835-rpi.dtsi index 8b95832dd0..715d50c645 100644 --- a/arch/arm/dts/bcm2835-rpi.dtsi +++ b/arch/arm/dts/bcm2835-rpi.dtsi @@ -1,7 +1,7 @@ #include <dt-bindings/power/raspberrypi-power.h> / { - memory { + memory@0 { device_type = "memory"; reg = <0 0x10000000>; }; @@ -18,7 +18,7 @@ soc { firmware: firmware { - compatible = "raspberrypi,bcm2835-firmware"; + compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; mboxes = <&mailbox>; }; @@ -27,6 +27,12 @@ firmware = <&firmware>; #power-domain-cells = <1>; }; + + vchiq: mailbox@7e00b840 { + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0x3c>; + interrupts = <0 2>; + }; }; }; @@ -65,30 +71,20 @@ &sdhci { pinctrl-names = "default"; pinctrl-0 = <&emmc_gpio48>; - status = "okay"; bus-width = <4>; }; &sdhost { pinctrl-names = "default"; pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; status = "okay"; + bus-width = <4>; }; &usb { power-domains = <&power RPI_POWER_DOMAIN_USB>; }; -&v3d { - power-domains = <&power RPI_POWER_DOMAIN_V3D>; -}; - &hdmi { power-domains = <&power RPI_POWER_DOMAIN_HDMI>; status = "okay"; diff --git a/arch/arm/dts/bcm2835.dtsi b/arch/arm/dts/bcm2835.dtsi index 659b6e9513..a5c3824c80 100644 --- a/arch/arm/dts/bcm2835.dtsi +++ b/arch/arm/dts/bcm2835.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" / { @@ -17,10 +18,10 @@ soc { ranges = <0x7e000000 0x20000000 0x02000000>; dma-ranges = <0x40000000 0x00000000 0x20000000>; + }; - arm-pmu { - compatible = "arm,arm1176-pmu"; - }; + arm-pmu { + compatible = "arm,arm1176-pmu"; }; }; diff --git a/arch/arm/dts/bcm2836-rpi-2-b.dts b/arch/arm/dts/bcm2836-rpi-2-b.dts index e8de41444b..7b4e651baf 100644 --- a/arch/arm/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/dts/bcm2836-rpi-2-b.dts @@ -1,6 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2836.dtsi" -#include "bcm2835-rpi.dtsi" +#include "bcm2836-rpi.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" #include "bcm283x-rpi-usb-host.dtsi" @@ -8,18 +9,18 @@ compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; model = "Raspberry Pi 2 Model B"; - memory { + memory@0 { reg = <0 0x40000000>; }; leds { act { - gpios = <&gpio 47 0>; + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; pwr { label = "PWR"; - gpios = <&gpio 35 0>; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; linux,default-trigger = "default-on"; }; @@ -27,6 +28,72 @@ }; &gpio { + /* + * Taken from rpi_SCH_2b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "", /* GPIO30 */ + "LAN_RUN", + "CAM_GPIO1", + "", /* GPIO33 */ + "", /* GPIO34 */ + "PWR_LOW_N", + "", /* GPIO36 */ + "", /* GPIO37 */ + "USB_LIMIT", + "", /* GPIO39 */ + "PWM0_OUT", + "CAM_GPIO0", + "SMPS_SCL", + "SMPS_SDA", + "ETHCLK", + "PWM1_OUT", + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ @@ -40,6 +107,12 @@ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2836-rpi.dtsi b/arch/arm/dts/bcm2836-rpi.dtsi new file mode 100644 index 0000000000..c4c858b984 --- /dev/null +++ b/arch/arm/dts/bcm2836-rpi.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm2835-rpi.dtsi" + +&vchiq { + compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq"; +}; diff --git a/arch/arm/dts/bcm2836.dtsi b/arch/arm/dts/bcm2836.dtsi index 2c26d0be8b..c933e84138 100644 --- a/arch/arm/dts/bcm2836.dtsi +++ b/arch/arm/dts/bcm2836.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" / { @@ -8,28 +9,28 @@ <0x40000000 0x40000000 0x00001000>; dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - local_intc: local_intc { + local_intc: local_intc@40000000 { compatible = "brcm,bcm2836-l1-intc"; reg = <0x40000000 0x100>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-parent = <&local_intc>; }; + }; - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&local_intc>; - interrupts = <9>; - }; + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&local_intc>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; }; timer { compatible = "arm,armv7-timer"; interrupt-parent = <&local_intc>; - interrupts = <0>, // PHYS_SECURE_PPI - <1>, // PHYS_NONSECURE_PPI - <3>, // VIRT_PPI - <2>; // HYP_PPI + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI + <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI + <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI + <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI always-on; }; @@ -75,7 +76,7 @@ compatible = "brcm,bcm2836-armctrl-ic"; reg = <0x7e00b200 0x200>; interrupt-parent = <&local_intc>; - interrupts = <8>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; }; &cpu_thermal { diff --git a/arch/arm/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/dts/bcm2837-rpi-3-a-plus.dts new file mode 100644 index 0000000000..7f4437a8ee --- /dev/null +++ b/arch/arm/dts/bcm2837-rpi-3-a-plus.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model A+"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + reg = <0 0x20000000>; + }; + + leds { + act { + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; + }; + + pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "", + "BT_WL_ON", + "STATUS_LED_R", + "", + "", + "CAM_GPIO0", + "CAM_GPIO1", + ""; + status = "okay"; + }; +}; + +&gpio { + /* + * This is mostly based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "", /* GPIO42 */ + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; + status = "okay"; +}; + +/* + * SDHCI is used to control the SDIO for wireless + * + * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven + * by a single GPIO. We can't give GPIO control to one of the drivers, + * otherwise the other part would get unexpectedly disturbed. + */ +&sdhci { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio34>; + status = "okay"; + bus-width = <4>; + non-removable; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SDHOST is used to drive the SD card */ +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; + bus-width = <4>; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + }; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/dts/bcm2837-rpi-3-b-plus.dts new file mode 100644 index 0000000000..c6fa34c241 --- /dev/null +++ b/arch/arm/dts/bcm2837-rpi-3-b-plus.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-lan7515.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model B+"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + reg = <0 0x40000000>; + }; + + leds { + act { + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; + }; + + pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; + }; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_ON", + "WL_ON", + "STATUS_LED_R", + "LAN_RUN", + "", + "CAM_GPIO0", + "CAM_GPIO1", + ""; + status = "okay"; + }; +}; + +&gpio { + /* + * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETHCLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; + status = "okay"; +}; + +/* SDHCI is used to control the SDIO for wireless */ +&sdhci { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio34>; + status = "okay"; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&wifi_pwrseq>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SDHOST is used to drive the SD card */ +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; + bus-width = <4>; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; + }; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/dts/bcm2837-rpi-3-b.dts b/arch/arm/dts/bcm2837-rpi-3-b.dts index 20725ca487..ce71f578c5 100644 --- a/arch/arm/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/dts/bcm2837-rpi-3-b.dts @@ -1,6 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2837.dtsi" -#include "bcm2835-rpi.dtsi" +#include "bcm2836-rpi.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" #include "bcm283x-rpi-usb-host.dtsi" @@ -8,15 +9,122 @@ compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; model = "Raspberry Pi 3 Model B"; - memory { + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + memory@0 { reg = <0 0x40000000>; }; leds { act { - gpios = <&gpio 47 0>; + gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; }; }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; + }; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_ON", + "WL_ON", + "STATUS_LED", + "LAN_RUN", + "HDMI_HPD_N", + "CAM_GPIO0", + "CAM_GPIO1", + "PWR_LOW_N"; + status = "okay"; + }; +}; + +&gpio { + /* + * Taken from rpi_SCH_3b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "", /* GPIO 28 */ + "LAN_RUN_BOOT", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETHCLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; + status = "okay"; +}; + +&hdmi { + hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>; }; /* uart0 communicates with the BT module */ @@ -24,6 +132,12 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; + }; }; /* uart1 is mapped to the pin header */ @@ -35,11 +149,19 @@ /* SDHCI is used to control the SDIO for wireless */ &sdhci { + #address-cells = <1>; + #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&emmc_gpio34>; status = "okay"; bus-width = <4>; non-removable; + mmc-pwrseq = <&wifi_pwrseq>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; }; /* SDHOST is used to drive the SD card */ diff --git a/arch/arm/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/dts/bcm2837-rpi-cm3-io3.dts new file mode 100644 index 0000000000..6c8233a36d --- /dev/null +++ b/arch/arm/dts/bcm2837-rpi-cm3-io3.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837-rpi-cm3.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,3-compute-module", "brcm,bcm2837"; + model = "Raspberry Pi Compute Module 3 IO board V3.0"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "GPIO40", + "GPIO41", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45", + "GPIO46", + "GPIO47", + /* Used by eMMC */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/dts/bcm2837-rpi-cm3.dtsi new file mode 100644 index 0000000000..81399b2c5a --- /dev/null +++ b/arch/arm/dts/bcm2837-rpi-cm3.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" + +/ { + memory@0 { + reg = <0 0x40000000>; + }; + + reg_3v3: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1v8: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HDMI_HPD_N", + "EMMC_EN_N", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; + status = "okay"; + }; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_1v8>; + status = "okay"; +}; diff --git a/arch/arm/dts/bcm2837.dtsi b/arch/arm/dts/bcm2837.dtsi index bc1cca5cf4..beb6c502da 100644 --- a/arch/arm/dts/bcm2837.dtsi +++ b/arch/arm/dts/bcm2837.dtsi @@ -8,22 +8,28 @@ <0x40000000 0x40000000 0x00001000>; dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - local_intc: local_intc { + local_intc: local_intc@40000000 { compatible = "brcm,bcm2836-l1-intc"; reg = <0x40000000 0x100>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-parent = <&local_intc>; }; }; + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupt-parent = <&local_intc>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + }; + timer { compatible = "arm,armv7-timer"; interrupt-parent = <&local_intc>; - interrupts = <0>, // PHYS_SECURE_PPI - <1>, // PHYS_NONSECURE_PPI - <3>, // VIRT_PPI - <2>; // HYP_PPI + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI + <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI + <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI + <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI always-on; }; @@ -73,7 +79,7 @@ compatible = "brcm,bcm2836-armctrl-ic"; reg = <0x7e00b200 0x200>; interrupt-parent = <&local_intc>; - interrupts = <8>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; }; &cpu_thermal { diff --git a/arch/arm/dts/bcm283x-rpi-lan7515.dtsi b/arch/arm/dts/bcm283x-rpi-lan7515.dtsi new file mode 100644 index 0000000000..70bece63f9 --- /dev/null +++ b/arch/arm/dts/bcm283x-rpi-lan7515.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/net/microchip-lan78xx.h> + +/ { + aliases { + ethernet0 = ðernet; + }; +}; + +&usb { + usb-port@1 { + compatible = "usb424,2514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usb-port@1 { + compatible = "usb424,2514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,7800"; + reg = <1>; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + eth_phy: ethernet-phy@1 { + reg = <1>; + microchip,led-modes = < + LAN78XX_LINK_1000_ACTIVITY + LAN78XX_LINK_10_100_ACTIVITY + >; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/dts/bcm283x-rpi-smsc9512.dtsi index 9a0599f711..967e081cb9 100644 --- a/arch/arm/dts/bcm283x-rpi-smsc9512.dtsi +++ b/arch/arm/dts/bcm283x-rpi-smsc9512.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 / { aliases { ethernet0 = ðernet; diff --git a/arch/arm/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/dts/bcm283x-rpi-usb-otg.dtsi new file mode 100644 index 0000000000..e2fd9610e1 --- /dev/null +++ b/arch/arm/dts/bcm283x-rpi-usb-otg.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +&usb { + dr_mode = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + /* + * According to dwc2 the sum of all device EP + * fifo sizes shouldn't exceed 3776 bytes. + */ + g-tx-fifo-size = <256 256 512 512 512 768 768>; +}; diff --git a/arch/arm/dts/bcm283x.dtsi b/arch/arm/dts/bcm283x.dtsi index e45ba584e0..9777644c6c 100644 --- a/arch/arm/dts/bcm283x.dtsi +++ b/arch/arm/dts/bcm283x.dtsi @@ -2,6 +2,8 @@ #include <dt-bindings/clock/bcm2835.h> #include <dt-bindings/clock/bcm2835-aux.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/soc/bcm2835-pm.h> /* firmware-provided startup stubs live here, where the secondary CPUs are * spinning. @@ -20,8 +22,13 @@ #address-cells = <1>; #size-cells = <1>; + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + chosen { - bootargs = "earlyprintk console=ttyAMA0"; + stdout-path = "serial0:115200n8"; }; thermal-zones { @@ -44,7 +51,7 @@ }; }; - soc: soc { + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -60,6 +67,12 @@ clock-frequency = <1000000>; }; + txp@7e004000 { + compatible = "brcm,bcm2835-txp"; + reg = <0x7e004000 0x20>; + interrupts = <1 11>; + }; + dma: dma@7e007000 { compatible = "brcm,bcm2835-dma"; reg = <0x7e007000 0xf00>; @@ -108,9 +121,18 @@ #interrupt-cells = <2>; }; - watchdog@7e100000 { - compatible = "brcm,bcm2835-pm-wdt"; - reg = <0x7e100000 0x28>; + pm: watchdog@7e100000 { + compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x7e100000 0x114>, + <0x7e00a000 0x24>; + clocks = <&clocks BCM2835_CLOCK_V3D>, + <&clocks BCM2835_CLOCK_PERI_IMAGE>, + <&clocks BCM2835_CLOCK_H264>, + <&clocks BCM2835_CLOCK_ISP>; + clock-names = "v3d", "peri_image", "h264", "isp"; + system-power-controller; }; clocks: cprman@7e101000 { @@ -130,6 +152,7 @@ rng@7e104000 { compatible = "brcm,bcm2835-rng"; reg = <0x7e104000 0x10>; + interrupts = <2 29>; }; mailbox: mailbox@7e00b880 { @@ -217,6 +240,7 @@ gpclk2_gpio43: gpclk2_gpio43 { brcm,pins = <43>; brcm,function = <BCM2835_FSEL_ALT0>; + brcm,pull = <BCM2835_PUD_OFF>; }; i2c0_gpio0: i2c0_gpio0 { @@ -329,10 +353,12 @@ uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 { brcm,pins = <30 31>; brcm,function = <BCM2835_FSEL_ALT3>; + brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>; }; uart0_gpio32: uart0_gpio32 { brcm,pins = <32 33>; brcm,function = <BCM2835_FSEL_ALT3>; + brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>; }; uart0_gpio36: uart0_gpio36 { brcm,pins = <36 37>; @@ -391,8 +417,8 @@ i2s: i2s@7e203000 { compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x20>, - <0x7e101098 0x02>; + reg = <0x7e203000 0x24>; + clocks = <&clocks BCM2835_CLOCK_PCM>; dmas = <&dma 2>, <&dma 3>; @@ -432,6 +458,17 @@ interrupts = <2 14>; /* pwa1 */ }; + dpi: dpi@7e208000 { + compatible = "brcm,bcm2835-dpi"; + reg = <0x7e208000 0x8c>; + clocks = <&clocks BCM2835_CLOCK_VPU>, + <&clocks BCM2835_CLOCK_DPI>; + clock-names = "core", "pixel"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dsi0: dsi@7e209000 { compatible = "brcm,bcm2835-dsi0"; reg = <0x7e209000 0x78>; @@ -459,7 +496,7 @@ status = "disabled"; }; - aux: aux@0x7e215000 { + aux: aux@7e215000 { compatible = "brcm,bcm2835-aux"; #clock-cells = <1>; reg = <0x7e215000 0x8>; @@ -602,6 +639,7 @@ compatible = "brcm,bcm2835-v3d"; reg = <0x7ec00000 0x1000>; interrupts = <1 10>; + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; }; vc4: gpu { @@ -634,7 +672,6 @@ usbphy: phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; }; - -#include "bcm283x-uboot.dtsi" diff --git a/arch/arm/dts/imx53-m53.dtsi b/arch/arm/dts/imx53-m53.dtsi new file mode 100644 index 0000000000..fe5e0d308e --- /dev/null +++ b/arch/arm/dts/imx53-m53.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + */ + +#include "imx53.dtsi" + +/ { + model = "Aries/DENX M53"; + compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_backlight: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd-supply"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@41 { + compatible = "st,stmpe610"; + reg = <0x41>; + id = <0>; + blocks = <0x5>; + interrupts = <6 0x0>; + interrupt-parent = <&gpio7>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <3>; + st,touch-det-delay = <3>; + st,settling = <4>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 + MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi new file mode 100644 index 0000000000..329fa3b5e2 --- /dev/null +++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marek Vasut <marex@denx.de> + */ + +/ { + soc { + u-boot,dm-pre-reloc; + + aips@50000000 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&gpio5 { + u-boot,dm-pre-reloc; +}; + +&gpio6 { + u-boot,dm-pre-reloc; +}; + +&gpio7 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx53-m53menlo.dts b/arch/arm/dts/imx53-m53menlo.dts new file mode 100644 index 0000000000..a6805eca9d --- /dev/null +++ b/arch/arm/dts/imx53-m53menlo.dts @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marek Vasut <marex@denx.de> + */ + +/dts-v1/; +#include "imx53-m53.dtsi" +#include "imx53-m53menlo-u-boot.dtsi" + +/ { + model = "MENLO M53 EMBEDDED DEVICE"; + compatible = "menlo,m53menlo", "fsl,imx53"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user1 { + label = "TestLed601"; + gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + user2 { + label = "TestLed602"; + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + eth { + label = "EthLedYe"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + }; + + panel { + compatible = "edt,etm070080dh6"; + enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, + <&clks IMX5_CLK_CKO1_PODF>, + <&clks IMX5_CLK_CKO1>; + assigned-clock-parents = <&clks IMX5_CLK_AHB>; + assigned-clock-rates = <133333334>, <33333334>, <33333334>; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio6>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + dac@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + }; +}; + +&i2c2 { + touchscreen@41 { + status = "disabled"; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1d5 + MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5 + MX53_PAD_GPIO_19__CCM_CLKO 0x1d5 + MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 + >; + }; + + pinctrl_display_gpio: display-gpiogrp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */ + MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */ + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 + MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 + >; + }; + + pinctrl_lvds0: lvds0grp { + /* LVDS pins only have pin mux configuration */ + fsl,pins = < + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_usb: usbgrp { + fsl,pins = < + MX53_PAD_GPIO_2__GPIO1_2 0x1d5 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5 + >; + }; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0>; + status = "okay"; + + lvds0: lvds-channel@0 { + reg = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb>; + vbus-supply = <®_usbh1_vbus>; + phy_type = "utmi"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index 211ff5f69e..ed341cfd9d 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -1,17 +1,8 @@ -/* - * Copyright 2016 Beckhoff Automation - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + #include "imx53-pinfunc.h" #include <dt-bindings/clock/imx5-clock.h> #include <dt-bindings/gpio/gpio.h> @@ -19,8 +10,17 @@ #include <dt-bindings/interrupt-controller/irq.h> / { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + aliases { - serial1 = &uart2; + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -36,7 +36,45 @@ mmc1 = &esdhc2; mmc2 = &esdhc3; mmc3 = &esdhc4; - usb1 = &usbh1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&clks IMX5_CLK_ARM>; + clock-latency = <61036>; + voltage-tolerance = <5>; + operating-points = < + /* kHz */ + 166666 850000 + 400000 900000 + 800000 1050000 + 1000000 1200000 + 1200000 1300000 + >; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu_di0>, <&ipu_di1>; + }; + + capture_subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu_csi0>, <&ipu_csi1>; }; tzic: tz-interrupt-controller@fffc000 { @@ -46,13 +84,143 @@ reg = <0x0fffc000 0x4000>; }; + clocks { + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + pmu: pmu { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&tzic>; + interrupts = <77>; + }; + + usbphy0: usbphy-0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + + usbphy1: usbphy-1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&tzic>; ranges; - u-boot,dm-pre-reloc; + + sata: sata@10000000 { + compatible = "fsl,imx53-ahci"; + reg = <0x10000000 0x1000>; + interrupts = <28>; + clocks = <&clks IMX5_CLK_SATA_GATE>, + <&clks IMX5_CLK_SATA_REF>, + <&clks IMX5_CLK_AHB>; + clock-names = "sata", "sata_ref", "ahb"; + status = "disabled"; + }; + + ipu: ipu@18000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ipu"; + reg = <0x18000000 0x08000000>; + interrupts = <11 10>; + clocks = <&clks IMX5_CLK_IPU_GATE>, + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; + clock-names = "bus", "di0", "di1"; + resets = <&src 2>; + + ipu_csi0: port@0 { + reg = <0>; + + ipu_csi0_from_parallel_sensor: endpoint { + }; + }; + + ipu_csi1: port@1 { + reg = <1>; + + ipu_csi1_from_parallel_sensor: endpoint { + }; + }; + + ipu_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu_di0_disp0: endpoint@0 { + reg = <0>; + }; + + ipu_di0_lvds0: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds0_in>; + }; + }; + + ipu_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu_di1_disp1: endpoint@0 { + reg = <0>; + }; + + ipu_di1_lvds1: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds1_in>; + }; + + ipu_di1_tve: endpoint@2 { + reg = <2>; + remote-endpoint = <&tve_in>; + }; + }; + }; + + gpu: gpu@30000000 { + compatible = "amd,imageon-200.0", "amd,imageon"; + reg = <0x30000000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <12>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; + clock-names = "core_clk", "mem_iface_clk"; + }; aips@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; @@ -92,6 +260,47 @@ status = "disabled"; }; + uart3: serial@5000c000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <33>; + clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, + <&clks IMX5_CLK_UART3_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi1: spi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x50010000 0x4000>; + interrupts = <36>; + clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, + <&clks IMX5_CLK_ECSPI1_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi2: ssi@50014000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x50014000 0x4000>; + interrupts = <30>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, + <&clks IMX5_CLK_SSI2_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + esdhc3: esdhc@50020000 { compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; @@ -117,25 +326,18 @@ }; }; - iomuxc: iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc"; - reg = <0x53fa8000 0x4000>; - }; - - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx53-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; + aipstz1: bridge@53f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x53f00000 0x60>; }; - uart2: serial@53fc0000 { - compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; - dma-names = "rx", "tx"; + usbotg: usb@53f80000 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80000 0x0200>; + interrupts = <18>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -144,15 +346,37 @@ reg = <0x53f80200 0x0200>; interrupts = <14>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; dr_mode = "host"; status = "disabled"; }; - clks: ccm@53fd4000{ - compatible = "fsl,imx53-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; + usbh2: usb@53f80400 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80400 0x0200>; + interrupts = <16>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; + status = "disabled"; + }; + + usbh3: usb@53f80600 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80600 0x0200>; + interrupts = <17>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 3>; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc: usbmisc@53f80800 { + #index-cells = <1>; + compatible = "fsl,imx53-usbmisc"; + reg = <0x53f80800 0x200>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; }; gpio1: gpio@53f84000 { @@ -195,6 +419,188 @@ #interrupt-cells = <2>; }; + kpp: kpp@53f94000 { + compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; + reg = <0x53f94000 0x4000>; + interrupts = <60>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + wdog1: wdog@53f98000 { + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f98000 0x4000>; + interrupts = <58>; + clocks = <&clks IMX5_CLK_DUMMY>; + }; + + wdog2: wdog@53f9c000 { + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f9c000 0x4000>; + interrupts = <59>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + gpt: timer@53fa0000 { + compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; + reg = <0x53fa0000 0x4000>; + interrupts = <39>; + clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, + <&clks IMX5_CLK_GPT_HF_GATE>; + clock-names = "ipg", "per"; + }; + + srtc: rtc@53fa4000 { + compatible = "fsl,imx53-rtc"; + reg = <0x53fa4000 0x4000>; + interrupts = <24>; + clocks = <&clks IMX5_CLK_SRTC_GATE>; + }; + + iomuxc: iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + }; + + gpr: iomuxc-gpr@53fa8000 { + compatible = "fsl,imx53-iomuxc-gpr", "syscon"; + reg = <0x53fa8000 0xc>; + }; + + ldb: ldb@53fa8008 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ldb"; + reg = <0x53fa8008 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds0_in: endpoint { + remote-endpoint = <&ipu_di0_lvds0>; + }; + }; + + port@2 { + reg = <2>; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + + port@1 { + reg = <1>; + + lvds1_in: endpoint { + remote-endpoint = <&ipu_di1_lvds1>; + }; + }; + + port@2 { + reg = <2>; + }; + }; + }; + + pwm1: pwm@53fb4000 { + #pwm-cells = <2>; + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb4000 0x4000>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <61>; + }; + + pwm2: pwm@53fb8000 { + #pwm-cells = <2>; + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb8000 0x4000>; + clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, + <&clks IMX5_CLK_PWM2_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <94>; + }; + + uart1: serial@53fbc000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fbc000 0x4000>; + interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@53fc0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + can1: can@53fc8000 { + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fc8000 0x4000>; + interrupts = <82>; + clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, + <&clks IMX5_CLK_CAN1_SERIAL_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can2: can@53fcc000 { + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fcc000 0x4000>; + interrupts = <83>; + clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, + <&clks IMX5_CLK_CAN2_SERIAL_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + src: src@53fd0000 { + compatible = "fsl,imx53-src", "fsl,imx51-src"; + reg = <0x53fd0000 0x4000>; + #reset-cells = <1>; + }; + + clks: ccm@53fd4000{ + compatible = "fsl,imx53-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 0x04 0 72 0x04>; + #clock-cells = <1>; + }; + gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53fdc000 0x4000>; @@ -234,6 +640,18 @@ clocks = <&clks IMX5_CLK_I2C3_GATE>; status = "disabled"; }; + + uart4: serial@53ff0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53ff0000 0x4000>; + interrupts = <13>; + clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, + <&clks IMX5_CLK_UART4_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; }; aips@60000000 { /* AIPS2 */ @@ -243,25 +661,74 @@ reg = <0x60000000 0x10000000>; ranges; + aipstz2: bridge@63f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x63f00000 0x60>; + }; + + iim: iim@63f98000 { + compatible = "fsl,imx53-iim", "fsl,imx27-iim"; + reg = <0x63f98000 0x4000>; + interrupts = <69>; + clocks = <&clks IMX5_CLK_IIM_GATE>; + }; + + uart5: serial@63f90000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x63f90000 0x4000>; + interrupts = <86>; + clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, + <&clks IMX5_CLK_UART5_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + tigerp: tigerp@63fa0000 { + compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; + reg = <0x63fa0000 0x28>; + }; + + owire: owire@63fa4000 { + compatible = "fsl,imx53-owire", "fsl,imx21-owire"; + reg = <0x63fa4000 0x4000>; + clocks = <&clks IMX5_CLK_OWIRE_GATE>; + status = "disabled"; + }; + + ecspi2: spi@63fac000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x63fac000 0x4000>; + interrupts = <37>; + clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, + <&clks IMX5_CLK_ECSPI2_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + sdma: sdma@63fb0000 { compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; }; - fec: ethernet@63fec000 { - compatible = "fsl,imx53-fec", "fsl,imx25-fec"; - reg = <0x63fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; + cspi: spi@63fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; + reg = <0x63fc0000 0x4000>; + interrupts = <38>; + clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, + <&clks IMX5_CLK_CSPI_IPG_GATE>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -284,66 +751,65 @@ clocks = <&clks IMX5_CLK_I2C1_GATE>; status = "disabled"; }; - }; - - ipu: ipu@18000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x08000000>; - interrupts = <11 10>; - clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - u-boot,dm-pre-reloc; - ipu_csi0: port@0 { - reg = <0>; + ssi1: ssi@63fcc000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fcc000 0x4000>; + interrupts = <29>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, + <&clks IMX5_CLK_SSI1_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; }; - ipu_csi1: port@1 { - reg = <1>; + audmux: audmux@63fd0000 { + compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; + reg = <0x63fd0000 0x4000>; + status = "disabled"; }; - ipu_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu_di0_lvds0: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds0_in>; - }; + nfc: nand@63fdb000 { + compatible = "fsl,imx53-nand"; + reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; + interrupts = <8>; + clocks = <&clks IMX5_CLK_NFC_GATE>; + status = "disabled"; }; - ipu_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu_di1_disp1: endpoint@0 { - reg = <0>; - }; - - ipu_di1_lvds1: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds1_in>; - }; + ssi3: ssi@63fe8000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fe8000 0x4000>; + interrupts = <96>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, + <&clks IMX5_CLK_SSI3_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 46 0 0>, + <&sdma 47 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; - ipu_di1_tve: endpoint@2 { - reg = <2>; - remote-endpoint = <&tve_in>; - }; + fec: ethernet@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; }; - }; - tve: tve@63ff0000 { + tve: tve@63ff0000 { compatible = "fsl,imx53-tve"; reg = <0x63ff0000 0x1000>; interrupts = <92>; @@ -357,68 +823,33 @@ remote-endpoint = <&ipu_di1_tve>; }; }; - }; - - src: src@53fd0000 { - compatible = "fsl,imx53-src", "fsl,imx51-src"; - reg = <0x53fd0000 0x4000>; - #reset-cells = <1>; - }; - - ldb: ldb@53fa8008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ldb"; - reg = <0x53fa8008 0x4>; - gpr = <&gpr>; - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_in: endpoint { - remote-endpoint = <&ipu_di0_lvds0>; - }; - }; - - port@2 { - reg = <2>; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; + }; - port@1 { - reg = <1>; + vpu: vpu@63ff4000 { + compatible = "fsl,imx53-vpu", "cnm,coda7541"; + reg = <0x63ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, + <&clks IMX5_CLK_VPU_GATE>; + clock-names = "per", "ahb"; + resets = <&src 1>; + iram = <&ocram>; + }; - lvds1_in: endpoint { - remote-endpoint = <&ipu_di1_lvds1>; - }; - }; + sahara: crypto@63ff8000 { + compatible = "fsl,imx53-sahara"; + reg = <0x63ff8000 0x4000>; + interrupts = <19 20>; + clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, + <&clks IMX5_CLK_SAHARA_IPG_GATE>; + clock-names = "ipg", "ahb"; + }; + }; - port@2 { - reg = <2>; - }; - }; + ocram: sram@f8000000 { + compatible = "mmio-sram"; + reg = <0xf8000000 0x20000>; + clocks = <&clks IMX5_CLK_OCRAM>; }; }; }; diff --git a/arch/arm/dts/imx6dl-wandboard-revb1.dts b/arch/arm/dts/imx6dl-wandboard-revb1.dts index 738db4fc77..c2946fbaa0 100644 --- a/arch/arm/dts/imx6dl-wandboard-revb1.dts +++ b/arch/arm/dts/imx6dl-wandboard-revb1.dts @@ -13,6 +13,7 @@ compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; }; diff --git a/arch/arm/dts/imx6q-wandboard-revb1.dts b/arch/arm/dts/imx6q-wandboard-revb1.dts new file mode 100644 index 0000000000..f6ccbecff9 --- /dev/null +++ b/arch/arm/dts/imx6q-wandboard-revb1.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-wandboard-revb1.dtsi" + +/ { + model = "Wandboard i.MX6 Quad Board rev B1"; + compatible = "wand,imx6q-wandboard", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi index 855dc6f9df..e781a45785 100644 --- a/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi +++ b/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi @@ -1,13 +1,8 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. +// +// Author: Fabio Estevam <fabio.estevam@freescale.com> #include "imx6qdl-wandboard.dtsi" diff --git a/arch/arm/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/dts/imx6qdl-wandboard-revd1.dtsi new file mode 100644 index 0000000000..9390979688 --- /dev/null +++ b/arch/arm/dts/imx6qdl-wandboard-revd1.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. +// +// Author: Fabio Estevam <fabio.estevam@freescale.com> + +#include "imx6qdl-wandboard.dtsi" + +/ { + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + regulator-name = "ETH_PHY"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 13 GPIO_ACTIVE_LOW>; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&fec { + phy-supply = <®_eth_phy>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-wandboard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl-wandboard.dtsi b/arch/arm/dts/imx6qdl-wandboard.dtsi index 4d03d49fde..90aa43d21b 100644 --- a/arch/arm/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/dts/imx6qdl-wandboard.dtsi @@ -8,6 +8,14 @@ #include <dt-bindings/gpio/gpio.h> / { + aliases { + mmc0 = &usdhc3; + }; + + chosen { + stdout-path = &uart1; + }; + sound { compatible = "fsl,imx6-wandboard-sgtl5000", "fsl,imx-audio-sgtl5000"; @@ -90,107 +98,6 @@ VDDIO-supply = <®_3p3v>; lrclk-strength = <3>; }; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; }; &iomuxc { @@ -321,7 +228,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/imx6qp-wandboard-revd1.dts b/arch/arm/dts/imx6qp-wandboard-revd1.dts new file mode 100644 index 0000000000..08d8b78a20 --- /dev/null +++ b/arch/arm/dts/imx6qp-wandboard-revd1.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + */ +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 QuadPlus Board revD1"; + compatible = "wand,imx6qp-wandboard", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi new file mode 100644 index 0000000000..2efb309d6b --- /dev/null +++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Rockchip Electronics Co., Ltd + */ + +#include "rk3288-u-boot.dtsi" + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; + +&pcfg_pull_none_drv_8ma { + u-boot,dm-spl; +}; + +&pcfg_pull_up_drv_8ma { + u-boot,dm-spl; +}; + +&sdmmc_bus4 { + u-boot,dm-spl; +}; + +&sdmmc_clk { + u-boot,dm-spl; +}; + +&sdmmc_cmd { + u-boot,dm-spl; +}; + +&sdmmc_pwr { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts index 3edd21cc2f..94c3afe860 100644 --- a/arch/arm/dts/rk3288-tinker.dts +++ b/arch/arm/dts/rk3288-tinker.dts @@ -28,8 +28,6 @@ &pinctrl { - u-boot,dm-pre-reloc; - usb { host_vbus_drv: host-vbus-drv { rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; @@ -42,7 +40,6 @@ }; &uart2 { - u-boot,dm-pre-reloc; reg-shift = <2>; }; @@ -51,22 +48,6 @@ status = "okay"; }; -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; - &i2c2 { m24c08@50 { compatible = "at,24c08", "i2c-eeprom"; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi new file mode 100644 index 0000000000..4cf75c7504 --- /dev/null +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Rockchip Electronics Co., Ltd + */ + +&dmc { + u-boot,dm-pre-reloc; +}; + +&pmu { + u-boot,dm-pre-reloc; +}; + +&sgrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&vopb { + u-boot,dm-pre-reloc; +}; + +&vopl { + u-boot,dm-pre-reloc; +}; + +&noc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi index 22ba3490f2..eccc069368 100644 --- a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2015 Google, Inc */ +#include "rk3288-u-boot.dtsi" + &dmc { rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 diff --git a/arch/arm/dts/rk3288-vyasa-u-boot.dtsi b/arch/arm/dts/rk3288-vyasa-u-boot.dtsi index 379b1e3189..7730d17228 100644 --- a/arch/arm/dts/rk3288-vyasa-u-boot.dtsi +++ b/arch/arm/dts/rk3288-vyasa-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com> */ +#include "rk3288-u-boot.dtsi" + &dmc { rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 487d22c9b0..866fc08215 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -468,7 +468,6 @@ }; dmc: dmc@ff610000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-dmc", "syscon"; rockchip,cru = <&cru>; rockchip,grf = <&grf>; @@ -584,13 +583,11 @@ }; pmu: power-management@ff730000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-pmu", "syscon"; reg = <0xff730000 0x100>; }; sgrf: syscon@ff740000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-sgrf", "syscon"; reg = <0xff740000 0x1000>; }; @@ -599,7 +596,6 @@ compatible = "rockchip,rk3288-cru"; reg = <0xff760000 0x1000>; rockchip,grf = <&grf>; - u-boot,dm-pre-reloc; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, @@ -615,7 +611,6 @@ }; grf: syscon@ff770000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-grf", "syscon"; reg = <0xff770000 0x1000>; }; @@ -660,7 +655,6 @@ }; vopb: vop@ff930000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-vop"; reg = <0xff930000 0x19c>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; @@ -715,7 +709,6 @@ iommus = <&vopl_mmu>; power-domains = <&power RK3288_PD_VIO>; status = "disabled"; - u-boot,dm-pre-reloc; vopl_out: port { #address-cells = <1>; #size-cells = <0>; @@ -911,7 +904,6 @@ }; noc: syscon@ffac0000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-noc", "syscon"; reg = <0xffac0000 0x2000>; }; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..b077436cbc --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index ca0fc391b2..0e2e047180 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -629,7 +629,6 @@ ap_i2c_audio: &i2c8 { &uart2 { status = "okay"; - u-boot,dm-pre-reloc; }; &usb_host0_ohci { diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 897e0bda85..74368da550 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -639,7 +639,6 @@ }; &uart0 { - u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts>; status = "okay"; diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 7bddc3acdb..50b0ca0df5 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -4,3 +4,7 @@ */ #include "rk3399-u-boot.dtsi" + +&vdd_log { + regulator-init-microvolt = <950000>; +}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 0786c1193a..fcfce9ae02 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -10,3 +10,11 @@ &spi1 { u-boot,dm-pre-reloc; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index ade7285786..d8f9d8dc5f 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -78,10 +78,6 @@ }; }; -&clk_hse { - u-boot,dm-pre-reloc; -}; - &fmc { /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ bank1: bank@0 { @@ -123,9 +119,7 @@ }; fmc_pins: fmc@0 { - u-boot,dm-pre-reloc; pins { - u-boot,dm-pre-reloc; pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */ <STM32_PINMUX('D', 9, AF12)>, /* D14 */ <STM32_PINMUX('D', 8, AF12)>, /* D13 */ diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 53a645dace..209a82c9cf 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -152,6 +152,16 @@ slew-rate = <2>; }; }; + + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; }; &qspi { diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 2776a396c7..e3a893e49c 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -348,7 +348,7 @@ struct bcm2835_mbox_tag_depth { }; #define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006 -#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044005 +#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044006 #define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006 #define BCM2835_MBOX_PIXEL_ORDER_BGR 0 diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d42a15e877..24d16299e8 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -17,7 +17,7 @@ #define ALIGN_SIZE 0x1000 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 -#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 +#define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60 #define IS_HAB_ENABLED_BIT \ (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index b5e91d4a7d..60aef15f15 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -12,7 +12,6 @@ choice config TARGET_MT7623 bool "MediaTek MT7623 SoC" select CPU_V7A - select ARCH_MISC_INIT help The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7 including NEON and GPU, Mali-450 graphics, several DDR3 options, @@ -25,7 +24,6 @@ config TARGET_MT7629 bool "MediaTek MT7629 SoC" select CPU_V7A select SPL - select ARCH_MISC_INIT help The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, @@ -34,7 +32,6 @@ config TARGET_MT7629 config TARGET_MT8516 bool "MediaTek MT8516 SoC" select ARM64 - select ARCH_MISC_INIT help The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35. including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, diff --git a/arch/arm/mach-mediatek/cpu.c b/arch/arm/mach-mediatek/cpu.c index b37e299b74..1923c9e527 100644 --- a/arch/arm/mach-mediatek/cpu.c +++ b/arch/arm/mach-mediatek/cpu.c @@ -8,18 +8,6 @@ #include <wdt.h> #include <dm/uclass-internal.h> -int arch_misc_init(void) -{ - struct udevice *wdt; - int ret; - - ret = uclass_first_device_err(UCLASS_WDT, &wdt); - if (!ret) - wdt_stop(wdt); - - return 0; -} - int arch_cpu_init(void) { icache_enable(); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c05e3c3f48..1090d21879 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -87,6 +87,21 @@ config ROCKCHIP_RK3288 select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL + select SUPPORT_TPL + imply TPL_BOOTROM_SUPPORT + imply TPL_CLK + imply TPL_DM + imply TPL_DRIVERS_MISC_SUPPORT + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT + imply TPL_NEEDS_SEPARATE_TEXT_BASE + imply TPL_NEEDS_SEPARATE_STACK + imply TPL_OF_CONTROL + imply TPL_OF_PLATDATA + imply TPL_RAM + imply TPL_REGMAP + imply TPL_SERIAL_SUPPORT + imply TPL_SYSCON imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB help @@ -104,11 +119,21 @@ config TPL_TEXT_BASE config TPL_MAX_SIZE default 32768 +config TPL_STACK + default 0xff718000 + endif config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 + select SUPPORT_SPL + select SPL + imply SPL_SERIAL_SUPPORT + imply SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT + select SYS_NS16550 help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -158,6 +183,7 @@ config ROCKCHIP_RK3399 select SPL select SPL_ATF select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_BOARD_INIT if SPL select SPL_LOAD_FIT select SPL_CLK if SPL select SPL_PINCTRL if SPL @@ -183,6 +209,7 @@ config ROCKCHIP_RK3399 imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SYS_MALLOC_SIMPLE + imply TPL_BOARD_INIT imply TPL_BOOTROM_SUPPORT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_OF_CONTROL diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 846c82d70a..23760a959a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,6 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index 212bd0a854..db0ae96ca8 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -12,6 +12,7 @@ import os import sys import getopt +import logging # pip install pyelftools from elftools.elf.elffile import ELFFile @@ -89,13 +90,17 @@ def append_conf_section(file, cnt, dtname, segments): file.write('\t\tconfig_%d {\n' % cnt) file.write('\t\t\tdescription = "%s";\n' % dtname) file.write('\t\t\tfirmware = "atf_1";\n') - file.write('\t\t\tloadables = "uboot",') + file.write('\t\t\tloadables = "uboot"') + if segments != 0: + file.write(',') for i in range(1, segments): - file.write('"atf_%d"' % (i)) + file.write('"atf_%d"' % (i + 1)) if i != (segments - 1): file.write(',') else: file.write(';\n') + if segments == 0: + file.write(';\n') file.write('\t\t\tfdt = "fdt_1";\n') file.write('\t\t};\n') file.write('\n') @@ -171,8 +176,18 @@ def generate_atf_binary(bl31_file_name): def main(): uboot_elf = "./u-boot" - bl31_elf = "./bl31.elf" fit_its = sys.stdout + if "BL31" in os.environ: + bl31_elf=os.getenv("BL31"); + elif os.path.isfile("./bl31.elf"): + bl31_elf = "./bl31.elf" + else: + os.system("echo 'int main(){}' > bl31.c") + os.system("${CROSS_COMPILE}gcc -c bl31.c -o bl31.elf") + bl31_elf = "./bl31.elf" + logging.basicConfig(format='%(levelname)s:%(message)s', level=logging.DEBUG) + logging.warning(' BL31 file bl31.elf NOT found, resulting binary is non-functional') + logging.warning(' Please read Building section in doc/README.rockchip') opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h") for opt, val in opts: diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 50680ce606..c5dcd061cf 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -99,21 +99,7 @@ config TARGET_VYASA_RK3288 bool "Vyasa-RK3288" select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER - select SUPPORT_TPL select TPL - select TPL_BOOTROM_SUPPORT - select TPL_CLK - select TPL_DM - select TPL_DRIVERS_MISC_SUPPORT - select TPL_LIBCOMMON_SUPPORT - select TPL_LIBGENERIC_SUPPORT - select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL - select TPL_OF_CONTROL - select TPL_OF_PLATDATA - select TPL_RAM - select TPL_REGMAP - select TPL_SERIAL_SUPPORT - select TPL_SYSCON help Vyasa is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It @@ -132,6 +118,7 @@ config TARGET_ROCK2 config TARGET_TINKER_RK3288 bool "Tinker-RK3288" select BOARD_LATE_INIT + select TPL help Tinker is a RK3288-based development board with 2 USB ports, HDMI, micro-SD card, audio, Gigabit Ethernet. It also includes on-board diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c new file mode 100644 index 0000000000..7f49d056a0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 800ca80022..890d80025f 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -11,13 +11,16 @@ #include <spl.h> #include <spl_gpio.h> #include <syscon.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/periph.h> #include <asm/arch-rockchip/sys_proto.h> +#include <power/regulator.h> #include <dm/pinctrl.h> void board_return_to_bootrom(void) @@ -161,7 +164,7 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - printascii("U-Boot SPL board init\n"); + debug("U-Boot SPL board init\n"); #endif ret = spl_early_init(); @@ -202,6 +205,66 @@ void board_init_f(ulong dummy) } } +#if defined(SPL_GPIO_SUPPORT) +static void rk3399_force_power_on_reset(void) +{ + ofnode node; + struct gpio_desc sysreset_gpio; + + debug("%s: trying to force a power-on reset\n", __func__); + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } + + if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, + &sysreset_gpio, GPIOD_IS_OUT)) { + debug("%s: could not find a /config/sysreset-gpio\n", __func__); + return; + } + + dm_gpio_set_value(&sysreset_gpio, 1); +} +#endif + +void spl_board_init(void) +{ +#if defined(SPL_GPIO_SUPPORT) + struct rk3399_cru *cru = rockchip_get_cru(); + + /* + * The RK3399 resets only 'almost all logic' (see also in the TRM + * "3.9.4 Global software reset"), when issuing a software reset. + * This may cause issues during boot-up for some configurations of + * the application software stack. + * + * To work around this, we test whether the last reset reason was + * a power-on reset and (if not) issue an overtemp-reset to reset + * the entire module. + * + * While this was previously fixed by modifying the various places + * that could generate a software reset (e.g. U-Boot's sysreset + * driver, the ATF or Linux), we now have it here to ensure that + * we no longer have to track this through the various components. + */ + if (cru->glb_rst_st != 0) + rk3399_force_power_on_reset(); +#endif + +#if defined(SPL_DM_REGULATOR) + /* + * Turning the eMMC and SPI back on (if disabled via the Qseven + * BIOS_ENABLE) signal is done through a always-on regulator). + */ + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif + + preloader_console_init(); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c index 86d3ffe97c..4a301249b4 100644 --- a/arch/arm/mach-rockchip/rk3399-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -8,6 +8,7 @@ #include <dm.h> #include <ram.h> #include <spl.h> +#include <version.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> @@ -46,7 +47,7 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - printascii("U-Boot TPL board init\n"); + debug("U-Boot TPL board init\n"); #endif ret = spl_early_init(); if (ret) { @@ -73,6 +74,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_BOOTROM; } +void spl_board_init(void) +{ + puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " + U_BOOT_TIME " " U_BOOT_TZ ")\n"); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 6ae31d3a1f..41338a1a33 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -18,7 +18,7 @@ int arch_cpu_init(void) */ #if defined(CONFIG_STM32F4) { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_16MB }, + O_I_WB_RD_WR_ALLOC, REGION_512MB }, #endif { 0x90000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index 9fe3eaadf1..e56e1f679c 100644 --- a/arch/arm/mach-uniphier/arm32/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -16,9 +16,19 @@ #include CONFIG_DEBUG_LL_INCLUDE #endif +#define SG_REVISION_TYPE_SHIFT 16 +#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT) #define BAUDRATE 115200 #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) +.macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd + ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) + ldr \rd, [\ra] + and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32)) + orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32)) + str \rd, [\ra] +.endm + ENTRY(debug_ll_init) ldr r0, =SG_REVISION ldr r1, [r0] diff --git a/arch/arm/mach-uniphier/debug-uart/Makefile b/arch/arm/mach-uniphier/debug-uart/Makefile index 5d78db58cb..81e9314a50 100644 --- a/arch/arm/mach-uniphier/debug-uart/Makefile +++ b/arch/arm/mach-uniphier/debug-uart/Makefile @@ -7,8 +7,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += debug-uart-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += debug-uart-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += debug-uart-ld6b.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += debug-uart-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += debug-uart-ld20.o endif obj-y += debug-uart.o diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c deleted file mode 100644 index b742feb4b0..0000000000 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> - */ - -#include <config.h> -#include <linux/kernel.h> -#include <linux/io.h> - -#include "../sc64-regs.h" -#include "../sg-regs.h" -#include "debug-uart.h" - -#define UNIPHIER_LD20_UART_CLK 58820000 - -unsigned int uniphier_ld20_debug_uart_init(void) -{ - u32 tmp; - - sg_set_iectrl(54); /* TXD0 */ - sg_set_iectrl(58); /* TXD1 */ - sg_set_iectrl(90); /* TXD2 */ - sg_set_iectrl(94); /* TXD3 */ - sg_set_pinsel(54, 0, 8, 4); /* TXD0 -> TXD0 */ - sg_set_pinsel(58, 1, 8, 4); /* SPITXD1 -> TXD1 */ - sg_set_pinsel(90, 1, 8, 4); /* PC0WE -> TXD2 */ - sg_set_pinsel(94, 1, 8, 4); /* PCD00 -> TXD3 */ - - tmp = readl(SC_CLKCTRL4); - tmp |= SC_CLKCTRL4_PERI; - writel(tmp, SC_CLKCTRL4); - - return DIV_ROUND_CLOSEST(UNIPHIER_LD20_UART_CLK, 16 * CONFIG_BAUDRATE); -} diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index 992b4a9857..bc96b2e7be 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -8,6 +8,7 @@ #include <linux/io.h> #include <linux/serial_reg.h> +#include "../sg-regs.h" #include "../soc-info.h" #include "debug-uart.h" @@ -26,8 +27,36 @@ static void _debug_uart_putc(int c) writel(c, base + UNIPHIER_UART_TX); } +#ifdef CONFIG_SPL_BUILD +void sg_set_pinsel(unsigned int pin, unsigned int muxval, + unsigned int mux_bits, unsigned int reg_stride) +{ + unsigned int shift = pin * mux_bits % 32; + unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; + u32 mask = (1U << mux_bits) - 1; + u32 tmp; + + tmp = readl(reg); + tmp &= ~(mask << shift); + tmp |= (mask & muxval) << shift; + writel(tmp, reg); +} + +void sg_set_iectrl(unsigned int pin) +{ + unsigned int bit = pin % 32; + unsigned long reg = SG_IECTRL + pin / 32 * 4; + u32 tmp; + + tmp = readl(reg); + tmp |= 1 << bit; + writel(tmp, reg); +} +#endif + void _debug_uart_init(void) { +#ifdef CONFIG_SPL_BUILD void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; unsigned int divisor; @@ -62,12 +91,6 @@ void _debug_uart_init(void) divisor = uniphier_ld6b_debug_uart_init(); break; #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) - case UNIPHIER_LD11_ID: - case UNIPHIER_LD20_ID: - divisor = uniphier_ld20_debug_uart_init(); - break; -#endif default: return; } @@ -75,5 +98,6 @@ void _debug_uart_init(void) writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR); writel(divisor, base + UNIPHIER_UART_LDR); +#endif } DEBUG_UART_FUNCS diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.h b/arch/arm/mach-uniphier/debug-uart/debug-uart.h index 4cbd2f08e7..f4e98c0bb0 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.h +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.h @@ -12,7 +12,9 @@ unsigned int uniphier_sld8_debug_uart_init(void); unsigned int uniphier_pro5_debug_uart_init(void); unsigned int uniphier_pxs2_debug_uart_init(void); unsigned int uniphier_ld6b_debug_uart_init(void); -unsigned int uniphier_ld11_debug_uart_init(void); -unsigned int uniphier_ld20_debug_uart_init(void); + +void sg_set_pinsel(unsigned int pin, unsigned int muxval, + unsigned int mux_bits, unsigned int reg_stride); +void sg_set_iectrl(unsigned int pin); #endif /* _MACH_DEBUG_UART_H */ diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 7e7c1d98db..fa4b3e386b 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -7,6 +7,7 @@ #include <common.h> #include <linux/errno.h> +#include <linux/io.h> #include <linux/kernel.h> #include <linux/printk.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index b105335f69..28de19c039 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -12,10 +12,6 @@ #define SC_BASE_ADDR 0x61840000 -#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110) -#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1) -#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0) - #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) #define SC_DPLLCTRL_SSC_EN (0x1 << 31) #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 0497655fb5..39ffed5885 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -87,54 +87,4 @@ #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16) #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16) -#ifdef __ASSEMBLY__ - - .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd - ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) - ldr \rd, [\ra] - and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32)) - orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32)) - str \rd, [\ra] - .endm - -#else - -#include <linux/types.h> -#include <linux/io.h> - -static inline void sg_set_pinsel(unsigned pin, unsigned muxval, - unsigned mux_bits, unsigned reg_stride) -{ - unsigned shift = pin * mux_bits % 32; - unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; - u32 mask = (1U << mux_bits) - 1; - u32 tmp; - - tmp = readl(reg); - tmp &= ~(mask << shift); - tmp |= (mask & muxval) << shift; - writel(tmp, reg); -} - -static inline void sg_set_iectrl(unsigned pin) -{ - unsigned bit = pin % 32; - unsigned long reg = SG_IECTRL + pin / 32 * 4; - u32 tmp; - - tmp = readl(reg); - tmp |= 1 << bit; - writel(tmp, reg); -} - -static inline void sg_set_iectrl_range(unsigned min, unsigned max) -{ - int i; - - for (i = min; i <= max; i++) - sg_set_iectrl(i); -} - -#endif /* __ASSEMBLY__ */ - #endif /* UNIPHIER_SG_REGS_H */ |