diff options
Diffstat (limited to 'arch/mips/cpu/mips32')
| -rw-r--r-- | arch/mips/cpu/mips32/cache.S | 17 | ||||
| -rw-r--r-- | arch/mips/cpu/mips32/start.S | 32 | ||||
| -rw-r--r-- | arch/mips/cpu/mips32/time.c | 5 |
3 files changed, 30 insertions, 24 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 117fc56df7..12f656cad0 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -18,7 +18,7 @@ #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT #endif -#define RA t8 +#define RA t9 /* * 16kB is the maximum size of instruction and data caches on MIPS 4K, @@ -128,8 +128,7 @@ NESTED(mips_cache_reset, 0, ra) move RA, ra li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE - li t4, CONFIG_SYS_CACHELINE_SIZE - move t5, t4 + li t8, CONFIG_SYS_CACHELINE_SIZE li v0, MIPS_MAX_CACHE_SIZE @@ -156,17 +155,17 @@ NESTED(mips_cache_reset, 0, ra) * Initialize the I-cache first, */ move a1, t2 - move a2, t4 - PTR_LA t7, mips_init_icache - jalr t7 + move a2, t8 + PTR_LA v1, mips_init_icache + jalr v1 /* * then initialize D-cache. */ move a1, t3 - move a2, t5 - PTR_LA t7, mips_init_dcache - jalr t7 + move a2, t8 + PTR_LA v1, mips_init_dcache + jalr v1 jr RA END(mips_cache_reset) diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index b08a897af0..70ad198cc9 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -41,7 +41,7 @@ _start: nop .org 0x10 -#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG +#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) /* * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to * access external NOR flashes. If the board boots from NOR flash the @@ -51,6 +51,12 @@ _start: */ .word CONFIG_SYS_XWAY_EBU_BOOTCFG .word 0x0 +#elif defined(CONFIG_QEMU_MALTA) + /* + * Linux expects the Board ID here. + */ + .word 0x00000420 # 0x420 (Malta Board with CoreLV) + .word 0x00000000 #endif .org 0x200 @@ -199,19 +205,19 @@ in_ram: * generated by GNU ld. Skip these reserved entries from relocation. */ lw t3, -4(t0) # t3 <-- num_got_entries - lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_ - add t4, s1 # t4 now holds relocated _G_O_T_ - addi t4, t4, 8 # skipping first two entries + lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + add t8, s1 # t8 now holds relocated _G_O_T_ + addi t8, t8, 8 # skipping first two entries li t2, 2 1: - lw t1, 0(t4) + lw t1, 0(t8) beqz t1, 2f add t1, s1 - sw t1, 0(t4) + sw t1, 0(t8) 2: addi t2, 1 blt t2, t3, 1b - addi t4, 4 + addi t8, 4 /* Update dynamic relocations */ lw t1, -16(t0) # t1 <-- __rel_dyn_start @@ -221,19 +227,19 @@ in_ram: addi t1, 8 1: - lw t3, -4(t1) # t3 <-- relocation info + lw t8, -4(t1) # t8 <-- relocation info - sub t3, 3 - bnez t3, 2f # skip non R_MIPS_REL32 entries + li t3, 3 + bne t8, t3, 2f # skip non R_MIPS_REL32 entries nop lw t3, -8(t1) # t3 <-- location to fix up in FLASH - lw t4, 0(t3) # t4 <-- original pointer - add t4, s1 # t4 <-- adjusted pointer + lw t8, 0(t3) # t8 <-- original pointer + add t8, s1 # t8 <-- adjusted pointer add t3, s1 # t3 <-- location to fix up in RAM - sw t4, 0(t3) + sw t8, 0(t3) 2: blt t1, t2, 1b diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c index 9f5cea4d8f..386f45a1b0 100644 --- a/arch/mips/cpu/mips32/time.c +++ b/arch/mips/cpu/mips32/time.c @@ -11,7 +11,8 @@ static unsigned long timestamp; /* how many counter cycles in a jiffy */ -#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ +#define CYCLES_PER_JIFFY \ + (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ /* * timer without interrupts @@ -38,7 +39,7 @@ ulong get_timer(ulong base) } write_c0_compare(expirelo); - return (timestamp - base); + return timestamp - base; } void __udelay(unsigned long usec) |