diff options
Diffstat (limited to 'arch/mips/dts/ocelot_pcb120.dts')
| -rw-r--r-- | arch/mips/dts/ocelot_pcb120.dts | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts index 658719e684..e608029a3f 100644 --- a/arch/mips/dts/ocelot_pcb120.dts +++ b/arch/mips/dts/ocelot_pcb120.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mscc,ocelot_pcb.dtsi" +#include <dt-bindings/mscc/ocelot_data.h> / { model = "Ocelot PCB120 Reference Board"; @@ -86,3 +87,77 @@ mscc,sgpio-ports = <0x000FFFFF>; }; +&mdio0 { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <3>; + }; + phy5: ethernet-phy@5 { + reg = <2>; + }; + phy6: ethernet-phy@6 { + reg = <1>; + }; + phy7: ethernet-phy@7 { + reg = <0>; + }; +}; + +&mdio1 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <3>; + }; + phy1: ethernet-phy@1 { + reg = <2>; + }; + phy2: ethernet-phy@2 { + reg = <1>; + }; + phy3: ethernet-phy@3 { + reg = <0>; + }; +}; + +&switch { + ethernet-ports { + port0: port@0 { + reg = <5>; + phy-handle = <&phy0>; + phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <9>; + phy-handle = <&phy1>; + phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <6>; + phy-handle = <&phy2>; + phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <4>; + phy-handle = <&phy3>; + phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>; + }; + port4: port@4 { + reg = <3>; + phy-handle = <&phy4>; + }; + port5: port@5 { + reg = <2>; + phy-handle = <&phy5>; + }; + port6: port@6 { + reg = <1>; + phy-handle = <&phy6>; + }; + port7: port@7 { + reg = <0>; + phy-handle = <&phy7>; + }; + }; +}; |