diff options
Diffstat (limited to 'arch/mips/dts')
29 files changed, 1099 insertions, 7 deletions
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index b447141f87..647d2bf0d5 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb +dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi index 85fb14b13b..37354324fe 100644 --- a/arch/mips/dts/ar933x.dtsi +++ b/arch/mips/dts/ar933x.dtsi @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> */ -#include <dt-bindings/interrupt-controller/irq.h> #include "skeleton.dtsi" / { @@ -68,7 +67,6 @@ uart0: uart@18020000 { compatible = "qca,ar9330-uart"; reg = <0x18020000 0x20>; - interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -103,7 +101,6 @@ spi0: spi@1f000000 { compatible = "qca,ar7100-spi"; reg = <0x1f000000 0x10>; - interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; diff --git a/arch/mips/dts/brcm,bcm6318.dtsi b/arch/mips/dts/brcm,bcm6318.dtsi index f75988be12..d678dab242 100644 --- a/arch/mips/dts/brcm,bcm6318.dtsi +++ b/arch/mips/dts/brcm,bcm6318.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/bcm6318-clock.h> +#include <dt-bindings/dma/bcm6318-dma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power-domain/bcm6318-power-domain.h> #include <dt-bindings/reset/bcm6318-reset.h> @@ -54,6 +55,12 @@ reg = <0x10000004 0x4>; #clock-cells = <1>; }; + + ubus_clk: ubus-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000008 0x4>; + #clock-cells = <1>; + }; }; ubus { @@ -182,5 +189,36 @@ status = "disabled"; }; + + enet: ethernet@10080000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10080000 0x8000>; + clocks = <&periph_clk BCM6318_CLK_ROBOSW250>, + <&periph_clk BCM6318_CLK_ROBOSW025>, + <&ubus_clk BCM6318_UCLK_ROBOSW>; + resets = <&periph_rst BCM6318_RST_ENETSW>, + <&periph_rst BCM6318_RST_EPHY>; + dmas = <&iudma BCM6318_DMA_ENETSW_RX>, + <&iudma BCM6318_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <5>; + + status = "disabled"; + }; + + iudma: dma-controller@10088000 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x10088000 0x80>, + <0x10088200 0x80>, + <0x10088400 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 62c440e675..f8a72ef535 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/bcm63268-clock.h> +#include <dt-bindings/dma/bcm63268-dma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power-domain/bcm63268-power-domain.h> #include <dt-bindings/reset/bcm63268-reset.h> @@ -217,5 +218,42 @@ reg = <0x10003000 0x894>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@1000d800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10700000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10700000 0x10000>; + clocks = <&periph_clk BCM63268_CLK_GMAC>, + <&periph_clk BCM63268_CLK_ROBOSW>, + <&periph_clk BCM63268_CLK_ROBOSW250>, + <&timer_clk BCM63268_TCLK_EPHY1>, + <&timer_clk BCM63268_TCLK_EPHY2>, + <&timer_clk BCM63268_TCLK_EPHY3>, + <&timer_clk BCM63268_TCLK_GPHY>; + resets = <&periph_rst BCM63268_RST_ENETSW>, + <&periph_rst BCM63268_RST_EPHY>, + <&periph_rst BCM63268_RST_GPHY>; + dmas = <&iudma BCM63268_DMA_ENETSW_RX>, + <&iudma BCM63268_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,rgmii-override; + brcm,rgmii-timing; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index e00a2950e2..50beed4171 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/bcm6328-clock.h> +#include <dt-bindings/dma/bcm6328-dma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power-domain/bcm6328-power-domain.h> #include <dt-bindings/reset/bcm6328-reset.h> @@ -187,5 +188,34 @@ reg = <0x10003000 0x864>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@1000d800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10e00000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10e00000 0x10000>; + clocks = <&periph_clk BCM6328_CLK_ROBOSW>; + resets = <&periph_rst BCM6328_RST_ENETSW>, + <&periph_rst BCM6328_RST_EPHY>; + dmas = <&iudma BCM6328_DMA_ENETSW_RX>, + <&iudma BCM6328_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <5>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index bbd58cf803..c547e949dd 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/bcm6338-clock.h> +#include <dt-bindings/dma/bcm6338-dma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/reset/bcm6338-reset.h> #include "skeleton.dtsi" @@ -130,5 +131,33 @@ reg = <0xfffe3100 0x38>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@fffe2400 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe2400 0x1c>, + <0xfffe2500 0x60>, + <0xfffe2600 0x60>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <6>; + resets = <&periph_rst BCM6338_RST_DMAMEM>; + }; + + enet: ethernet@fffe2800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe2800 0x2dc>; + clocks = <&periph_clk BCM6338_CLK_ENET>; + resets = <&periph_rst BCM6338_RST_ENET>; + dmas = <&iudma BCM6338_DMA_ENET_RX>, + <&iudma BCM6338_DMA_ENET_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi index cc80bbc808..79e7bd892b 100644 --- a/arch/mips/dts/brcm,bcm6348.dtsi +++ b/arch/mips/dts/brcm,bcm6348.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/bcm6348-clock.h> +#include <dt-bindings/dma/bcm6348-dma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/reset/bcm6348-reset.h> #include "skeleton.dtsi" @@ -159,5 +160,46 @@ reg = <0xfffe2300 0x38>; u-boot,dm-pre-reloc; }; + + enet0: ethernet@fffe6000 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe6000 0x2dc>; + dmas = <&iudma BCM6348_DMA_ENET0_RX>, + <&iudma BCM6348_DMA_ENET0_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + enet1: ethernet@fffe6800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe6800 0x2dc>; + dmas = <&iudma BCM6348_DMA_ENET1_RX>, + <&iudma BCM6348_DMA_ENET1_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + iudma: dma-controller@fffe7000 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe7000 0x1c>, + <0xfffe7100 0x40>, + <0xfffe7200 0x40>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&periph_clk BCM6348_CLK_ENET>; + resets = <&periph_rst BCM6348_RST_ENET>, + <&periph_rst BCM6348_RST_DMAMEM>; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 0617b46e92..5e9c9ad769 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/bcm6358-clock.h> +#include <dt-bindings/dma/bcm6358-dma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/reset/bcm6358-reset.h> #include "skeleton.dtsi" @@ -190,5 +191,50 @@ status = "disabled"; }; + + enet0: ethernet@fffe4000 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe4000 0x2dc>; + clocks = <&periph_clk BCM6358_CLK_ENET0>; + dmas = <&iudma BCM6358_DMA_ENET0_RX>, + <&iudma BCM6358_DMA_ENET0_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + enet1: ethernet@fffe4800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe4800 0x2dc>; + clocks = <&periph_clk BCM6358_CLK_ENET1>; + dmas = <&iudma BCM6358_DMA_ENET1_RX>, + <&iudma BCM6358_DMA_ENET1_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + iudma: dma-controller@fffe5000 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe5000 0x24>, + <0xfffe5100 0x80>, + <0xfffe5200 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + clocks = <&periph_clk BCM6358_CLK_EMUSB>, + <&periph_clk BCM6358_CLK_USBSU>, + <&periph_clk BCM6358_CLK_EPHY>; + resets = <&periph_rst BCM6358_RST_ENET>, + <&periph_rst BCM6358_RST_EPHY>; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi index 3047b82b21..c77b80a4cc 100644 --- a/arch/mips/dts/brcm,bcm6362.dtsi +++ b/arch/mips/dts/brcm,bcm6362.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/bcm6362-clock.h> +#include <dt-bindings/dma/bcm6362-dma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power-domain/bcm6362-power-domain.h> #include <dt-bindings/reset/bcm6362-reset.h> @@ -211,5 +212,36 @@ reg = <0x10003000 0x864>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@1000d800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10e00000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10e00000 0x10000>; + clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>, + <&periph_clk BCM6362_CLK_SWPKT_SAR>, + <&periph_clk BCM6362_CLK_ROBOSW>; + resets = <&periph_rst BCM6362_RST_ENETSW>, + <&periph_rst BCM6362_RST_EPHY>; + dmas = <&iudma BCM6362_DMA_ENETSW_RX>, + <&iudma BCM6362_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <6>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi index 65d769ab4f..89590d6ff9 100644 --- a/arch/mips/dts/brcm,bcm6368.dtsi +++ b/arch/mips/dts/brcm,bcm6368.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/bcm6368-clock.h> +#include <dt-bindings/dma/bcm6368-dma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/reset/bcm6368-reset.h> #include "skeleton.dtsi" @@ -192,5 +193,36 @@ status = "disabled"; }; + + iudma: dma-controller@10006800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x10006800 0x80>, + <0x10006a00 0x80>, + <0x10006c00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10f00000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10f00000 0x10000>; + clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>, + <&periph_clk BCM6368_CLK_SWPKT_SAR>, + <&periph_clk BCM6368_CLK_ROBOSW>; + resets = <&periph_rst BCM6368_RST_SWITCH>, + <&periph_rst BCM6368_RST_EPHY>; + dmas = <&iudma BCM6368_DMA_ENETSW_RX>, + <&iudma BCM6368_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <6>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts new file mode 100644 index 0000000000..8d6417af73 --- /dev/null +++ b/arch/mips/dts/ci20.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "jz4780.dtsi" + +/ { + compatible = "img,ci20", "ingenic,jz4780"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial4:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000 + 0x30000000 0x30000000>; + }; +}; + +&ext { + clock-frequency = <48000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&nemc { + status = "okay"; + + nandc: nand-controller@1 { + compatible = "ingenic,jz4780-nand"; + reg = <1 0 0x1000000>; + + #address-cells = <1>; + #size-cells = <0>; + + ingenic,bch-controller = <&bch>; + + ingenic,nemc-tAS = <10>; + ingenic,nemc-tAH = <5>; + ingenic,nemc-tBP = <10>; + ingenic,nemc-tAW = <15>; + ingenic,nemc-tSTRV = <100>; + + nand@1 { + reg = <1>; + + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x0 0x0 0x800000>; + }; + + partition@0x800000 { + label = "u-boot"; + reg = <0x0 0x800000 0x0 0x200000>; + }; + + partition@0xa00000 { + label = "u-boot-env"; + reg = <0x0 0xa00000 0x0 0x200000>; + }; + + partition@0xc00000 { + label = "boot"; + reg = <0x0 0xc00000 0x0 0x4000000>; + }; + + partition@0x8c00000 { + label = "system"; + reg = <0x0 0x4c00000 0x1 0xfb400000>; + }; + }; + }; + }; +}; + +&bch { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,ar-5315u.dts b/arch/mips/dts/comtrend,ar-5315u.dts index 45570189d0..eb60aaa8d5 100644 --- a/arch/mips/dts/comtrend,ar-5315u.dts +++ b/arch/mips/dts/comtrend,ar-5315u.dts @@ -24,6 +24,38 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@0 { + compatible = "brcm,enetsw-port"; + reg = <0>; + label = "fe4"; + brcm,phy-id = <1>; + }; + + port@1 { + compatible = "brcm,enetsw-port"; + reg = <1>; + label = "fe3"; + brcm,phy-id = <2>; + }; + + port@2 { + compatible = "brcm,enetsw-port"; + reg = <2>; + label = "fe2"; + brcm,phy-id = <3>; + }; + + port@3 { + compatible = "brcm,enetsw-port"; + reg = <3>; + label = "fe1"; + brcm,phy-id = <4>; + }; +}; + &leds { status = "okay"; diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts index e993b5cd89..03e3851ab1 100644 --- a/arch/mips/dts/comtrend,ar-5387un.dts +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -24,6 +24,38 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@0 { + compatible = "brcm,enetsw-port"; + reg = <0>; + label = "fe1"; + brcm,phy-id = <1>; + }; + + port@1 { + compatible = "brcm,enetsw-port"; + reg = <1>; + label = "fe2"; + brcm,phy-id = <2>; + }; + + port@2 { + compatible = "brcm,enetsw-port"; + reg = <2>; + label = "fe3"; + brcm,phy-id = <3>; + }; + + port@3 { + compatible = "brcm,enetsw-port"; + reg = <3>; + label = "fe4"; + brcm,phy-id = <4>; + }; +}; + &leds { status = "okay"; diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts index 25747ca95d..f6b8a94e25 100644 --- a/arch/mips/dts/comtrend,ct-5361.dts +++ b/arch/mips/dts/comtrend,ct-5361.dts @@ -34,6 +34,18 @@ }; }; +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts index 8c6a4a1eac..512cb52de3 100644 --- a/arch/mips/dts/comtrend,vr-3032u.dts +++ b/arch/mips/dts/comtrend,vr-3032u.dts @@ -24,6 +24,38 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@0 { + compatible = "brcm,enetsw-port"; + reg = <0>; + label = "fe2"; + brcm,phy-id = <1>; + }; + + port@1 { + compatible = "brcm,enetsw-port"; + reg = <1>; + label = "fe3"; + brcm,phy-id = <2>; + }; + + port@2 { + compatible = "brcm,enetsw-port"; + reg = <2>; + label = "fe4"; + brcm,phy-id = <3>; + }; + + port@3 { + compatible = "brcm,enetsw-port"; + reg = <3>; + label = "fe1"; + brcm,phy-id = <4>; + }; +}; + &leds { status = "okay"; brcm,serial-leds; diff --git a/arch/mips/dts/comtrend,wap-5813n.dts b/arch/mips/dts/comtrend,wap-5813n.dts index bd41dab9f8..7e835b28d2 100644 --- a/arch/mips/dts/comtrend,wap-5813n.dts +++ b/arch/mips/dts/comtrend,wap-5813n.dts @@ -54,6 +54,20 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@4 { + compatible = "brcm,enetsw-port"; + reg = <4>; + label = "rgmii"; + brcm,phy-id = <0xff>; + speed = <1000>; + full-duplex; + bypass-link; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts index 60455c2ff8..6a7fc1df4b 100644 --- a/arch/mips/dts/huawei,hg556a.dts +++ b/arch/mips/dts/huawei,hg556a.dts @@ -93,6 +93,18 @@ status = "okay"; }; +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi new file mode 100644 index 0000000000..f62a7a95f8 --- /dev/null +++ b/arch/mips/dts/jz4780.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <dt-bindings/clock/jz4780-cgu.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ingenic,jz4780"; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4780-intc"; + reg = <0x10001000 0x50>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + ext: ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + rtc: rtc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + cgu: jz4780-cgu@10000000 { + compatible = "ingenic,jz4780-cgu"; + reg = <0x10000000 0x100>; + + clocks = <&ext>, <&rtc>; + clock-names = "ext", "rtc"; + + #clock-cells = <1>; + }; + + mmc0: mmc@13450000 { + compatible = "ingenic,jz4780-mmc"; + reg = <0x13450000 0x1000>; + + status = "disabled"; + + clocks = <&cgu JZ4780_CLK_MSC0>; + clock-names = "mmc"; + }; + + mmc1: mmc@13460000 { + compatible = "ingenic,jz4780-mmc"; + reg = <0x13460000 0x1000>; + + clocks = <&cgu JZ4780_CLK_MSC1>; + clock-names = "mmc"; + + status = "disabled"; + }; + + uart0: serial@10030000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10030000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <51>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART0>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart1: serial@10031000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10031000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <50>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART1>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart2: serial@10032000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10032000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <49>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart3: serial@10033000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10033000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <48>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART3>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart4: serial@10034000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10034000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <34>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART4>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + status = "disabled"; + }; + + bch: bch@134d0000 { + compatible = "ingenic,jz4780-bch"; + reg = <0x134d0000 0x10000>; + + clocks = <&cgu JZ4780_CLK_BCH>; + + status = "disabled"; + }; +}; diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts new file mode 100644 index 0000000000..74f9274c21 --- /dev/null +++ b/arch/mips/dts/luton_pcb091.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,luton.dtsi" + +/ { + model = "Luton10 PCB091 Reference Board"; + compatible = "mscc,luton-pcb091", "mscc,luton"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + spi-cs-high; + }; +}; + diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi new file mode 100644 index 0000000000..6a4ad2a5be --- /dev/null +++ b/arch/mips/dts/mscc,luton.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,luton"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <208333333>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x60000000 0x10200000>; + + uart0: serial@10100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + + compatible = "ns16550a"; + reg = <0x10100000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + gpio: pinctrl@70068 { + compatible = "mscc,luton-pinctrl"; + reg = <0x70068 0x68>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 32>; + + uart_pins: uart-pins { + pins = "GPIO_30", "GPIO_31"; + function = "uart"; + }; + + }; + + gpio_spi_bitbang: gpio@10000064 { + compatible = "mscc,spi-bitbang-gpio"; + reg = <0x10000064 0x4>; + gpio-controller; + #gpio-cells = <2>; + + }; + + spi0: spi-bitbang { + compatible = "spi-gpio"; + status = "okay"; + gpio-sck = <&gpio_spi_bitbang 6 0>; + gpio-miso = <&gpio_spi_bitbang 0 0>; + gpio-mosi = <&gpio_spi_bitbang 5 0>; + cs-gpios = <&gpio_spi_bitbang 1 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi new file mode 100644 index 0000000000..87b4736285 --- /dev/null +++ b/arch/mips/dts/mscc,ocelot.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,ocelot"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + clocks = <&cpu_clk>; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + cpu_clk: cpu-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x70000000 0x2000000>; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@0 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x0 0x2c>; + }; + + intc: interrupt-controller@70 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + uart2: serial@100800 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100800 0x20>; + interrupts = <7>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + spi0: spi-master@101000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-ssi"; + reg = <0x101000 0x40>; + num-chipselect = <4>; + bus-num = <0>; + reg-io-width = <4>; + reg-shift = <2>; + spi-max-frequency = <18000000>; /* input clock */ + clocks = <&ahb_clk>; + + status = "disabled"; + }; + + reset@1070008 { + compatible = "mscc,ocelot-chip-reset"; + reg = <0x1070008 0x4>; + }; + + gpio: pinctrl@1070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x1070034 0x68>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + + spi_cs1_pin: spi-cs1-pin { + pins = "GPIO_8"; + function = "si"; + }; + + spi_cs2_pin: spi-cs2-pin { + pins = "GPIO_9"; + function = "si"; + }; + + spi_cs3_pin: spi-cs3-pin { + pins = "GPIO_16"; + function = "si"; + }; + + spi_cs4_pin: spi-cs4-pin { + pins = "GPIO_17"; + function = "si"; + }; + }; + }; +}; diff --git a/arch/mips/dts/mscc,ocelot_pcb.dtsi b/arch/mips/dts/mscc,ocelot_pcb.dtsi new file mode 100644 index 0000000000..90725d3b94 --- /dev/null +++ b/arch/mips/dts/mscc,ocelot_pcb.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,ocelot.dtsi" + +/ { + compatible = "mscc,ocelot"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi_cs1_pin>; + pinctrl-names = "default"; + + spi-flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + }; + + spi-nand@1 { + compatible = "spi-nand"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <1>; /* CS1 */ + }; +}; diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts index 322d1567ff..2b72491f0b 100644 --- a/arch/mips/dts/netgear,dgnd3700v2.dts +++ b/arch/mips/dts/netgear,dgnd3700v2.dts @@ -43,6 +43,20 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@4 { + compatible = "brcm,enetsw-port"; + reg = <4>; + label = "rgmii"; + brcm,phy-id = <0xff>; + speed = <1000>; + full-duplex; + bypass-link; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/arch/mips/dts/nexys4ddr.dts b/arch/mips/dts/nexys4ddr.dts index e254ab1eaa..6de8584ea7 100644 --- a/arch/mips/dts/nexys4ddr.dts +++ b/arch/mips/dts/nexys4ddr.dts @@ -40,7 +40,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { - compatible = <0x0007c0f0 0xfffffff0>; device_type = "ethernet-phy"; reg = <1>; } ; diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts new file mode 100644 index 0000000000..47d305a614 --- /dev/null +++ b/arch/mips/dts/ocelot_pcb120.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,ocelot_pcb.dtsi" + +/ { + model = "Ocelot PCB120 Reference Board"; + compatible = "mscc,ocelot-pcb120", "mscc,ocelot"; +}; diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts new file mode 100644 index 0000000000..17d8d326ce --- /dev/null +++ b/arch/mips/dts/ocelot_pcb123.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,ocelot_pcb.dtsi" + +/ { + model = "Ocelot PCB123 Reference Board"; + compatible = "mscc,ocelot-pcb123", "mscc,ocelot"; +}; diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi index 599e809c47..ba29ea287e 100644 --- a/arch/mips/dts/qca953x.dtsi +++ b/arch/mips/dts/qca953x.dtsi @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> */ -#include <dt-bindings/interrupt-controller/irq.h> #include "skeleton.dtsi" / { @@ -63,7 +62,6 @@ reg = <0x18020000 0x20>; reg-shift = <2>; clock-frequency = <25000000>; - interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -72,7 +70,6 @@ spi0: spi@1f000000 { compatible = "qca,ar7100-spi"; reg = <0x1f000000 0x10>; - interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; diff --git a/arch/mips/dts/sagem,f@st1704.dts b/arch/mips/dts/sagem,f@st1704.dts index 5300f8b6df..ec6846dd9f 100644 --- a/arch/mips/dts/sagem,f@st1704.dts +++ b/arch/mips/dts/sagem,f@st1704.dts @@ -39,6 +39,18 @@ }; }; +&enet { + status = "okay"; + phy = <&enetphy>; + phy-mode = "mii"; + + enetphy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio { status = "okay"; }; diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts index bdc6f8ae45..dfbc4148dc 100644 --- a/arch/mips/dts/sfr,nb4-ser.dts +++ b/arch/mips/dts/sfr,nb4-ser.dts @@ -53,6 +53,30 @@ status = "okay"; }; +&enet0 { + status = "okay"; + phy = <&enet0phy>; + phy-mode = "internal"; + + enet0phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio0 { status = "okay"; }; |