diff options
Diffstat (limited to 'arch/mips/lib/cache.c')
| -rw-r--r-- | arch/mips/lib/cache.c | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 91b037f87d..e305f3207a 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -10,7 +10,9 @@ #ifdef CONFIG_MIPS_L2_CACHE #include <asm/cm.h> #endif +#include <asm/io.h> #include <asm/mipsregs.h> +#include <asm/system.h> DECLARE_GLOBAL_DATA_PTR; @@ -96,6 +98,9 @@ static inline unsigned long scache_line_size(void) const unsigned int cache_ops[] = { ops }; \ unsigned int i; \ \ + if (!lsize) \ + break; \ + \ for (; addr <= aend; addr += lsize) { \ for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \ mips_cache(cache_ops[i], addr); \ @@ -116,19 +121,24 @@ void flush_cache(ulong start_addr, ulong size) /* flush I-cache & D-cache simultaneously */ cache_loop(start_addr, start_addr + size, ilsize, HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); - return; + goto ops_done; } /* flush D-cache */ cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); /* flush L2 cache */ - if (slsize) - cache_loop(start_addr, start_addr + size, slsize, - HIT_WRITEBACK_INV_SD); + cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD); /* flush I-cache */ cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); + +ops_done: + /* ensure cache ops complete before any further memory accesses */ + sync(); + + /* ensure the pipeline doesn't contain now-invalid instructions */ + instruction_hazard_barrier(); } void flush_dcache_range(ulong start_addr, ulong stop) @@ -143,8 +153,10 @@ void flush_dcache_range(ulong start_addr, ulong stop) cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); /* flush L2 cache */ - if (slsize) - cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); + cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); + + /* ensure cache ops complete before any further memory accesses */ + sync(); } void invalidate_dcache_range(ulong start_addr, ulong stop) @@ -157,8 +169,10 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) return; /* invalidate L2 cache */ - if (slsize) - cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); + cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); + + /* ensure cache ops complete before any further memory accesses */ + sync(); } |