diff options
Diffstat (limited to 'arch/mips/mach-mscc')
21 files changed, 25 insertions, 0 deletions
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 3ee589891b..b4ffd44ea4 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -4,6 +4,8 @@ */ #include <common.h> +#include <init.h> +#include <linux/bitops.h> #include <asm/io.h> #include <asm/types.h> diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c index 72c70c9e84..b12bac63c2 100644 --- a/arch/mips/mach-mscc/dram.c +++ b/arch/mips/mach-mscc/dram.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <init.h> #include <asm/io.h> #include <asm/types.h> diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c index 5e3a53372d..d6b4c5d768 100644 --- a/arch/mips/mach-mscc/gpio.c +++ b/arch/mips/mach-mscc/gpio.c @@ -5,6 +5,7 @@ #include <common.h> #include <asm/io.h> +#include <linux/bitops.h> void mscc_gpio_set_alternate(int gpio, int mode) { diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index bf75e52ec3..d52eabbd2b 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -9,6 +9,7 @@ #include <asm/cacheops.h> #include <asm/io.h> #include <asm/reboot.h> +#include <linux/bitops.h> #include <mach/common.h> #define MIPS_VCOREIII_MEMORY_DDR3 diff --git a/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h index 4a1228d29f..8d1d21b9b1 100644 --- a/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h @@ -6,6 +6,8 @@ #ifndef _MSCC_JR2_DEVCPU_GCB_H_ #define _MSCC_JR2_DEVCPU_GCB_H_ +#include <linux/bitops.h> + #define PERF_GPR 0x4 #define PERF_SOFT_RST 0x8 diff --git a/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h index 3c84edc18a..e11ad8788f 100644 --- a/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h @@ -6,6 +6,8 @@ #ifndef _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_ #define _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_ +#include <linux/bitops.h> + #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36)) #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36)) #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h index 6e0bbe2746..151bb3e6d4 100644 --- a/arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h @@ -6,6 +6,8 @@ #ifndef _MSCC_JR2_ICPU_CFG_H_ #define _MSCC_JR2_ICPU_CFG_H_ +#include <linux/bitops.h> + #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x4 diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h index a74a68593d..750a8013d1 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_DEVCPU_GCB_H_ #define _MSCC_OCELOT_DEVCPU_GCB_H_ +#include <linux/bitops.h> #define PERF_SOFT_RST 0x90 #define PERF_SOFT_RST_SOFT_SWC_RST BIT(1) diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h index 2303734894..07c4f9aeb6 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h @@ -8,6 +8,7 @@ #ifndef _MSCC_LUTON_MIIM_REGS_H_ #define _MSCC_LUTON_MIIM_REGS_H_ +#include <linux/bitops.h> #define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36)) #define MIIM_MII_CMD(gi) (0xa8 + (gi * 36)) #define MIIM_MII_DATA(gi) (0xac + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h index 9233f037bb..ded7c5fa77 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_ICPU_CFG_H_ #define _MSCC_OCELOT_ICPU_CFG_H_ +#include <linux/bitops.h> #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x4 diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h index b2a4203644..5715ec164c 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_DEVCPU_GCB_H_ #define _MSCC_OCELOT_DEVCPU_GCB_H_ +#include <linux/bitops.h> #define PERF_SOFT_RST 0x8 #define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2) diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h index 4ad92214a3..50cf073eab 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ #define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ +#include <linux/bitops.h> #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h index 04cf70bec3..fb10bf2c26 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_ICPU_CFG_H_ #define _MSCC_OCELOT_ICPU_CFG_H_ +#include <linux/bitops.h> #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x4 diff --git a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h index 9b80fdb574..43d40be716 100644 --- a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVAL_DEVCPU_GCB_H_ #define _MSCC_SERVAL_DEVCPU_GCB_H_ +#include <linux/bitops.h> #define CHIP_ID 0x0 #define PERF_GPR 0x4 diff --git a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h index a3abbc4015..e8cb1dcf9a 100644 --- a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_ #define _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_ +#include <linux/bitops.h> #define MIIM_MII_STATUS(gi) (0x5c + (gi * 36)) #define MIIM_MII_CMD(gi) (0x64 + (gi * 36)) #define MIIM_MII_DATA(gi) (0x68 + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h index b8c9d5ca49..4d4151b3d5 100644 --- a/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVAL_ICPU_CFG_H_ #define _MSCC_SERVAL_ICPU_CFG_H_ +#include <linux/bitops.h> #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x8 diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h index 493eaad1df..7d6c64f316 100644 --- a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVALT_DEVCPU_GCB_H_ #define _MSCC_SERVALT_DEVCPU_GCB_H_ +#include <linux/bitops.h> #define PERF_GPR 0x4 #define PERF_SOFT_RST 0x8 diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h index 8c67190ecb..72d7c4d08d 100644 --- a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_ #define _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_ +#include <linux/bitops.h> #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36)) #define MIIM_MII_CMD(gi) (0xcc + (gi * 36)) #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h index 491ead169f..13967f66b0 100644 --- a/arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVALT_ICPU_CFG_H_ #define _MSCC_SERVALT_ICPU_CFG_H_ +#include <linux/bitops.h> #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x8 diff --git a/arch/mips/mach-mscc/include/mach/tlb.h b/arch/mips/mach-mscc/include/mach/tlb.h index fdb554f551..ebd8ad0dc1 100644 --- a/arch/mips/mach-mscc/include/mach/tlb.h +++ b/arch/mips/mach-mscc/include/mach/tlb.h @@ -7,6 +7,7 @@ #define __ASM_MACH_TLB_H #include <asm/mipsregs.h> +#include <linux/bitops.h> #include <mach/common.h> #include <linux/sizes.h> diff --git a/arch/mips/mach-mscc/phy.c b/arch/mips/mach-mscc/phy.c index add6280e38..83d3e5bdd2 100644 --- a/arch/mips/mach-mscc/phy.c +++ b/arch/mips/mach-mscc/phy.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <log.h> #include <asm/io.h> int mscc_phy_rd_wr(u8 read, |