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-rw-r--r--arch/mips/Kconfig24
-rw-r--r--arch/mips/cpu/start.S6
2 files changed, 29 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 48e754cc46..eb00ee71bc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -270,6 +270,30 @@ config MIPS_CACHE_INDEX_BASE
Normally this is CKSEG0. If the MIPS system needs to move this block
to some SRAM or ScratchPad RAM, adapt this option accordingly.
+config MIPS_CACHE_SETUP
+ bool "Allow generic start code to initialize and setup caches"
+ default n if SKIP_LOWLEVEL_INIT
+ default y
+ help
+ This allows the generic start code to invoke the generic initialization
+ of the CPU caches. Disabling this can be useful for RAM boot scenarios
+ (EJTAG, SPL payload) or for machines which don't need cache initialization
+ or which want to provide their own cache implementation.
+
+ If unsure, say yes.
+
+config MIPS_CACHE_DISABLE
+ bool "Allow generic start code to initially disable caches"
+ default n if SKIP_LOWLEVEL_INIT
+ default y
+ help
+ This allows the generic start code to initially disable the CPU caches
+ and run uncached until the caches are initialized and enabled. Disabling
+ this can be useful on machines which don't need cache initialization or
+ which want to provide their own cache implementation.
+
+ If unsure, say yes.
+
config MIPS_RELOCATION_TABLE_SIZE
hex "Relocation table size"
range 0x100 0x10000
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index a9f8743717..0c303031ad 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -195,7 +195,7 @@ wr_done:
/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
mtc0 zero, CP0_COMPARE
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_MIPS_CACHE_DISABLE
/* Disable caches */
PTR_LA t9, mips_cache_disable
jalr t9
@@ -234,12 +234,16 @@ wr_done:
jalr t9
nop
# endif
+#endif
+#ifdef CONFIG_MIPS_CACHE_SETUP
/* Initialize caches... */
PTR_LA t9, mips_cache_reset
jalr t9
nop
+#endif
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init