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-rw-r--r--arch/powerpc/cpu/mpc83xx/initreg/Kconfig6
-rw-r--r--arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr139
-rw-r--r--arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr115
-rw-r--r--arch/powerpc/cpu/mpc83xx/initreg/initreg.h79
4 files changed, 339 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
new file mode 100644
index 0000000000..a6b42a29af
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
@@ -0,0 +1,6 @@
+menu "Initial register configuration"
+
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr"
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
new file mode 100644
index 0000000000..e6b6130de2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
@@ -0,0 +1,139 @@
+menu "LCRR - Clock Ratio Register register"
+
+if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
+
+choice
+ prompt "DLL bypass"
+
+config LCRR_DBYP_UNSET
+ bool "Don't set value"
+
+config LCRR_DBYP_PLL_ENABLED
+ bool "PLL enabled"
+
+config LCRR_DBYP_PLL_BYPASSED
+ bool "PLL bypassed"
+
+endchoice
+
+endif
+
+if ARCH_MPC834X || ARCH_MPC8360
+
+choice
+ prompt "Additional delay cycles for SDRAM control signals"
+
+config LCRR_BUFCMDC_UNSET
+ bool "Don't set value"
+
+config LCRR_BUFCMDC_4
+ bool "4"
+
+config LCRR_BUFCMDC_1
+ bool "1"
+
+config LCRR_BUFCMDC_2
+ bool "2"
+
+config LCRR_BUFCMDC_3
+ bool "3"
+
+endchoice
+
+choice
+ prompt "Extended CAS latency"
+
+config LCRR_ECL_UNSET
+ bool "Don't set value"
+
+config LCRR_ECL_4
+ bool "4"
+
+config LCRR_ECL_5
+ bool "5"
+
+config LCRR_ECL_6
+ bool "6"
+
+config LCRR_ECL_7
+ bool "7"
+
+endchoice
+
+endif # ARCH_MPC834X || ARCH_MPC8360
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address delay cycles"
+
+config LCRR_EADC_UNSET
+ bool "Don't set value"
+
+config LCRR_EADC_4
+ bool "4"
+
+config LCRR_EADC_1
+ bool "1"
+
+config LCRR_EADC_2
+ bool "2"
+
+config LCRR_EADC_3
+ bool "3"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+choice
+ prompt "System clock divider"
+
+config LCRR_CLKDIV_UNSET
+ bool "Don't set value"
+
+config LCRR_CLKDIV_2
+ bool "2"
+
+config LCRR_CLKDIV_4
+ bool "4"
+
+config LCRR_CLKDIV_8
+ bool "8"
+
+endchoice
+
+config LCRR_DBYP
+ hex
+ default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
+ default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
+
+config LCRR_BUFCMDC
+ hex
+ default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
+ default 0x10000000 if LCRR_BUFCMDC_1
+ default 0x20000000 if LCRR_BUFCMDC_2
+ default 0x30000000 if LCRR_BUFCMDC_3
+
+config LCRR_ECL
+ hex
+ default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
+ default 0x1000000 if LCRR_ECL_5
+ default 0x2000000 if LCRR_ECL_6
+ default 0x3000000 if LCRR_ECL_7
+
+config LCRR_EADC
+ hex
+ default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
+ default 0x10000 if LCRR_EADC_1
+ default 0x20000 if LCRR_EADC_2
+ default 0x30000 if LCRR_EADC_3
+
+config LCRR_CLKDIV
+ hex
+ default 0x0 if LCRR_CLKDIV_UNSET
+ default 0x2 if LCRR_CLKDIV_2
+ default 0x4 if LCRR_CLKDIV_4
+ default 0x8 if LCRR_CLKDIV_8
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
new file mode 100644
index 0000000000..f32309e6c0
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
@@ -0,0 +1,115 @@
+menu "SPCR - System priority and configuration register"
+
+choice
+ prompt "Optimize"
+
+config SPCR_OPT_UNSET
+ bool "Don't set value"
+
+config SPCR_OPT_NONE
+ bool "No performance enhancement"
+
+config SPCR_OPT_SPEC_READ
+ bool "Performance enhancement by speculative read"
+
+endchoice
+
+if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X
+
+choice
+ prompt "TSEC emergency priority"
+
+config SPCR_TSECEP_UNSET
+ bool "Don't set value"
+
+config SPCR_TSECEP_0
+ bool "Level 0 (lowest priority)"
+
+config SPCR_TSECEP_1
+ bool "Level 1"
+
+config SPCR_TSECEP_2
+ bool "Level 2"
+
+config SPCR_TSECEP_3
+ bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+if ARCH_MPC8349
+
+choice
+ prompt "TSEC1 emergency priority"
+
+config SPCR_TSEC1EP_UNSET
+ bool "Don't set value"
+
+config SPCR_TSEC1EP_0
+ bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC1EP_1
+ bool "Level 1"
+
+config SPCR_TSEC1EP_2
+ bool "Level 2"
+
+config SPCR_TSEC1EP_3
+ bool "Level 3 (highest priority)"
+
+endchoice
+
+choice
+ prompt "TSEC2 emergency priority"
+
+config SPCR_TSEC2EP_UNSET
+ bool "Don't set value"
+
+config SPCR_TSEC2EP_0
+ bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC2EP_1
+ bool "Level 1"
+
+config SPCR_TSEC2EP_2
+ bool "Level 2"
+
+config SPCR_TSEC2EP_3
+ bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+config SPCR_OPT
+ hex
+ default 0x0 if SPCR_OPT_UNSET
+ default 0x0 if SPCR_OPT_NONE
+ default 0x800000 if SPCR_OPT_SPEC_READ
+
+config SPCR_TSECEP
+ hex
+ default 0x0 if SPCR_TSECEP_UNSET
+ default 0x0 if SPCR_TSECEP_0
+ default 0x100 if SPCR_TSECEP_1
+ default 0x200 if SPCR_TSECEP_2
+ default 0x300 if SPCR_TSECEP_3
+
+config SPCR_TSEC1EP
+ hex
+ default 0x0 if SPCR_TSEC1EP_UNSET
+ default 0x0 if SPCR_TSEC1EP_0
+ default 0x100 if SPCR_TSEC1EP_1
+ default 0x200 if SPCR_TSEC1EP_2
+ default 0x300 if SPCR_TSEC1EP_3
+
+config SPCR_TSEC2EP
+ hex
+ default 0x0 if SPCR_TSEC2EP_UNSET
+ default 0x0 if SPCR_TSEC2EP_0
+ default 0x1 if SPCR_TSEC2EP_1
+ default 0x2 if SPCR_TSEC2EP_2
+ default 0x3 if SPCR_TSEC2EP_3
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
new file mode 100644
index 0000000000..63aa5c9466
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
@@ -0,0 +1,79 @@
+#define SPCR_PCIHPE_MASK 0x10000000
+#define SPCR_PCIPR_MASK 0x03000000
+#define SPCR_OPT_MASK 0x00800000
+#define SPCR_TBEN_MASK 0x00400000
+#define SPCR_COREPR_MASK 0x00300000
+#define SPCR_TSEC1DP_MASK 0x00003000
+#define SPCR_TSEC1BDP_MASK 0x00000C00
+#define SPCR_TSEC1EP_MASK 0x00000300
+#define SPCR_TSEC2DP_MASK 0x00000030
+#define SPCR_TSEC2BDP_MASK 0x0000000C
+#define SPCR_TSEC2EP_MASK 0x00000003
+#define SPCR_TSECDP_MASK 0x00003000
+#define SPCR_TSECBDP_MASK 0x00000C00
+#define SPCR_TSECEP_MASK 0x00000300
+
+ const __be32 spcr_mask =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+ SPCR_OPT_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+ SPCR_TSECEP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+ SPCR_TSEC1EP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+ SPCR_TSEC2EP_MASK |
+#endif
+ 0;
+ const __be32 spcr_val =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+ CONFIG_SPCR_OPT |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+ CONFIG_SPCR_TSECEP |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+ CONFIG_SPCR_TSEC1EP |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+ CONFIG_SPCR_TSEC2EP |
+#endif
+ 0;
+
+ const __be32 lcrr_mask =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+ LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+ LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+ LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+ LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+ LCRR_CLKDIV |
+#endif
+ 0;
+
+ const __be32 lcrr_val =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+ CONFIG_LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+ CONFIG_LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+ CONFIG_LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+ CONFIG_LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+ CONFIG_LCRR_CLKDIV |
+#endif
+ 0;