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Diffstat (limited to 'arch/powerpc/cpu/mpc83xx')
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu.c9
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu_init.c2
-rw-r--r--arch/powerpc/cpu/mpc83xx/serdes.c4
-rw-r--r--arch/powerpc/cpu/mpc83xx/spd_sdram.c4
-rw-r--r--arch/powerpc/cpu/mpc83xx/speed.c4
5 files changed, 20 insertions, 3 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 82370b5430..b29f271e9b 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -25,6 +25,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_CPU_MPC83XX
int checkcpu(void)
{
volatile immap_t *immr;
@@ -114,7 +115,9 @@ int checkcpu(void)
return 0;
}
+#endif
+#ifndef CONFIG_SYSRESET
int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
@@ -169,17 +172,17 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
return 1;
}
-
+#endif
/*
* Get timebase clock frequency (like cpu_clk in Hz)
*/
-
+#ifndef CONFIG_TIMER
unsigned long get_tbclk(void)
{
return (gd->bus_clk + 3L) / 4L;
}
-
+#endif
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index fcac9f63a8..1555205e06 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -464,6 +464,7 @@ static int print_83xx_arb_event(int force)
}
#endif /* CONFIG_DISPLAY_AER_xxxx */
+#ifndef CONFIG_CPU_MPC83XX
/*
* Figure out the cause of the reset
*/
@@ -505,3 +506,4 @@ int prt_83xx_rsr(void)
return 0;
}
+#endif
diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c
index 982a4475f0..8242f95265 100644
--- a/arch/powerpc/cpu/mpc83xx/serdes.c
+++ b/arch/powerpc/cpu/mpc83xx/serdes.c
@@ -8,6 +8,8 @@
* Author: Li Yang <leoli@freescale.com>
*/
+#ifndef CONFIG_MPC83XX_SERDES
+
#include <config.h>
#include <common.h>
#include <asm/io.h>
@@ -148,3 +150,5 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
tmp |= FSL_SRDSRSTCTL_RST;
out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
}
+
+#endif /* !CONFIG_MPC83XX_SERDES */
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index bbc8ef03c7..328a018eb6 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -10,6 +10,8 @@
* Xianghua Xiao (X.Xiao@motorola.com)
*/
+#ifndef CONFIG_MPC83XX_SDRAM
+
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
@@ -924,3 +926,5 @@ void ddr_enable_ecc(unsigned int dram_size)
__asm__ __volatile__ ("isync");
}
#endif /* CONFIG_DDR_ECC */
+
+#endif /* !CONFIG_MPC83XX_SDRAM */
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index f0945281cd..39bc1c5340 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -6,6 +6,8 @@
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*/
+#ifndef CONFIG_CLK_MPC83XX
+
#include <common.h>
#include <mpc83xx.h>
#include <command.h>
@@ -590,3 +592,5 @@ U_BOOT_CMD(clocks, 1, 0, do_clocks,
"print clock configuration",
" clocks"
);
+
+#endif