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-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile18
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c24
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c52
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c29
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c7
-rw-r--r--arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c95
-rw-r--r--arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c65
-rw-r--r--arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c65
-rw-r--r--arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c74
-rw-r--r--arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c81
-rw-r--r--arch/powerpc/cpu/mpc85xx/p1021_serdes.c64
-rw-r--r--arch/powerpc/cpu/mpc85xx/p2020_serdes.c73
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S4
-rw-r--r--arch/powerpc/cpu/mpc85xx/tlb.c6
14 files changed, 648 insertions, 9 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 63d79233d5..af7bc09b91 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,8 +66,6 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_CORENET) += liodn.o
COBJS-$(CONFIG_MP) += mp.o
-COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
-COBJS-$(CONFIG_P1022) += p1022_serdes.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_FSL_CORENET) += portals.o
@@ -77,6 +75,22 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
+
+# SoC specific SERDES support
+COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
+COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
+COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
+COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o
+COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o
+COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
+COBJS-$(CONFIG_P1011) += p1021_serdes.o
+COBJS-$(CONFIG_P1012) += p1021_serdes.o
+COBJS-$(CONFIG_P1013) += p1013_serdes.o
+COBJS-$(CONFIG_P1020) += p1021_serdes.o
+COBJS-$(CONFIG_P1021) += p1021_serdes.o
+COBJS-$(CONFIG_P1022) += p1022_serdes.o
+COBJS-$(CONFIG_P2010) += p2020_serdes.o
+COBJS-$(CONFIG_P2020) += p2020_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS = $(COBJS-y)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index d73f3d7f14..7dfa596f03 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -47,6 +47,28 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
+ puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
+#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
+ puts("Work-around for Erratum ESDHC111 enabled\n");
+#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
+ puts("Work-around for Erratum ESDHC135 enabled\n");
+#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
+ puts("Work-around for Erratum ESDHC136 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
+ puts("Work-around for Erratum CPC-A002 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
+ puts("Work-around for Erratum CPC-A003 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+ puts("Work-around for Erratum ELBC-A001 enabled\n");
+#endif
+
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 55ee36d0bc..4ef9be1b22 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,6 +34,7 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
@@ -286,6 +287,57 @@ void mpc85xx_reginfo(void)
print_lbc_regs();
}
+/* Common ddr init for non-corenet fsl 85xx platforms */
+#ifndef CONFIG_FSL_CORENET
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
+ {
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned int x = 10;
+ unsigned int i;
+
+ /*
+ * Work around to stabilize DDR DLL
+ */
+ out_be32(&gur->ddrdllcr, 0x81000000);
+ asm("sync;isync;msync");
+ udelay(200);
+ while (in_be32(&gur->ddrdllcr) != 0x81000100) {
+ setbits_be32(&gur->devdisr, 0x00010000);
+ for (i = 0; i < x; i++)
+ ;
+ clrbits_be32(&gur->devdisr, 0x00010000);
+ x++;
+ }
+ }
+#endif
+
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ /* Some boards also have sdram on the lbc */
+ lbc_sdram_init();
+
+ puts("DDR: ");
+ return dram_size;
+}
+#endif
+
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4b8faa5daf..8ece970097 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Modified by Xianghua Xiao, X.Xiao@motorola.com
@@ -40,6 +40,8 @@
DECLARE_GLOBAL_DATA_PTR;
+extern void srio_init(void);
+
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -140,6 +142,13 @@ static void enable_cpc(void)
u32 cpccfg0 = in_be32(&cpc->cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
+ setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
+ setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
+#endif
+
out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
/* Read back to sync write */
in_be32(&cpc->cpccsr0);
@@ -232,6 +241,12 @@ void cpu_init_f (void)
invalidate_cpc();
}
+/* Implement a dummy function for those platforms w/o SERDES */
+static void __fsl_serdes__init(void)
+{
+ return ;
+}
+__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
/*
* Initialize L2 as cache.
@@ -375,15 +390,25 @@ int cpu_init_r(void)
qe_reset();
#endif
-#if defined(CONFIG_SYS_HAS_SERDES)
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
+
+#ifdef CONFIG_SYS_SRIO
+ srio_init();
#endif
#if defined(CONFIG_MP)
setup_mp();
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+ {
+ void *p;
+ p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+ setbits_be32(p, 1 << (31 - 14));
+ }
+#endif
+
#ifdef CONFIG_SYS_LBC_LCRR
/*
* Modify the CLKDIV field of LCRR register to improve the writing
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 53e0596554..00fa752996 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_qe_setup(void *blob);
extern void ft_fixup_num_cores(void *blob);
+extern void ft_srio_setup(void *blob);
#ifdef CONFIG_MP
#include "mp.h"
@@ -478,4 +479,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_qportals(blob);
#endif
+
+#ifdef CONFIG_SYS_SRIO
+ ft_srio_setup(blob);
+#endif
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
new file mode 100644
index 0000000000..7c490972a5
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 8
+#define SRDS2_MAX_LANES 4
+
+static u32 serdes1_prtcl_map, serdes2_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
+ [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
+ [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
+ [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
+ [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
+ [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
+};
+
+static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
+ [0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
+ [0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
+ [0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
+ [0x6] = {PCIE3, NONE, NONE, NONE},
+ [0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3},
+};
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ int ret = (1 << device) & serdes1_prtcl_map;
+
+ if (ret)
+ return ret;
+
+ return (1 << device) & serdes2_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+
+ if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
+ serdes2_prtcl_map |= (1 << lane_prtcl);
+ }
+
+ if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
+ serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);
+
+ if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
+ serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
+}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
new file mode 100644
index 0000000000..76288cd568
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 8
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+ return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
+
+ if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
+ return ;
+ }
+
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
new file mode 100644
index 0000000000..258263739f
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 8
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+ return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
new file mode 100644
index 0000000000..f480c2609d
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 4
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x0] = {PCIE1, NONE, NONE, NONE},
+ [0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
+ [0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
+ [0x3] = {SRIO1, SRIO2, NONE, NONE},
+ [0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2},
+ [0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
+ [0x6] = {PCIE1, NONE, SRIO1, SRIO2},
+ [0x7] = {PCIE1, PCIE1, SRIO1, SRIO2},
+ [0x8] = {PCIE1, PCIE1, SRIO1, SRIO2},
+ [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
+ [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
+ [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
+ [0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2},
+ [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+ return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
new file mode 100644
index 0000000000..2ff5d9a060
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 8
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
+ [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
+ [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
+ [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
+ [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+ return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+ serdes1_prtcl_map |= (1 << SGMII_TSEC1);
+
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ serdes1_prtcl_map |= (1 << SGMII_TSEC2);
+
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ serdes1_prtcl_map |= (1 << SGMII_TSEC3);
+
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
+ serdes1_prtcl_map |= (1 << SGMII_TSEC4);
+}
diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
new file mode 100644
index 0000000000..457ab5dca8
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 4
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x0] = {PCIE1, NONE, NONE, NONE},
+ [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
+ [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
+ [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+ return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
new file mode 100644
index 0000000000..389ff6bd28
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 4
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x0] = {PCIE1, NONE, NONE, NONE},
+ [0x2] = {PCIE1, PCIE2, PCIE3, PCIE3},
+ [0x4] = {PCIE1, PCIE1, PCIE3, PCIE3},
+ [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
+ [0x7] = {SRIO2, SRIO1, NONE, NONE},
+ [0x8] = {SRIO2, SRIO2, SRIO2, SRIO2},
+ [0x9] = {SRIO2, SRIO2, SRIO2, SRIO2},
+ [0xa] = {SRIO2, SRIO2, SRIO2, SRIO2},
+ [0xb] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
+ [0xc] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
+ [0xd] = {PCIE1, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
+ [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
+ [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+ return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 945c1b8477..fa98af64b5 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
* See file CREDITS for list of people who contributed to this
@@ -753,7 +753,7 @@ dcache_disable:
lis r4,0
ori r4,r4,L1CSR0_DCE
andc r3,r3,r4
- mtspr L1CSR0,r0
+ mtspr L1CSR0,r3
isync
blr
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index e3a71aec5c..31143ba530 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -250,10 +250,14 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
int i;
unsigned int tlb_size;
+ unsigned int wimge = 0;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
u64 size, memsize = (u64)memsize_in_meg << 20;
+#ifdef CONFIG_SYS_PPC_DDR_WIMGE
+ wimge = CONFIG_SYS_PPC_DDR_WIMGE;
+#endif
size = min(memsize, CONFIG_MAX_MEM_MAPPED);
/* Convert (4^max) kB to (2^max) bytes */
@@ -277,7 +281,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
tlb_size = (camsize - 10) / 2;
set_tlb(1, ram_tlb_address, p_addr,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, wimge,
0, ram_tlb_index, tlb_size, 1);
size -= 1ULL << camsize;
generated by cgit (git 2.34.1) at 2025-01-20 22:20:41 +0000