17 files changed, 119 insertions, 4490 deletions

diff --git a/arch/powerpc/include/asm/4xx_pci.h b/arch/powerpc/include/asm/4xx_pci.h
index f686e7cb07..276a78077d 100644
--- a/arch/powerpc/include/asm/4xx_pci.h
+++ b/arch/powerpc/include/asm/4xx_pci.h
@@ -56,5 +56,7 @@ int pci_arbiter_enabled(void);
 int __pci_pre_init(struct pci_controller *hose);
 void __pci_target_init(struct pci_controller *hose);
 void __pci_master_init(struct pci_controller *hose);
+void pci_target_init(struct pci_controller *);
+void pcie_setup_hoses(int busno);
 
 #endif
diff --git a/arch/powerpc/include/asm/5xx_immap.h b/arch/powerpc/include/asm/5xx_immap.h
deleted file mode 100644
index 0a333c2ad6..0000000000
--- a/arch/powerpc/include/asm/5xx_immap.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * File:		5xx_immap.h
- *
- * Discription:		MPC555 Internal Memory Map
- *
- */
-
-#ifndef __IMMAP_5XX__
-#define __IMMAP_5XX__
-
-/* System Configuration Registers.
-*/
-typedef	struct sys_conf {
-	uint sc_siumcr;
-	uint sc_sypcr;
-	char res1[6];
-	ushort sc_swsr;
-	uint sc_sipend;
-	uint sc_simask;
-	uint sc_siel;
-	uint sc_sivec;
-	uint sc_tesr;
-	uint sc_sgpiodt1;
-	uint sc_sgpiodt2;
-	uint sc_sgpiocr;
-	uint sc_emcr;
-	uint sc_res1aa;
-	uint sc_res1ab;
-	uint sc_pdmcr;
-	char res3[192];
-} sysconf5xx_t;
-
-
-/* Memory Controller Registers.
-*/
-typedef struct	mem_ctlr {
-	uint memc_br0;
-	uint memc_or0;
-	uint memc_br1;
-	uint memc_or1;
-	uint memc_br2;
-	uint memc_or2;
-	uint memc_br3;
-	uint memc_or3;
-	char res1[32];
-	uint memc_dmbr;
-	uint memc_dmor;
-	char res2[48];
-	ushort memc_mstat;
-	ushort memc_res4a;
-	char res3[132];
-} memctl5xx_t;
-
-/* System Integration Timers.
-*/
-typedef struct	sys_int_timers {
-	ushort sit_tbscr;
-	char res1[2];
-	uint sit_tbref0;
-	uint sit_tbref1;
-	char res2[20];
-	ushort sit_rtcsc;
-	char res3[2];
-	uint sit_rtc;
-	uint sit_rtsec;
-	uint sit_rtcal;
-	char res4[16];
-	ushort sit_piscr;
-	char res5[2];
-	uint sit_pitc;
-	uint sit_pitr;
-	char res6[52];
-} sit5xx_t;
-
-/* Clocks and Reset
-*/
-typedef struct clk_and_reset {
-	uint car_sccr;
-	uint car_plprcr;
-	ushort car_rsr;
-	ushort car_res7a;
-	ushort car_colir;
-	ushort car_res7b;
-	ushort car_vsrmcr;
-	ushort car_res7c;
-	char res1[108];
-
-} car5xx_t;
-
-#define TBSCR_TBE		((ushort)0x0001)
-
-/* System Integration Timer Keys
-*/
-typedef struct sitk {
-	uint sitk_tbscrk;
-	uint sitk_tbref0k;
-	uint sitk_tbref1k;
-	uint sitk_tbk;
-	char res1[16];
-	uint sitk_rtcsck;
-	uint sitk_rtck;
-	uint sitk_rtseck;
-	uint sitk_rtcalk;
-	char res2[16];
-	uint sitk_piscrk;
-	uint sitk_pitck;
-	char res3[56];
-} sitk5xx_t;
-
-/* Clocks and Reset Keys.
-*/
-typedef struct cark {
-	uint	cark_sccrk;
-	uint	cark_plprcrk;
-	uint	cark_rsrk;
-	char	res1[1140];
-} cark8xx_t;
-
-/* The key to unlock registers maintained by keep-alive power.
-*/
-#define KAPWR_KEY	((unsigned int)0x55ccaa33)
-
-/* Flash Configuration
-*/
-typedef struct fl {
-	uint fl_cmfmcr;
-	uint fl_cmftst;
-	uint fl_cmfctl;
-	char res1[52];
-} fl5xx_t;
-
-/* Dpram Control
-*/
-typedef struct dprc {
-	ushort dprc_dptmcr;
-	ushort dprc_ramtst;
-	ushort dprc_rambar;
-	ushort dprc_misrh;
-	ushort dprc_misrl;
-	ushort dprc_miscnt;
-} dprc5xx_t;
-
-/* Time Processor Unit
-*/
-typedef struct tpu {
-	ushort tpu_tpumcr;
-	ushort tpu_tcr;
-	ushort tpu_dscr;
-	ushort tpu_dssr;
-	ushort tpu_ticr;
-	ushort tpu_cier;
-	ushort tpu_cfsr0;
-	ushort tpu_cfsr1;
-	ushort tpu_cfsr2;
-	ushort tpu_cfsr3;
-	ushort tpu_hsqr0;
-	ushort tpu_hsqr1;
-	ushort tpu_hsrr0;
-	ushort tpu_hsrr1;
-	ushort tpu_cpr0;
-	ushort tpu_cpr1;
-	ushort tpu_cisr;
-	ushort tpu_lr;
-	ushort tpu_sglr;
-	ushort tpu_dcnr;
-	ushort tpu_tpumcr2;
-	ushort tpu_tpumcr3;
-	ushort tpu_isdr;
-	ushort tpu_iscr;
-	char   res1[208];
-	char   tpu[16][16];
-	char   res2[512];
-} tpu5xx_t;
-
-/* QADC
-*/
-typedef struct qadc {
-	ushort qadc_64mcr;
-	ushort qadc_64test;
-	ushort qadc_64int;
-	u_char  qadc_portqa;
-	u_char  qadc_portqb;
-	ushort qadc_ddrqa;
-	ushort qadc_qacr0;
-	ushort qadc_qacr1;
-	ushort qadc_qacr2;
-	ushort qadc_qasr0;
-	ushort qadc_qasr1;
-	char   res1[492];
-       /* command convertion word table */
-	ushort qadc_ccw[64];
-       /* result word table, unsigned right justified */
-	ushort qadc_rjurr[64];
-       /* result word table, signed left justified */
-	ushort qadc_ljsrr[64];
-       /* result word table, unsigned left justified */
-	ushort qadc_ljurr[64];
-} qadc5xx_t;
-
-/* QSMCM
-*/
-typedef struct qsmcm {
-	ushort qsmcm_qsmcr;
-	ushort qsmcm_qtest;
-	ushort qsmcm_qdsci_il;
-	ushort qsmcm_qspi_il;
-	ushort qsmcm_scc1r0;
-	ushort qsmcm_scc1r1;
-	ushort qsmcm_sc1sr;
-	ushort qsmcm_sc1dr;
-	char   res1[2];
-	char   res2[2];
-	ushort qsmcm_portqs;
-	u_char qsmcm_pqspar;
-	u_char qsmcm_ddrqs;
-	ushort qsmcm_spcr0;
-	ushort qsmcm_spcr1;
-	ushort qsmcm_spcr2;
-	u_char qsmcm_spcr3;
-	u_char qsmcm_spsr;
-	ushort qsmcm_scc2r0;
-	ushort qsmcm_scc2r1;
-	ushort qsmcm_sc2sr;
-	ushort qsmcm_sc2dr;
-	ushort qsmcm_qsci1cr;
-	ushort qsmcm_qsci1sr;
-	ushort qsmcm_sctq[16];
-	ushort qsmcm_scrq[16];
-	char   res3[212];
-	ushort qsmcm_recram[32];
-	ushort qsmcm_tranram[32];
-	u_char qsmcm_comdram[32];
-	char   res[3616];
-} qsmcm5xx_t;
-
-
-/* MIOS
-*/
-
-typedef struct mios {
-	ushort mios_mpwmsm0perr;                 /* mpwmsm0 */
-	ushort mios_mpwmsm0pulr;
-	ushort mios_mpwmsm0cntr;
-	ushort mios_mpwmsm0scr;
-	ushort mios_mpwmsm1perr;                 /* mpwmsm1 */
-	ushort mios_mpwmsm1pulr;
-	ushort mios_mpwmsm1cntr;
-	ushort mios_mpwmsm1scr;
-	ushort mios_mpwmsm2perr;                 /* mpwmsm2 */
-	ushort mios_mpwmsm2pulr;
-	ushort mios_mpwmsm2cntr;
-	ushort mios_mpwmsm2scr;
-	ushort mios_mpwmsm3perr;                 /* mpwmsm3 */
-	ushort mios_mpwmsm3pulr;
-	ushort mios_mpwmsm3cntr;
-	ushort mios_mpwmsm3scr;
-	char res1[16];
-	ushort mios_mmcsm6cnt;                   /* mmcsm6 */
-	ushort mios_mmcsm6mlr;
-	ushort mios_mmcsm6scrd, mmcsm6scr;
-	char res2[32];
-	ushort mios_mdasm11ar;                   /* mdasm11 */
-	ushort mios_mdasm11br;
-	ushort mios_mdasm11scrd, mdasm11scr;
-	ushort mios_mdasm12ar;                   /* mdasm12 */
-	ushort mios_mdasm12br;
-	ushort mios_mdasm12scrd, mdasm12scr;
-	ushort mios_mdasm13ar;                   /* mdasm13 */
-	ushort mios_mdasm13br;
-	ushort mios_mdasm13scrd, mdasm13scr;
-	ushort mios_mdasm14ar;                   /* mdasm14 */
-	ushort mios_mdasm14br;
-	ushort mios_mdasm14scrd, mdasm14scr;
-	ushort mios_mdasm15ar;                   /* mdasm15 */
-	ushort mios_mdasm15br;
-	ushort mios_mdasm15scrd, mdasm15scr;
-	ushort mios_mpwmsm16perr;                /* mpwmsm16 */
-	ushort mios_mpwmsm16pulr;
-	ushort mios_mpwmsm16cntr;
-	ushort mios_mpwmsm16scr;
-	ushort mios_mpwmsm17perr;                /* mpwmsm17 */
-	ushort mios_mpwmsm17pulr;
-	ushort mios_mpwmsm17cntr;
-	ushort mios_mpwmsm17scr;
-	ushort mios_mpwmsm18perr;                /* mpwmsm18 */
-	ushort mios_mpwmsm18pulr;
-	ushort mios_mpwmsm18cntr;
-	ushort mios_mpwmsm18scr;
-	ushort mios_mpwmsm19perr;                /* mpwmsm19 */
-	ushort mios_mpwmsm19pulr;
-	ushort mios_mpwmsm19cntr;
-	ushort mios_mpwmsm19scr;
-	char res3[16];
-	ushort mios_mmcsm22cnt;                  /* mmcsm22 */
-	ushort mios_mmcsm22mlr;
-	ushort mios_mmcsm22scrd, mmcsm22scr;
-	char res4[32];
-	ushort mios_mdasm27ar;                   /* mdasm27 */
-	ushort mios_mdasm27br;
-	ushort mios_mdasm27scrd, mdasm27scr;
-	ushort mios_mdasm28ar;                   /*mdasm28 */
-	ushort mios_mdasm28br;
-	ushort mios_mdasm28scrd, mdasm28scr;
-	ushort mios_mdasm29ar;                   /* mdasm29 */
-	ushort mios_mdasm29br;
-	ushort mios_mdasm29scrd, mdasm29scr;
-	ushort mios_mdasm30ar;                   /* mdasm30 */
-	ushort mios_mdasm30br;
-	ushort mios_mdasm30scrd, mdasm30scr;
-	ushort mios_mdasm31ar;                   /* mdasm31 */
-	ushort mios_mdasm31br;
-	ushort mios_mdasm31scrd, mdasm31scr;
-	ushort mios_mpiosm32dr;
-	ushort mios_mpiosm32ddr;
-	char res5[1788];
-	ushort mios_mios1tpcr;
-	char mios_res13[2];
-	ushort mios_mios1vnr;
-	ushort mios_mios1mcr;
-	char res6[12];
-	ushort mios_res42z;
-	ushort mios_mcpsmscr;
-	char res7[1000];
-	ushort mios_mios1sr0;
-	char res12[2];
-	ushort mios_mios1er0;
-	ushort mios_mios1rpr0;
-	char res8[40];
-	ushort mios_mios1lvl0;
-	char res9[14];
-	ushort mios_mios1sr1;
-	char res10[2];
-	ushort mios_mios1er1;
-	ushort mios_mios1rpr1;
-	char res11[40];
-	ushort mios_mios1lvl1;
-	char res13[1038];
-} mios5xx_t;
-
-/* Toucan Module
-*/
-typedef struct tcan {
-	ushort tcan_tcnmcr;
-	ushort tcan_cantcr;
-	ushort tcan_canicr;
-	u_char tcan_canctrl0;
-	u_char tcan_canctrl1;
-	u_char tcan_presdiv;
-	u_char tcan_canctrl2;
-	ushort tcan_timer;
-	char res1[4];
-	ushort tcan_rxgmskhi;
-	ushort tcan_rxgmsklo;
-	ushort tcan_rx14mskhi;
-	ushort tcan_rx14msklo;
-	ushort tcan_rx15mskhi;
-	ushort tcan_rx15msklo;
-	char res2[4];
-	ushort tcan_estat;
-	ushort tcan_imask;
-	ushort tcan_iflag;
-	u_char tcan_rxectr;
-	u_char tcan_txectr;
-	char res3[88];
-	struct {
-	       ushort scr;
-	       ushort id_high;
-	       ushort id_low;
-	       u_char data[8];
-		   char res4[2];
-	    } tcan_mbuff[16];
-	    char res5[640];
-} tcan5xx_t;
-
-/* UIMB
-*/
-typedef struct uimb {
-	uint uimb_umcr;
-	char res1[12];
-	uint uimb_utstcreg;
-	char res2[12];
-	uint uimb_uipend;
-} uimb5xx_t;
-
-
-/* Internal Memory Map MPC555
-*/
-typedef struct immap {
-	char               res1[262144];	/* CMF Flash A 256 Kbytes */
-	char               res2[196608];	/* CMF Flash B 192 Kbytes */
-	char               res3[2670592];	/* Reserved for Flash */
-	sysconf5xx_t       im_siu_conf;		/* SIU Configuration */
-	memctl5xx_t	   im_memctl;		/* Memory Controller */
-	sit5xx_t           im_sit;		/* System Integration Timers */
-	car5xx_t	   im_clkrst;		/* Clocks and Reset */
-	sitk5xx_t          im_sitk;		/* System Integration Timer Keys*/
-	cark8xx_t          im_clkrstk;		/* Clocks and Resert Keys */
-	fl5xx_t	           im_fla;	        /* Flash Module A */
-	fl5xx_t	           im_flb;	        /* Flash Module B */
-	char               res4[14208];		/* Reserved for SIU */
-	dprc5xx_t	   im_dprc;		/* Dpram Control Register */
-	char               res5[8180];		/* Reserved */
-	char               dptram[6144];	/* Dptram */
-	char               res6[2048];		/* Reserved */
-	tpu5xx_t	   im_tpua;		/* Time Proessing Unit A */
-	tpu5xx_t	   im_tpub;		/* Time Processing Unit B */
-	qadc5xx_t	   im_qadca;		/* QADC A */
-	qadc5xx_t	   im_qadcb;		/* QADC B */
-	qsmcm5xx_t	   im_qsmcm;		/* SCI and SPI */
-	mios5xx_t	   im_mios;		/* MIOS */
-	tcan5xx_t          im_tcana;		/* Toucan A */
-	tcan5xx_t          im_tcanb;		/* Toucan B */
-	char               res7[1792];		/* Reserved */
-	uimb5xx_t          im_uimb;	        /* UIMB */
-} immap_t;
-
-#endif /* __IMMAP_5XX__ */
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h
deleted file mode 100644
index dfaddb6f1d..0000000000
--- a/arch/powerpc/include/asm/8xx_immap.h
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- * MPC8xx Internal Memory Map
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- *
- * The I/O on the MPC860 is comprised of blocks of special registers
- * and the dual port ram for the Communication Processor Module.
- * Within this space are functional units such as the SIU, memory
- * controller, system timers, and other control functions.  It is
- * a combination that I found difficult to separate into logical
- * functional files.....but anyone else is welcome to try.  -- Dan
- */
-#ifndef __IMMAP_8XX__
-#define __IMMAP_8XX__
-
-/* System configuration registers.
-*/
-typedef	struct sys_conf {
-	uint	sc_siumcr;
-	uint	sc_sypcr;
-	uint	sc_swt;
-	char	res1[2];
-	ushort	sc_swsr;
-	uint	sc_sipend;
-	uint	sc_simask;
-	uint	sc_siel;
-	uint	sc_sivec;
-	uint	sc_tesr;
-	char	res2[0xc];
-	uint	sc_sdcr;
-	char	res3[0x4c];
-} sysconf8xx_t;
-
-/* PCMCIA configuration registers.
-*/
-typedef struct pcmcia_conf {
-	uint	pcmc_pbr0;
-	uint	pcmc_por0;
-	uint	pcmc_pbr1;
-	uint	pcmc_por1;
-	uint	pcmc_pbr2;
-	uint	pcmc_por2;
-	uint	pcmc_pbr3;
-	uint	pcmc_por3;
-	uint	pcmc_pbr4;
-	uint	pcmc_por4;
-	uint	pcmc_pbr5;
-	uint	pcmc_por5;
-	uint	pcmc_pbr6;
-	uint	pcmc_por6;
-	uint	pcmc_pbr7;
-	uint	pcmc_por7;
-	char	res1[0x20];
-	uint	pcmc_pgcra;
-	uint	pcmc_pgcrb;
-	uint	pcmc_pscr;
-	char	res2[4];
-	uint	pcmc_pipr;
-	char	res3[4];
-	uint	pcmc_per;
-	char	res4[4];
-} pcmconf8xx_t;
-
-/* Memory controller registers.
-*/
-typedef struct	mem_ctlr {
-	uint	memc_br0;
-	uint	memc_or0;
-	uint	memc_br1;
-	uint	memc_or1;
-	uint	memc_br2;
-	uint	memc_or2;
-	uint	memc_br3;
-	uint	memc_or3;
-	uint	memc_br4;
-	uint	memc_or4;
-	uint	memc_br5;
-	uint	memc_or5;
-	uint	memc_br6;
-	uint	memc_or6;
-	uint	memc_br7;
-	uint	memc_or7;
-	char	res1[0x24];
-	uint	memc_mar;
-	uint	memc_mcr;
-	char	res2[4];
-	uint	memc_mamr;
-	uint	memc_mbmr;
-	ushort	memc_mstat;
-	ushort	memc_mptpr;
-	uint	memc_mdr;
-	char	res3[0x80];
-} memctl8xx_t;
-
-/* System Integration Timers.
-*/
-typedef struct	sys_int_timers {
-	ushort	sit_tbscr;
-	char	res0[0x02];
-	uint	sit_tbreff0;
-	uint	sit_tbreff1;
-	char	res1[0x14];
-	ushort	sit_rtcsc;
-	char	res2[0x02];
-	uint	sit_rtc;
-	uint	sit_rtsec;
-	uint	sit_rtcal;
-	char	res3[0x10];
-	ushort	sit_piscr;
-	char	res4[2];
-	uint	sit_pitc;
-	uint	sit_pitr;
-	char	res5[0x34];
-} sit8xx_t;
-
-#define TBSCR_TBIRQ_MASK	((ushort)0xff00)
-#define TBSCR_REFA		((ushort)0x0080)
-#define TBSCR_REFB		((ushort)0x0040)
-#define TBSCR_REFAE		((ushort)0x0008)
-#define TBSCR_REFBE		((ushort)0x0004)
-#define TBSCR_TBF		((ushort)0x0002)
-#define TBSCR_TBE		((ushort)0x0001)
-
-#define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
-#define RTCSC_SEC		((ushort)0x0080)
-#define RTCSC_ALR		((ushort)0x0040)
-#define RTCSC_38K		((ushort)0x0010)
-#define RTCSC_SIE		((ushort)0x0008)
-#define RTCSC_ALE		((ushort)0x0004)
-#define RTCSC_RTF		((ushort)0x0002)
-#define RTCSC_RTE		((ushort)0x0001)
-
-#define PISCR_PIRQ_MASK		((ushort)0xff00)
-#define PISCR_PS		((ushort)0x0080)
-#define PISCR_PIE		((ushort)0x0004)
-#define PISCR_PTF		((ushort)0x0002)
-#define PISCR_PTE		((ushort)0x0001)
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-	uint	car_sccr;
-	uint	car_plprcr;
-	uint	car_rsr;
-	char	res[0x74];        /* Reserved area                  */
-} car8xx_t;
-
-/* System Integration Timers keys.
-*/
-typedef struct sitk {
-	uint	sitk_tbscrk;
-	uint	sitk_tbreff0k;
-	uint	sitk_tbreff1k;
-	uint	sitk_tbk;
-	char	res1[0x10];
-	uint	sitk_rtcsck;
-	uint	sitk_rtck;
-	uint	sitk_rtseck;
-	uint	sitk_rtcalk;
-	char	res2[0x10];
-	uint	sitk_piscrk;
-	uint	sitk_pitck;
-	char	res3[0x38];
-} sitk8xx_t;
-
-/* Clocks and reset keys.
-*/
-typedef struct cark {
-	uint	cark_sccrk;
-	uint	cark_plprcrk;
-	uint	cark_rsrk;
-	char	res[0x474];
-} cark8xx_t;
-
-/* The key to unlock registers maintained by keep-alive power.
-*/
-#define KAPWR_KEY	((unsigned int)0x55ccaa33)
-
-/* Video interface.  MPC823 Only.
-*/
-typedef struct vid823 {
-	ushort	vid_vccr;
-	ushort	res1;
-	u_char	vid_vsr;
-	u_char	res2;
-	u_char	vid_vcmr;
-	u_char	res3;
-	uint	vid_vbcb;
-	uint	res4;
-	uint	vid_vfcr0;
-	uint	vid_vfaa0;
-	uint	vid_vfba0;
-	uint	vid_vfcr1;
-	uint	vid_vfaa1;
-	uint	vid_vfba1;
-	u_char	res5[0x18];
-} vid823_t;
-
-/* LCD interface.  823 Only.
-*/
-typedef struct lcd {
-	uint	lcd_lccr;
-	uint	lcd_lchcr;
-	uint	lcd_lcvcr;
-	char	res1[4];
-	uint	lcd_lcfaa;
-	uint	lcd_lcfba;
-	char	lcd_lcsr;
-	char	res2[0x7];
-} lcd823_t;
-
-/* I2C
-*/
-typedef struct i2c {
-	u_char	i2c_i2mod;
-	char	res1[3];
-	u_char	i2c_i2add;
-	char	res2[3];
-	u_char	i2c_i2brg;
-	char	res3[3];
-	u_char	i2c_i2com;
-	char	res4[3];
-	u_char	i2c_i2cer;
-	char	res5[3];
-	u_char	i2c_i2cmr;
-	char	res6[0x8b];
-} i2c8xx_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-	char	res1[4];
-	uint	sdma_sdar;
-	u_char	sdma_sdsr;
-	char	res3[3];
-	u_char	sdma_sdmr;
-	char	res4[3];
-	u_char	sdma_idsr1;
-	char	res5[3];
-	u_char	sdma_idmr1;
-	char	res6[3];
-	u_char	sdma_idsr2;
-	char	res7[3];
-	u_char	sdma_idmr2;
-	char	res8[0x13];
-} sdma8xx_t;
-
-/* Communication Processor Module Interrupt Controller.
-*/
-typedef struct cpm_ic {
-	ushort	cpic_civr;
-	char	res[0xe];
-	uint	cpic_cicr;
-	uint	cpic_cipr;
-	uint	cpic_cimr;
-	uint	cpic_cisr;
-} cpic8xx_t;
-
-/* Input/Output Port control/status registers.
-*/
-typedef struct io_port {
-	ushort	iop_padir;
-	ushort	iop_papar;
-	ushort	iop_paodr;
-	ushort	iop_padat;
-	char	res1[8];
-	ushort	iop_pcdir;
-	ushort	iop_pcpar;
-	ushort	iop_pcso;
-	ushort	iop_pcdat;
-	ushort	iop_pcint;
-	char	res2[6];
-	ushort	iop_pddir;
-	ushort	iop_pdpar;
-	char	res3[2];
-	ushort	iop_pddat;
-	uint	utmode;
-	char	res4[4];
-} iop8xx_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-	ushort	cpmt_tgcr;
-	char	res1[0xe];
-	ushort	cpmt_tmr1;
-	ushort	cpmt_tmr2;
-	ushort	cpmt_trr1;
-	ushort	cpmt_trr2;
-	ushort	cpmt_tcr1;
-	ushort	cpmt_tcr2;
-	ushort	cpmt_tcn1;
-	ushort	cpmt_tcn2;
-	ushort	cpmt_tmr3;
-	ushort	cpmt_tmr4;
-	ushort	cpmt_trr3;
-	ushort	cpmt_trr4;
-	ushort	cpmt_tcr3;
-	ushort	cpmt_tcr4;
-	ushort	cpmt_tcn3;
-	ushort	cpmt_tcn4;
-	ushort	cpmt_ter1;
-	ushort	cpmt_ter2;
-	ushort	cpmt_ter3;
-	ushort	cpmt_ter4;
-	char	res2[8];
-} cpmtimer8xx_t;
-
-/* Finally, the Communication Processor stuff.....
-*/
-typedef struct scc {		/* Serial communication channels */
-	uint	scc_gsmrl;
-	uint	scc_gsmrh;
-	ushort	scc_psmr;
-	char	res1[2];
-	ushort	scc_todr;
-	ushort	scc_dsr;
-	ushort	scc_scce;
-	char	res2[2];
-	ushort	scc_sccm;
-	char	res3;
-	u_char	scc_sccs;
-	char	res4[8];
-} scc_t;
-
-typedef struct smc {		/* Serial management channels */
-	char	res1[2];
-	ushort	smc_smcmr;
-	char	res2[2];
-	u_char	smc_smce;
-	char	res3[3];
-	u_char	smc_smcm;
-	char	res4[5];
-} smc_t;
-
-/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
- * it fits within the address space.
- */
-
-typedef struct fec {
-	uint	fec_addr_low;		/* lower 32 bits of station address	*/
-	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
-	ushort	res1;			/* reserved				*/
-	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
-	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
-	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
-	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
-	uint	fec_r_buff_size;	/* Rx buffer size			*/
-	uint	res2[9];		/* reserved				*/
-	uint	fec_ecntrl;		/* ethernet control register		*/
-	uint	fec_ievent;		/* interrupt event register		*/
-	uint	fec_imask;		/* interrupt mask register		*/
-	uint	fec_ivec;		/* interrupt level and vector status	*/
-	uint	fec_r_des_active;	/* Rx ring updated flag			*/
-	uint	fec_x_des_active;	/* Tx ring updated flag			*/
-	uint	res3[10];		/* reserved				*/
-	uint	fec_mii_data;		/* MII data register			*/
-	uint	fec_mii_speed;		/* MII speed control register		*/
-	uint	res4[17];		/* reserved				*/
-	uint	fec_r_bound;		/* end of RAM (read-only)		*/
-	uint	fec_r_fstart;		/* Rx FIFO start address		*/
-	uint	res5[6];		/* reserved				*/
-	uint	fec_x_fstart;		/* Tx FIFO start address		*/
-	uint	res6[17];		/* reserved				*/
-	uint	fec_fun_code;		/* fec SDMA function code		*/
-	uint	res7[3];		/* reserved				*/
-	uint	fec_r_cntrl;		/* Rx control register			*/
-	uint	fec_r_hash;		/* Rx hash register			*/
-	uint	res8[14];		/* reserved				*/
-	uint	fec_x_cntrl;		/* Tx control register			*/
-	uint	res9[0x1e];		/* reserved				*/
-} fec_t;
-
-/* The FEC and LCD color map share the same address space....
- * I guess we will never see an 823T :-).
- */
-union fec_lcd {
-	fec_t	fl_un_fec;
-	u_char	fl_un_cmap[0x200];
-};
-
-typedef struct comm_proc {
-	/* General control and status registers.
-	*/
-	ushort	cp_cpcr;
-	u_char	res1[2];
-	ushort	cp_rccr;
-	u_char	res2;
-	u_char	cp_rmds;
-	u_char	res3[4];
-	ushort	cp_cpmcr1;
-	ushort	cp_cpmcr2;
-	ushort	cp_cpmcr3;
-	ushort	cp_cpmcr4;
-	u_char	res4[2];
-	ushort	cp_rter;
-	u_char	res5[2];
-	ushort	cp_rtmr;
-	u_char	res6[0x14];
-
-	/* Baud rate generators.
-	*/
-	uint	cp_brgc1;
-	uint	cp_brgc2;
-	uint	cp_brgc3;
-	uint	cp_brgc4;
-
-	/* Serial Communication Channels.
-	*/
-	scc_t	cp_scc[4];
-
-	/* Serial Management Channels.
-	*/
-	smc_t	cp_smc[2];
-
-	/* Serial Peripheral Interface.
-	*/
-	ushort	cp_spmode;
-	u_char	res7[4];
-	u_char	cp_spie;
-	u_char	res8[3];
-	u_char	cp_spim;
-	u_char	res9[2];
-	u_char	cp_spcom;
-	u_char	res10[2];
-
-	/* Parallel Interface Port.
-	*/
-	u_char	res11[2];
-	ushort	cp_pipc;
-	u_char	res12[2];
-	ushort	cp_ptpr;
-	uint	cp_pbdir;
-	uint	cp_pbpar;
-	u_char	res13[2];
-	ushort	cp_pbodr;
-	uint	cp_pbdat;
-
-	/* Port E - MPC87x/88x only.
-	 */
-	uint	cp_pedir;
-	uint	cp_pepar;
-	uint	cp_peso;
-	uint	cp_peodr;
-	uint	cp_pedat;
-
-	/* Communications Processor Timing Register -
-	   Contains RMII Timing for the FECs on MPC87x/88x only.
-	*/
-	uint	cp_cptr;
-
-	/* Serial Interface and Time Slot Assignment.
-	*/
-	uint	cp_simode;
-	u_char	cp_sigmr;
-	u_char	res15;
-	u_char	cp_sistr;
-	u_char	cp_sicmr;
-	u_char	res16[4];
-	uint	cp_sicr;
-	uint	cp_sirp;
-	u_char	res17[0xc];
-
-	/* 256 bytes of MPC823 video controller RAM array.
-	*/
-	u_char	cp_vcram[0x100];
-	u_char	cp_siram[0x200];
-
-	/* The fast ethernet controller is not really part of the CPM,
-	 * but it resides in the address space.
-	 * The LCD color map is also here.
-	 */
-	union	fec_lcd	fl_un;
-#define cp_fec		fl_un.fl_un_fec
-#define lcd_cmap	fl_un.fl_un_cmap
-	char	res18[0xE00];
-
-	/* The MPC885 family has a second FEC here */
-	fec_t	cp_fec2;
-#define cp_fec1	cp_fec	/* consistency macro */
-
-	/* Dual Ported RAM follows.
-	 * There are many different formats for this memory area
-	 * depending upon the devices used and options chosen.
-	 * Some processors don't have all of it populated.
-	 */
-	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
-
-	/* Parameter RAM */
-	union {
-		u_char	cp_dparam[0x400];
-		u16	cp_dparam16[0x200];
-	};
-} cpm8xx_t;
-
-/* Internal memory map.
-*/
-typedef struct immap {
-	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
-	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
-	memctl8xx_t	im_memctl;	/* Memory Controller */
-	sit8xx_t	im_sit;		/* System integration timers */
-	car8xx_t	im_clkrst;	/* Clocks and reset */
-	sitk8xx_t	im_sitk;	/* Sys int timer keys */
-	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
-	vid823_t	im_vid;		/* Video (823 only) */
-	lcd823_t	im_lcd;		/* LCD (823 only) */
-	i2c8xx_t	im_i2c;		/* I2C control/status */
-	sdma8xx_t	im_sdma;	/* SDMA control/status */
-	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
-	iop8xx_t	im_ioport;	/* IO Port control/status */
-	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
-	cpm8xx_t	im_cpm;		/* Communication processor */
-} immap_t;
-
-#endif /* __IMMAP_8XX__ */
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index d3a83910b6..20c52fcddc 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -7,9 +7,7 @@
 #include <asm/processor.h>
 
 /* bytes per L1 cache line */
-#if defined(CONFIG_8xx)
-#define	L1_CACHE_SHIFT	4
-#elif defined(CONFIG_PPC64BRIDGE)
+#if defined(CONFIG_PPC64BRIDGE)
 #define L1_CACHE_SHIFT	7
 #elif defined(CONFIG_E500MC)
 #define L1_CACHE_SHIFT	6
@@ -72,41 +70,4 @@ void disable_cpc_sram(void);
 #define L2CACHE_NONE	0x03	/* NONE */
 #define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
 
-#ifdef CONFIG_8xx
-/* Cache control on the MPC8xx is provided through some additional
- * special purpose registers.
- */
-#define IC_CST		560	/* Instruction cache control/status */
-#define IC_ADR		561	/* Address needed for some commands */
-#define IC_DAT		562	/* Read-only data register */
-#define DC_CST		568	/* Data cache control/status */
-#define DC_ADR		569	/* Address needed for some commands */
-#define DC_DAT		570	/* Read-only data register */
-
-/* Commands.  Only the first few are available to the instruction cache.
-*/
-#define	IDC_ENABLE	0x02000000	/* Cache enable */
-#define IDC_DISABLE	0x04000000	/* Cache disable */
-#define IDC_LDLCK	0x06000000	/* Load and lock */
-#define IDC_UNLINE	0x08000000	/* Unlock line */
-#define IDC_UNALL	0x0a000000	/* Unlock all */
-#define IDC_INVALL	0x0c000000	/* Invalidate all */
-
-#define DC_FLINE	0x0e000000	/* Flush data cache line */
-#define DC_SFWT		0x01000000	/* Set forced writethrough mode */
-#define DC_CFWT		0x03000000	/* Clear forced writethrough mode */
-#define DC_SLES		0x05000000	/* Set little endian swap mode */
-#define DC_CLES		0x07000000	/* Clear little endian swap mode */
-
-/* Status.
-*/
-#define IDC_ENABLED	0x80000000	/* Cache is enabled */
-#define IDC_CERR1	0x00200000	/* Cache error 1 */
-#define IDC_CERR2	0x00100000	/* Cache error 2 */
-#define IDC_CERR3	0x00080000	/* Cache error 3 */
-
-#define DC_DFWT		0x40000000	/* Data cache is forced write through */
-#define DC_LES		0x20000000	/* Caches are little endian mode */
-#endif /* CONFIG_8xx */
-
 #endif
diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h
deleted file mode 100644
index 4f78186d9d..0000000000
--- a/arch/powerpc/include/asm/cpm_8260.h
+++ /dev/null
@@ -1,795 +0,0 @@
-/*
- * MPC8260 Communication Processor Module.
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * This file contains structures and information for the communication
- * processor channels found in the dual port RAM or parameter RAM.
- * All CPM control and status is available through the MPC8260 internal
- * memory map.  See immap.h for details.
- */
-#ifndef __CPM_82XX__
-#define __CPM_82XX__
-
-#include <asm/immap_8260.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST	((uint)0x80000000)
-#define CPM_CR_PAGE	((uint)0x7c000000)
-#define CPM_CR_SBLOCK	((uint)0x03e00000)
-#define CPM_CR_FLG	((uint)0x00010000)
-#define CPM_CR_MCN	((uint)0x00003fc0)
-#define CPM_CR_OPCODE	((uint)0x0000000f)
-
-/* Device sub-block and page codes.
-*/
-#define CPM_CR_SCC1_SBLOCK	(0x04)
-#define CPM_CR_SCC2_SBLOCK	(0x05)
-#define CPM_CR_SCC3_SBLOCK	(0x06)
-#define CPM_CR_SCC4_SBLOCK	(0x07)
-#define CPM_CR_SMC1_SBLOCK	(0x08)
-#define CPM_CR_SMC2_SBLOCK	(0x09)
-#define CPM_CR_SPI_SBLOCK	(0x0a)
-#define CPM_CR_I2C_SBLOCK	(0x0b)
-#define CPM_CR_TIMER_SBLOCK	(0x0f)
-#define CPM_CR_RAND_SBLOCK	(0x0e)
-#define CPM_CR_FCC1_SBLOCK	(0x10)
-#define CPM_CR_FCC2_SBLOCK	(0x11)
-#define CPM_CR_FCC3_SBLOCK	(0x12)
-#define CPM_CR_IDMA1_SBLOCK	(0x14)
-#define CPM_CR_IDMA2_SBLOCK	(0x15)
-#define CPM_CR_IDMA3_SBLOCK	(0x16)
-#define CPM_CR_IDMA4_SBLOCK	(0x17)
-#define CPM_CR_MCC1_SBLOCK	(0x1c)
-
-#define CPM_CR_SCC1_PAGE	(0x00)
-#define CPM_CR_SCC2_PAGE	(0x01)
-#define CPM_CR_SCC3_PAGE	(0x02)
-#define CPM_CR_SCC4_PAGE	(0x03)
-#define CPM_CR_SMC1_PAGE	(0x07)
-#define CPM_CR_SMC2_PAGE	(0x08)
-#define CPM_CR_SPI_PAGE		(0x09)
-#define CPM_CR_I2C_PAGE		(0x0a)
-#define CPM_CR_TIMER_PAGE	(0x0a)
-#define CPM_CR_RAND_PAGE	(0x0a)
-#define CPM_CR_FCC1_PAGE	(0x04)
-#define CPM_CR_FCC2_PAGE	(0x05)
-#define CPM_CR_FCC3_PAGE	(0x06)
-#define CPM_CR_IDMA1_PAGE	(0x07)
-#define CPM_CR_IDMA2_PAGE	(0x08)
-#define CPM_CR_IDMA3_PAGE	(0x09)
-#define CPM_CR_IDMA4_PAGE	(0x0a)
-#define CPM_CR_MCC1_PAGE	(0x07)
-#define CPM_CR_MCC2_PAGE	(0x08)
-
-/* Some opcodes (there are more...later)
-*/
-#define CPM_CR_INIT_TRX		((ushort)0x0000)
-#define CPM_CR_INIT_RX		((ushort)0x0001)
-#define CPM_CR_INIT_TX		((ushort)0x0002)
-#define CPM_CR_HUNT_MODE	((ushort)0x0003)
-#define CPM_CR_STOP_TX		((ushort)0x0004)
-#define CPM_CR_RESTART_TX	((ushort)0x0006)
-#define CPM_CR_SET_GADDR	((ushort)0x0008)
-
-#define mk_cr_cmd(PG, SBC, MCN, OP) \
-	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
-
-/* Dual Port RAM addresses.  The first 16K is available for almost
- * any CPM use, so we put the BDs there.  The first 128 bytes are
- * used for SMC1 and SMC2 parameter RAM, so we start allocating
- * BDs above that.  All of this must change when we start
- * downloading RAM microcode.
- */
-#define CPM_DATAONLY_BASE	((uint)128)
-#define CPM_DP_NOSPACE		((uint)0x7fffffff)
-#ifndef CONFIG_MPC8272_FAMILY
-#define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE	((uint)0x0000b000)
-#else  /* 8247/48/71/72 */
-#define CPM_DATAONLY_SIZE	((uint)(4 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE	((uint)0x00009000)
-#endif /* !CONFIG_MPC8272_FAMILY */
-
-/* The number of pages of host memory we allocate for CPM.  This is
- * done early in kernel initialization to get physically contiguous
- * pages.
- */
-#define NUM_CPM_HOST_PAGES	2
-
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-extern	cpm8260_t	*cpmp;		/* Pointer to comm processor */
-uint		m8260_cpm_dpalloc(uint size, uint align);
-uint		m8260_cpm_hostalloc(uint size, uint align);
-void		m8260_cpm_setbrg(uint brg, uint rate);
-void		m8260_cpm_fastbrg(uint brg, uint rate, int div16);
-void		m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
-
-/* Buffer descriptors used by many of the CPM protocols.
-*/
-typedef struct cpm_buf_desc {
-	ushort	cbd_sc;		/* Status and Control */
-	ushort	cbd_datlen;	/* Data length in buffer */
-	uint	cbd_bufaddr;	/* Buffer address in host memory */
-} cbd_t;
-
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
-#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
-#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
-#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
-#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
-#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
-#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
-#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
-#define BD_SC_BR	((ushort)0x0020)	/* Break received */
-#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
-#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
-#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
-#define BD_SC_CD	((ushort)0x0001)	/* ?? */
-
-/* Function code bits, usually generic to devices.
-*/
-#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
-#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */
-#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
-#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
-#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
-
-/* Parameter RAM offsets from the base.
-*/
-#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
-#define CPM_POST_WORD_ADDR      0x80FC	/* steal a long at the end of SCC1 */
-#else
-#define CPM_POST_WORD_ADDR	CONFIG_SYS_CPM_POST_WORD_ADDR
-#endif
-
-#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
-#define CPM_BOOTCOUNT_ADDR	(CPM_POST_WORD_ADDR - 2*sizeof(ulong))
-#else
-#define CPM_BOOTCOUNT_ADDR	CONFIG_SYS_CPM_BOOTCOUNT_ADDR
-#endif
-
-#define PROFF_SCC1		((uint)0x8000)
-#define PROFF_SCC2		((uint)0x8100)
-#define PROFF_SCC3		((uint)0x8200)
-#define PROFF_SCC4		((uint)0x8300)
-#define PROFF_FCC1		((uint)0x8400)
-#define PROFF_FCC2		((uint)0x8500)
-#define PROFF_FCC3		((uint)0x8600)
-#define PROFF_MCC1		((uint)0x8700)
-#define PROFF_SMC1_BASE		((uint)0x87fc)
-#define PROFF_IDMA1_BASE	((uint)0x87fe)
-#define PROFF_MCC2		((uint)0x8800)
-#define PROFF_SMC2_BASE		((uint)0x88fc)
-#define PROFF_IDMA2_BASE	((uint)0x88fe)
-#define PROFF_SPI_BASE		((uint)0x89fc)
-#define PROFF_IDMA3_BASE	((uint)0x89fe)
-#define PROFF_TIMERS		((uint)0x8ae0)
-#define PROFF_REVNUM		((uint)0x8af0)
-#define PROFF_RAND		((uint)0x8af8)
-#define PROFF_I2C_BASE		((uint)0x8afc)
-#define PROFF_IDMA4_BASE	((uint)0x8afe)
-
-/* The SMCs are relocated to any of the first eight DPRAM pages.
- * We will fix these at the first locations of DPRAM, until we
- * get some microcode patches :-).
- * The parameter ram space for the SMCs is fifty-some bytes, and
- * they are required to start on a 64 byte boundary.
- */
-#define PROFF_SMC1	(0)
-#define PROFF_SMC2	(64)
-#define PROFF_SPI	((16*1024) - 128)
-
-/* Define enough so I can at least use the serial port as a UART.
- */
-typedef struct smc_uart {
-	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	smc_rfcr;	/* Rx function code */
-	u_char	smc_tfcr;	/* Tx function code */
-	ushort	smc_mrblr;	/* Max receive buffer length */
-	uint	smc_rstate;	/* Internal */
-	uint	smc_idp;	/* Internal */
-	ushort	smc_rbptr;	/* Internal */
-	ushort	smc_ibc;	/* Internal */
-	uint	smc_rxtmp;	/* Internal */
-	uint	smc_tstate;	/* Internal */
-	uint	smc_tdp;	/* Internal */
-	ushort	smc_tbptr;	/* Internal */
-	ushort	smc_tbc;	/* Internal */
-	uint	smc_txtmp;	/* Internal */
-	ushort	smc_maxidl;	/* Maximum idle characters */
-	ushort	smc_tmpidl;	/* Temporary idle counter */
-	ushort	smc_brklen;	/* Last received break length */
-	ushort	smc_brkec;	/* rcv'd break condition counter */
-	ushort	smc_brkcr;	/* xmt break count register */
-	ushort	smc_rmask;	/* Temporary bit mask */
-	uint	smc_stmp;	/* SDMA Temp */
-} smc_uart_t;
-
-/* SMC uart mode register (Internal memory map).
-*/
-#define	SMCMR_REN	((ushort)0x0001)
-#define SMCMR_TEN	((ushort)0x0002)
-#define SMCMR_DM	((ushort)0x000c)
-#define SMCMR_SM_GCI	((ushort)0x0000)
-#define SMCMR_SM_UART	((ushort)0x0020)
-#define SMCMR_SM_TRANS	((ushort)0x0030)
-#define SMCMR_SM_MASK	((ushort)0x0030)
-#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
-#define SMCMR_REVD	SMCMR_PM_EVEN
-#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
-#define SMCMR_BS	SMCMR_PEN
-#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
-#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
-#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC Event and Mask register.
-*/
-#define	SMCM_TXE	((unsigned char)0x10)
-#define	SMCM_BSY	((unsigned char)0x04)
-#define	SMCM_TX		((unsigned char)0x02)
-#define	SMCM_RX		((unsigned char)0x01)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST		((uint)0x00020000)
-#define CPM_BRG_EN		((uint)0x00010000)
-#define CPM_BRG_EXTC_INT	((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
-#define CPM_BRG_ATB		((uint)0x00002000)
-#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
-#define CPM_BRG_DIV16		((uint)0x00000001)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP		((uint)0x00040000)
-#define SCC_GSMRH_GDE		((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
-#define SCC_GSMRH_REVD		((uint)0x00002000)
-#define SCC_GSMRH_TRX		((uint)0x00001000)
-#define SCC_GSMRH_TTX		((uint)0x00000800)
-#define SCC_GSMRH_CDP		((uint)0x00000400)
-#define SCC_GSMRH_CTSP		((uint)0x00000200)
-#define SCC_GSMRH_CDS		((uint)0x00000100)
-#define SCC_GSMRH_CTSS		((uint)0x00000080)
-#define SCC_GSMRH_TFL		((uint)0x00000040)
-#define SCC_GSMRH_RFW		((uint)0x00000020)
-#define SCC_GSMRH_TXSY		((uint)0x00000010)
-#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8		((uint)0x00000008)
-#define SCC_GSMRH_SYNL4		((uint)0x00000004)
-#define SCC_GSMRH_RTSM		((uint)0x00000002)
-#define SCC_GSMRH_RSYN		((uint)0x00000001)
-
-#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
-#define SCC_GSMRL_TCI		((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
-#define SCC_GSMRL_RINV		((uint)0x02000000)
-#define SCC_GSMRL_TINV		((uint)0x01000000)
-#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48	((uint)0x00800000)
-#define SCC_GSMRL_TPL_32	((uint)0x00600000)
-#define SCC_GSMRL_TPL_16	((uint)0x00400000)
-#define SCC_GSMRL_TPL_8		((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
-#define SCC_GSMRL_TPP_01	((uint)0x00100000)
-#define SCC_GSMRL_TPP_10	((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
-#define SCC_GSMRL_TEND		((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
-#define SCC_GSMRL_ENR		((uint)0x00000020)
-#define SCC_GSMRL_ENT		((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
-#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
-
-#define SCC_TODR_TOD		((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define	SCCM_TXE	((unsigned char)0x10)
-#define	SCCM_BSY	((unsigned char)0x04)
-#define	SCCM_TX		((unsigned char)0x02)
-#define	SCCM_RX		((unsigned char)0x01)
-
-typedef struct scc_param {
-	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	scc_rfcr;	/* Rx function code */
-	u_char	scc_tfcr;	/* Tx function code */
-	ushort	scc_mrblr;	/* Max receive buffer length */
-	uint	scc_rstate;	/* Internal */
-	uint	scc_idp;	/* Internal */
-	ushort	scc_rbptr;	/* Internal */
-	ushort	scc_ibc;	/* Internal */
-	uint	scc_rxtmp;	/* Internal */
-	uint	scc_tstate;	/* Internal */
-	uint	scc_tdp;	/* Internal */
-	ushort	scc_tbptr;	/* Internal */
-	ushort	scc_tbc;	/* Internal */
-	uint	scc_txtmp;	/* Internal */
-	uint	scc_rcrc;	/* Internal */
-	uint	scc_tcrc;	/* Internal */
-} sccp_t;
-
-/* CPM Ethernet through SCC1.
- */
-typedef struct scc_enet {
-	sccp_t	sen_genscc;
-	uint	sen_cpres;	/* Preset CRC */
-	uint	sen_cmask;	/* Constant mask for CRC */
-	uint	sen_crcec;	/* CRC Error counter */
-	uint	sen_alec;	/* alignment error counter */
-	uint	sen_disfc;	/* discard frame counter */
-	ushort	sen_pads;	/* Tx short frame pad character */
-	ushort	sen_retlim;	/* Retry limit threshold */
-	ushort	sen_retcnt;	/* Retry limit counter */
-	ushort	sen_maxflr;	/* maximum frame length register */
-	ushort	sen_minflr;	/* minimum frame length register */
-	ushort	sen_maxd1;	/* maximum DMA1 length */
-	ushort	sen_maxd2;	/* maximum DMA2 length */
-	ushort	sen_maxd;	/* Rx max DMA */
-	ushort	sen_dmacnt;	/* Rx DMA counter */
-	ushort	sen_maxb;	/* Max BD byte count */
-	ushort	sen_gaddr1;	/* Group address filter */
-	ushort	sen_gaddr2;
-	ushort	sen_gaddr3;
-	ushort	sen_gaddr4;
-	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf0rba;	/* Internal */
-	uint	sen_tbuf0crc;	/* Internal */
-	ushort	sen_tbuf0bcnt;	/* Internal */
-	ushort	sen_paddrh;	/* physical address (MSB) */
-	ushort	sen_paddrm;
-	ushort	sen_paddrl;	/* physical address (LSB) */
-	ushort	sen_pper;	/* persistence */
-	ushort	sen_rfbdptr;	/* Rx first BD pointer */
-	ushort	sen_tfbdptr;	/* Tx first BD pointer */
-	ushort	sen_tlbdptr;	/* Tx last BD pointer */
-	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf1rba;	/* Internal */
-	uint	sen_tbuf1crc;	/* Internal */
-	ushort	sen_tbuf1bcnt;	/* Internal */
-	ushort	sen_txlen;	/* Tx Frame length counter */
-	ushort	sen_iaddr1;	/* Individual address filter */
-	ushort	sen_iaddr2;
-	ushort	sen_iaddr3;
-	ushort	sen_iaddr4;
-	ushort	sen_boffcnt;	/* Backoff counter */
-
-	/* NOTE: Some versions of the manual have the following items
-	 * incorrectly documented.  Below is the proper order.
-	 */
-	ushort	sen_taddrh;	/* temp address (MSB) */
-	ushort	sen_taddrm;
-	ushort	sen_taddrl;	/* temp address (LSB) */
-} scc_enet_t;
-
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
-#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* SCC Mode Register (PSMR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
-#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
-#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
-#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
-#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
-#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
-#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
-#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
-#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
-#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
-#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
-#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
-#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
- * Common to SCC and FCC.
- */
-#define BD_ENET_RX_EMPTY	((ushort)0x8000)
-#define BD_ENET_RX_WRAP		((ushort)0x2000)
-#define BD_ENET_RX_INTR		((ushort)0x1000)
-#define BD_ENET_RX_LAST		((ushort)0x0800)
-#define BD_ENET_RX_FIRST	((ushort)0x0400)
-#define BD_ENET_RX_MISS		((ushort)0x0100)
-#define BD_ENET_RX_BC		((ushort)0x0080)	/* FCC Only */
-#define BD_ENET_RX_MC		((ushort)0x0040)	/* FCC Only */
-#define BD_ENET_RX_LG		((ushort)0x0020)
-#define BD_ENET_RX_NO		((ushort)0x0010)
-#define BD_ENET_RX_SH		((ushort)0x0008)
-#define BD_ENET_RX_CR		((ushort)0x0004)
-#define BD_ENET_RX_OV		((ushort)0x0002)
-#define BD_ENET_RX_CL		((ushort)0x0001)
-#define BD_ENET_RX_STATS	((ushort)0x01ff)	/* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
- * Common to SCC and FCC.
- */
-#define BD_ENET_TX_READY	((ushort)0x8000)
-#define BD_ENET_TX_PAD		((ushort)0x4000)
-#define BD_ENET_TX_WRAP		((ushort)0x2000)
-#define BD_ENET_TX_INTR		((ushort)0x1000)
-#define BD_ENET_TX_LAST		((ushort)0x0800)
-#define BD_ENET_TX_TC		((ushort)0x0400)
-#define BD_ENET_TX_DEF		((ushort)0x0200)
-#define BD_ENET_TX_HB		((ushort)0x0100)
-#define BD_ENET_TX_LC		((ushort)0x0080)
-#define BD_ENET_TX_RL		((ushort)0x0040)
-#define BD_ENET_TX_RCMASK	((ushort)0x003c)
-#define BD_ENET_TX_UN		((ushort)0x0002)
-#define BD_ENET_TX_CSL		((ushort)0x0001)
-#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-	sccp_t	scc_genscc;
-	uint	scc_res1;	/* Reserved */
-	uint	scc_res2;	/* Reserved */
-	ushort	scc_maxidl;	/* Maximum idle chars */
-	ushort	scc_idlc;	/* temp idle counter */
-	ushort	scc_brkcr;	/* Break count register */
-	ushort	scc_parec;	/* receive parity error counter */
-	ushort	scc_frmec;	/* receive framing error counter */
-	ushort	scc_nosec;	/* receive noise counter */
-	ushort	scc_brkec;	/* receive break condition counter */
-	ushort	scc_brkln;	/* last received break length */
-	ushort	scc_uaddr1;	/* UART address character 1 */
-	ushort	scc_uaddr2;	/* UART address character 2 */
-	ushort	scc_rtemp;	/* Temp storage */
-	ushort	scc_toseq;	/* Transmit out of sequence char */
-	ushort	scc_char1;	/* control character 1 */
-	ushort	scc_char2;	/* control character 2 */
-	ushort	scc_char3;	/* control character 3 */
-	ushort	scc_char4;	/* control character 4 */
-	ushort	scc_char5;	/* control character 5 */
-	ushort	scc_char6;	/* control character 6 */
-	ushort	scc_char7;	/* control character 7 */
-	ushort	scc_char8;	/* control character 8 */
-	ushort	scc_rccm;	/* receive control character mask */
-	ushort	scc_rccr;	/* receive control character register */
-	ushort	scc_rlbc;	/* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR		((ushort)0x1000)
-#define UART_SCCM_GLT		((ushort)0x0800)
-#define UART_SCCM_AB		((ushort)0x0200)
-#define UART_SCCM_IDL		((ushort)0x0100)
-#define UART_SCCM_GRA		((ushort)0x0080)
-#define UART_SCCM_BRKE		((ushort)0x0040)
-#define UART_SCCM_BRKS		((ushort)0x0020)
-#define UART_SCCM_CCR		((ushort)0x0008)
-#define UART_SCCM_BSY		((ushort)0x0004)
-#define UART_SCCM_TX		((ushort)0x0002)
-#define UART_SCCM_RX		((ushort)0x0001)
-
-/* The SCC PSMR when used as a UART.
-*/
-#define SCU_PSMR_FLC		((ushort)0x8000)
-#define SCU_PSMR_SL		((ushort)0x4000)
-#define SCU_PSMR_CL		((ushort)0x3000)
-#define SCU_PSMR_UM		((ushort)0x0c00)
-#define SCU_PSMR_FRZ		((ushort)0x0200)
-#define SCU_PSMR_RZS		((ushort)0x0100)
-#define SCU_PSMR_SYN		((ushort)0x0080)
-#define SCU_PSMR_DRT		((ushort)0x0040)
-#define SCU_PSMR_PEN		((ushort)0x0010)
-#define SCU_PSMR_RPM		((ushort)0x000c)
-#define SCU_PSMR_REVP		((ushort)0x0008)
-#define SCU_PSMR_TPM		((ushort)0x0003)
-#define SCU_PSMR_TEVP		((ushort)0x0003)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-	sccp_t	st_genscc;
-	uint	st_cpres;	/* Preset CRC */
-	uint	st_cmask;	/* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST		((ushort)0x0800)
-
-/*  SCC as HDLC controller - taken from commproc.h
- */
-typedef struct scc_hdlc {
-	sccp_t  sh_genscc;
-	/*
-	* HDLC specific parameter RAM
-	*/
-	uchar   res[4];         /* reserved */
-	ulong   sh_cmask;       /* CRC constant */
-	ulong   sh_cpres;       /* CRC preset */
-	ushort  sh_disfc;       /* discarded frame counter */
-	ushort  sh_crcec;       /* CRC error counter */
-	ushort  sh_abtsc;       /* abort sequence counter */
-	ushort  sh_nmarc;       /* nonmatching address rx cnt */
-	ushort  sh_retrc;       /* frame retransmission cnt */
-	ushort  sh_mflr;        /* maximum frame length reg */
-	ushort  sh_maxcnt;      /* maximum length counter */
-	ushort  sh_rfthr;       /* received frames threshold */
-	ushort  sh_rfcnt;       /* received frames count */
-	ushort  sh_hmask;       /* user defined frm addr mask */
-	ushort  sh_haddr1;      /* user defined frm address 1 */
-	ushort  sh_haddr2;      /* user defined frm address 2 */
-	ushort  sh_haddr3;      /* user defined frm address 3 */
-	ushort  sh_haddr4;      /* user defined frm address 4 */
-	ushort  tmp;            /* temp */
-	ushort  tmp_mb;         /* temp */
-} scc_hdlc_t;
-
-/* How about some FCCs.....
-*/
-#define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
-#define FCC_GFMR_DIAG_LE	((uint)0x40000000)
-#define FCC_GFMR_DIAG_AE	((uint)0x80000000)
-#define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
-#define FCC_GFMR_TCI		((uint)0x20000000)
-#define FCC_GFMR_TRX		((uint)0x10000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_CDP		((uint)0x04000000)
-#define FCC_GFMR_CTSP		((uint)0x02000000)
-#define FCC_GFMR_CDS		((uint)0x01000000)
-#define FCC_GFMR_CTSS		((uint)0x00800000)
-#define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
-#define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
-#define FCC_GFMR_SYNL_8		((uint)0x00008000)
-#define FCC_GFMR_SYNL_16	((uint)0x0000c000)
-#define FCC_GFMR_RTSM		((uint)0x00002000)
-#define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
-#define FCC_GFMR_REVD		((uint)0x00000400)
-#define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
-#define FCC_GFMR_TCRC_16	((uint)0x00000000)
-#define FCC_GFMR_TCRC_32	((uint)0x00000080)
-#define FCC_GFMR_ENR		((uint)0x00000020)
-#define FCC_GFMR_ENT		((uint)0x00000010)
-#define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
-#define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
-#define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
-
-/* Generic FCC parameter ram.
-*/
-typedef struct fcc_param {
-	ushort	fcc_riptr;	/* Rx Internal temp pointer */
-	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
-	ushort	fcc_res1;
-	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
-	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_rbase;	/* Receive BD base */
-	ushort	fcc_rbdstat;	/* RxBD status */
-	ushort	fcc_rbdlen;	/* RxBD down counter */
-	uint	fcc_rdptr;	/* RxBD internal data pointer */
-	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_tbase;	/* Transmit BD base */
-	ushort	fcc_tbdstat;	/* TxBD status */
-	ushort	fcc_tbdlen;	/* TxBD down counter */
-	uint	fcc_tdptr;	/* TxBD internal data pointer */
-	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
-	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
-	uint	fcc_rcrc;	/* Rx temp CRC */
-	uint	fcc_res2;
-	uint	fcc_tcrc;	/* Tx temp CRC */
-} fccp_t;
-
-
-/* Ethernet controller through FCC.
-*/
-typedef struct fcc_enet {
-	fccp_t	fen_genfcc;
-	uint	fen_statbuf;	/* Internal status buffer */
-	uint	fen_camptr;	/* CAM address */
-	uint	fen_cmask;	/* Constant mask for CRC */
-	uint	fen_cpres;	/* Preset CRC */
-	uint	fen_crcec;	/* CRC Error counter */
-	uint	fen_alec;	/* alignment error counter */
-	uint	fen_disfc;	/* discard frame counter */
-	ushort	fen_retlim;	/* Retry limit */
-	ushort	fen_retcnt;	/* Retry counter */
-	ushort	fen_pper;	/* Persistence */
-	ushort	fen_boffcnt;	/* backoff counter */
-	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
-	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
-	ushort	fen_tfcstat;	/* out of sequence TxBD */
-	ushort	fen_tfclen;
-	uint	fen_tfcptr;
-	ushort	fen_mflr;	/* Maximum frame length (1518) */
-	ushort	fen_paddrh;	/* MAC address */
-	ushort	fen_paddrm;
-	ushort	fen_paddrl;
-	ushort	fen_ibdcount;	/* Internal BD counter */
-	ushort	fen_idbstart;	/* Internal BD start pointer */
-	ushort	fen_ibdend;	/* Internal BD end pointer */
-	ushort	fen_txlen;	/* Internal Tx frame length counter */
-	uint	fen_ibdbase[8]; /* Internal use */
-	uint	fen_iaddrh;	/* Individual address filter */
-	uint	fen_iaddrl;
-	ushort	fen_minflr;	/* Minimum frame length (64) */
-	ushort	fen_taddrh;	/* Filter transfer MAC address */
-	ushort	fen_taddrm;
-	ushort	fen_taddrl;
-	ushort	fen_padptr;	/* Pointer to pad byte buffer */
-	ushort	fen_cftype;	/* control frame type */
-	ushort	fen_cfrange;	/* control frame range */
-	ushort	fen_maxb;	/* maximum BD count */
-	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
-	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
-	ushort	fen_maxd;	/* internal max DMA count */
-	ushort	fen_dmacnt;	/* internal DMA counter */
-	uint	fen_octc;	/* Total octect counter */
-	uint	fen_colc;	/* Total collision counter */
-	uint	fen_broc;	/* Total broadcast packet counter */
-	uint	fen_mulc;	/* Total multicast packet count */
-	uint	fen_uspc;	/* Total packets < 64 bytes */
-	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
-	uint	fen_ospc;	/* Total packets > 1518 */
-	uint	fen_jbrc;	/* Total packets > 1518 with errors */
-	uint	fen_p64c;	/* Total packets == 64 bytes */
-	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
-	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
-	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
-	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
-	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
-	uint	fen_cambuf;	/* Internal CAM buffer poiner */
-	ushort	fen_rfthr;	/* Received frames threshold */
-	ushort	fen_rfcnt;	/* Received frames count */
-} fcc_enet_t;
-
-/* FCC Event/Mask register as used by Ethernet.
-*/
-#define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
-#define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
-#define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
-#define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* FCC Mode Register (FPSMR) as used by Ethernet.
-*/
-#define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
-#define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
-#define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
-#define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
-#define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
-#define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
-#define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
-#define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
-#define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
-#define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
-#define FCC_PSMR_RMII	((uint)0x00020000)	/* Use RMII interface */
-#define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
-#define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
-#define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
-	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
-	u_char	iic_rfcr;	/* Rx function code */
-	u_char	iic_tfcr;	/* Tx function code */
-	ushort	iic_mrblr;	/* Max receive buffer length */
-	uint	iic_rstate;	/* Internal */
-	uint	iic_rdp;	/* Internal */
-	ushort	iic_rbptr;	/* Internal */
-	ushort	iic_rbc;	/* Internal */
-	uint	iic_rxtmp;	/* Internal */
-	uint	iic_tstate;	/* Internal */
-	uint	iic_tdp;	/* Internal */
-	ushort	iic_tbptr;	/* Internal */
-	ushort	iic_tbc;	/* Internal */
-	uint	iic_txtmp;	/* Internal */
-} iic_t;
-
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
-	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
-	u_char	spi_rfcr;	/* Rx function code */
-	u_char	spi_tfcr;	/* Tx function code */
-	ushort	spi_mrblr;	/* Max receive buffer length */
-	uint	spi_rstate;	/* Internal */
-	uint	spi_rdp;	/* Internal */
-	ushort	spi_rbptr;	/* Internal */
-	ushort	spi_rbc;	/* Internal */
-	uint	spi_rxtmp;	/* Internal */
-	uint	spi_tstate;	/* Internal */
-	uint	spi_tdp;	/* Internal */
-	ushort	spi_tbptr;	/* Internal */
-	ushort	spi_tbc;	/* Internal */
-	uint	spi_txtmp;	/* Internal */
-	uint	spi_res;	/* Tx temp. */
-	uint	spi_res1[4];	/* SDMA temp. */
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
-#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
-#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
-#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
-#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
-#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
-#define SPMODE_EN	((ushort)0x0100)	/* Enable */
-#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
-#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
-
-#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x)	((x) &0xF)
-
-/* SPI Event/Mask register.
-*/
-#define SPI_EMASK		0x37	/* Event Mask				*/
-#define SPI_MME			0x20	/* Multi-Master Error			*/
-#define SPI_TXE			0x10	/* Transmit Error			*/
-#define SPI_BSY			0x04	/* Busy					*/
-#define SPI_TXB			0x02	/* Tx Buffer Empty			*/
-#define SPI_RXB			0x01	/* RX Buffer full/closed		*/
-
-#define SPI_STR			0x80	/* SPCOM: Start transmit		*/
-
-#define SPI_EB		((u_char)0x10)		/* big endian byte order */
-
-#define BD_IIC_START		((ushort)0x0400)
-
-#endif /* __CPM_82XX__ */
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 3943d0e92b..d0c3fa05f8 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -19,9 +19,6 @@ struct arch_global_data {
 	u8 sdhc_adapter;
 #endif
 #endif
-#if defined(CONFIG_8xx)
-	unsigned long brg_clk;
-#endif
 #if defined(CONFIG_CPM2)
 	/* There are many clocks on the MPC8260 - see page 9-5 */
 	unsigned long vco_out;
@@ -84,13 +81,6 @@ struct arch_global_data {
 #if defined(CONFIG_E500)
 	u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
 #endif
-#if defined(CONFIG_MPC5xxx)
-	unsigned long ipb_clk;
-#endif
-#if defined(CONFIG_MPC512X)
-	u32 ips_clk;
-	u32 csb_clk;
-#endif /* CONFIG_MPC512X */
 	unsigned long reset_status;	/* reset status register at boot */
 #if defined(CONFIG_MPC83xx)
 	unsigned long arbiter_event_attributes;
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
deleted file mode 100644
index bed80aa933..0000000000
--- a/arch/powerpc/include/asm/immap_512x.h
+++ /dev/null
@@ -1,1264 +0,0 @@
-/*
- * (C) Copyright 2007-2009 DENX Software Engineering
- *
- * MPC512x Internal Memory Map
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Based on the MPC83xx header.
- */
-
-#ifndef __IMMAP_512x__
-#define __IMMAP_512x__
-
-#include <asm/types.h>
-#if defined(CONFIG_E300)
-#include <asm/e300.h>
-#endif
-
-/*
- * System reset offset (PowerPC standard)
- */
-#define EXC_OFF_SYS_RESET	0x0100
-#define	_START_OFFSET		EXC_OFF_SYS_RESET
-
-#define SPR_5121E		0x80180000
-
-/*
- * IMMRBAR - Internal Memory Register Base Address
- */
-#define CONFIG_DEFAULT_IMMR	0xFF400000	/* Default IMMR base address */
-#define IMMRBAR			0x0000		/* Register offset to immr */
-#define IMMRBAR_BASE_ADDR	0xFFF00000	/* Base address mask */
-#define IMMRBAR_RES		~(IMMRBAR_BASE_ADDR)
-
-
-#ifndef __ASSEMBLY__
-typedef struct law512x {
-	u32 bar;	/* Base Addr Register */
-	u32 ar;		/* Attributes Register */
-} law512x_t;
-
-/*
- * System configuration registers
- */
-typedef struct sysconf512x {
-	u32 immrbar;		/* Internal memory map base address register */
-	u8 res0[0x1c];
-	u32 lpbaw;		/* LP Boot Access Window */
-	u32 lpcs0aw;		/* LP CS0 Access Window */
-	u32 lpcs1aw;		/* LP CS1 Access Window */
-	u32 lpcs2aw;		/* LP CS2 Access Window */
-	u32 lpcs3aw;		/* LP CS3 Access Window */
-	u32 lpcs4aw;		/* LP CS4 Access Window */
-	u32 lpcs5aw;		/* LP CS5 Access Window */
-	u32 lpcs6aw;		/* LP CS6 Access Window */
-	u32 lpcs7aw;		/* LP CS7 Access Window */
-	u8 res1[0x1c];
-	law512x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
-	u8 res2[0x28];
-	law512x_t ddrlaw;	/* DDR Local Access Window */
-	u8 res3[0x18];
-	u32 mbxbar;		/* MBX Base Address */
-	u32 srambar;		/* SRAM Base Address */
-	u32 nfcbar;		/* NFC Base Address */
-	u8 res4[0x34];
-	u32 spridr;		/* System Part and Revision ID Register */
-	u32 spcr;		/* System Priority Configuration Register */
-	u8 res5[0xf8];
-} sysconf512x_t;
-
-#define LAWBAR_BAR	0xFFFFF000	/* Base address mask */
-
-/*
- * Watch Dog Timer (WDT) Registers
- */
-typedef struct wdt512x {
-	u8 res0[4];
-	u32 swcrr;		/* System watchdog control register */
-	u32 swcnr;		/* System watchdog count register */
-	u8 res1[2];
-	u16 swsrr;		/* System watchdog service register */
-	u8 res2[0xF0];
-} wdt512x_t;
-
-/*
- * RTC Module Registers
- */
-typedef struct rtclk512x {
-	u8 fixme[0x100];
-} rtclk512x_t;
-
-/*
- * General Purpose Timer
- */
-typedef struct gpt512x {
-	u8 fixme[0x100];
-} gpt512x_t;
-
-/*
- * Integrated Programmable Interrupt Controller
- */
-typedef struct ipic512x {
-	u8 fixme[0x100];
-} ipic512x_t;
-
-/*
- * System Arbiter Registers
- */
-typedef struct arbiter512x {
-	u32 acr;		/* Arbiter Configuration Register */
-	u32 atr;		/* Arbiter Timers Register */
-	u32 ater;		/* Arbiter Transfer Error Register */
-	u32 aer;		/* Arbiter Event Register */
-	u32 aidr;		/* Arbiter Interrupt Definition Register */
-	u32 amr;		/* Arbiter Mask Register */
-	u32 aeatr;		/* Arbiter Event Attributes Register */
-	u32 aeadr;		/* Arbiter Event Address Register */
-	u32 aerr;		/* Arbiter Event Response Register */
-	u8 res1[0xDC];
-} arbiter512x_t;
-
-/*
- * Reset Module
- */
-typedef struct reset512x {
-	u32 rcwl;		/* Reset Configuration Word Low Register */
-	u32 rcwh;		/* Reset Configuration Word High Register */
-	u8 res0[8];
-	u32 rsr;		/* Reset Status Register */
-	u32 rmr;		/* Reset Mode Register */
-	u32 rpr;		/* Reset protection Register */
-	u32 rcr;		/* Reset Control Register */
-	u32 rcer;		/* Reset Control Enable Register */
-	u8 res1[0xDC];
-} reset512x_t;
-
-/* RSR - Reset Status Register */
-#define RSR_SWSR	0x00002000	/* software soft reset */
-#define RSR_SWHR	0x00001000	/* software hard reset */
-#define RSR_JHRS	0x00000200	/* jtag hreset */
-#define RSR_JSRS	0x00000100	/* jtag sreset status */
-#define RSR_CSHR	0x00000010	/* checkstop reset status */
-#define RSR_SWRS	0x00000008	/* software watchdog reset status */
-#define RSR_BMRS	0x00000004	/* bus monitop reset status */
-#define RSR_SRS		0x00000002	/* soft reset status */
-#define RSR_HRS		0x00000001	/* hard reset status */
-#define RSR_RES		~(RSR_SWSR | RSR_SWHR |\
-			 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
-			 RSR_BMRS | RSR_SRS | RSR_HRS)
-
-/* RMR - Reset Mode Register */
-#define RMR_CSRE	0x00000001	/* checkstop reset enable */
-#define RMR_CSRE_SHIFT	0
-#define RMR_RES		(~(RMR_CSRE))
-
-/* RCR - Reset Control Register */
-#define RCR_SWHR	0x00000002	/* software hard reset */
-#define RCR_SWSR	0x00000001	/* software soft reset */
-#define RCR_RES		(~(RCR_SWHR | RCR_SWSR))
-
-/* RCER - Reset Control Enable Register */
-#define RCER_CRE	0x00000001	/* software hard reset */
-#define RCER_RES	(~(RCER_CRE))
-
-/*
- * Clock Module
- */
-typedef struct clk512x {
-	u32 spmr;		/* System PLL Mode Register */
-	u32 sccr[2];		/* System Clock Control Registers */
-	u32 scfr[2];		/* System Clock Frequency Registers */
-	u8 res0[4];
-	u32 bcr;		/* Bread Crumb Register */
-	u32 pscccr[12];		/* PSC0-11 Clock Control Registers */
-	u32 spccr;		/* SPDIF Clock Control Register */
-	u32 cccr;		/* CFM Clock Control Register */
-	u32 dccr;		/* DIU Clock Control Register */
-	u32 msccr[4];		/* MSCAN1-4 Clock Control Registers */
-	u8 res1[0x98];
-} clk512x_t;
-
-/* SPMR - System PLL Mode Register */
-#define SPMR_SPMF		0x0F000000
-#define SPMR_SPMF_SHIFT		24
-#define SPMR_CPMF		0x000F0000
-#define SPMR_CPMF_SHIFT		16
-
-/* System Clock Control Register 1 commands */
-#define CLOCK_SCCR1_CFG_EN		0x80000000
-#define CLOCK_SCCR1_LPC_EN		0x40000000
-#define CLOCK_SCCR1_NFC_EN		0x20000000
-#define CLOCK_SCCR1_PATA_EN		0x10000000
-#define CLOCK_SCCR1_PSC_EN(cn)		(0x08000000 >> (cn))
-#define CLOCK_SCCR1_PSCFIFO_EN		0x00008000
-#define CLOCK_SCCR1_SATA_EN		0x00004000
-#define CLOCK_SCCR1_FEC_EN		0x00002000
-#define CLOCK_SCCR1_TPR_EN		0x00001000
-#define CLOCK_SCCR1_PCI_EN		0x00000800
-#define CLOCK_SCCR1_DDR_EN		0x00000400
-
-/* System Clock Control Register 2 commands */
-#define CLOCK_SCCR2_DIU_EN		0x80000000
-#define CLOCK_SCCR2_AXE_EN		0x40000000
-#define CLOCK_SCCR2_MEM_EN		0x20000000
-#define CLOCK_SCCR2_USB1_EN		0x10000000
-#define CLOCK_SCCR2_USB2_EN		0x08000000
-#define CLOCK_SCCR2_I2C_EN		0x04000000
-#define CLOCK_SCCR2_BDLC_EN		0x02000000
-#define CLOCK_SCCR2_SDHC_EN		0x01000000
-#define CLOCK_SCCR2_SPDIF_EN		0x00800000
-#define CLOCK_SCCR2_MBX_BUS_EN		0x00400000
-#define CLOCK_SCCR2_MBX_EN		0x00200000
-#define CLOCK_SCCR2_MBX_3D_EN		0x00100000
-#define CLOCK_SCCR2_IIM_EN		0x00080000
-
-/* SCFR1 System Clock Frequency Register 1 */
-#ifndef SCFR1_IPS_DIV
-#define SCFR1_IPS_DIV		0x3
-#endif
-#define SCFR1_IPS_DIV_MASK	0x03800000
-#define SCFR1_IPS_DIV_SHIFT	23
-
-#define SCFR1_PCI_DIV		0x6
-#define SCFR1_PCI_DIV_MASK	0x00700000
-#define SCFR1_PCI_DIV_SHIFT	20
-
-#define SCFR1_LPC_DIV_MASK	0x00003800
-#define SCFR1_LPC_DIV_SHIFT	11
-
-#define SCFR1_NFC_DIV_MASK	0x00000700
-#define SCFR1_NFC_DIV_SHIFT	8
-
-#define SCFR1_DIU_DIV_MASK	0x000000FF
-#define SCFR1_DIU_DIV_SHIFT	0
-
-/* SCFR2 System Clock Frequency Register 2 */
-#define SCFR2_SYS_DIV		0xFC000000
-#define SCFR2_SYS_DIV_SHIFT	26
-
-/* SPCR - System Priority Configuration Register */
-#define SPCR_TBEN	0x00400000	/* E300 core time base unit enable */
-
-/*
- * Power Management Control Module
- */
-typedef struct pmc512x {
-	u8 fixme[0x100];
-} pmc512x_t;
-
-/*
- * General purpose I/O module
- */
-typedef struct gpio512x {
-	u32 gpdir;
-	u32 gpodr;
-	u32 gpdat;
-	u32 gpier;
-	u32 gpimr;
-	u32 gpicr1;
-	u32 gpicr2;
-	u8 res0[0xE4];
-} gpio512x_t;
-
-/*
- * DDR Memory Controller Memory Map
- */
-typedef struct ddr512x {
-	u32 ddr_sys_config;	/* System Configuration Register */
-	u32 ddr_time_config0;	/* Timing Configuration Register */
-	u32 ddr_time_config1;	/* Timing Configuration Register */
-	u32 ddr_time_config2;	/* Timing Configuration Register */
-	u32 ddr_command;	/* Command Register */
-	u32 ddr_compact_command;	/* Compact Command Register */
-	u32 self_refresh_cmd_0;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_1;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_2;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_3;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_4;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
-	u32 dqs_config_offset_count;	/* DQS Config Offset Count */
-	u32 dqs_config_offset_time;	/* DQS Config Offset Time */
-	u32 DQS_delay_status;	/* DQS Delay Status */
-	u32 res0[0xF];
-	u32 prioman_config1;	/* Priority Manager Configuration */
-	u32 prioman_config2;	/* Priority Manager Configuration */
-	u32 hiprio_config;	/* High Priority Configuration */
-	u32 lut_table0_main_upper;	/* LUT0 Main Upper */
-	u32 lut_table1_main_upper;	/* LUT1 Main Upper */
-	u32 lut_table2_main_upper;	/* LUT2 Main Upper */
-	u32 lut_table3_main_upper;	/* LUT3 Main Upper */
-	u32 lut_table4_main_upper;	/* LUT4 Main Upper */
-	u32 lut_table0_main_lower;	/* LUT0 Main Lower */
-	u32 lut_table1_main_lower;	/* LUT1 Main Lower */
-	u32 lut_table2_main_lower;	/* LUT2 Main Lower */
-	u32 lut_table3_main_lower;	/* LUT3 Main Lower */
-	u32 lut_table4_main_lower;	/* LUT4 Main Lower */
-	u32 lut_table0_alternate_upper;	/* LUT0 Alternate Upper */
-	u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
-	u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
-	u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
-	u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
-	u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
-	u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
-	u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
-	u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
-	u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
-	u32 performance_monitor_config;
-	u32 event_time_counter;
-	u32 event_time_preset;
-	u32 performance_monitor1_address_low;
-	u32 performance_monitor2_address_low;
-	u32 performance_monitor1_address_hi;
-	u32 performance_monitor2_address_hi;
-	u32 res1[2];
-	u32 performance_monitor1_read_counter;
-	u32 performance_monitor2_read_counter;
-	u32 performance_monitor1_write_counter;
-	u32 performance_monitor2_write_counter;
-	u32 granted_ack_counter0;
-	u32 granted_ack_counter1;
-	u32 granted_ack_counter2;
-	u32 granted_ack_counter3;
-	u32 granted_ack_counter4;
-	u32 cumulative_wait_counter0;
-	u32 cumulative_wait_counter1;
-	u32 cumulative_wait_counter2;
-	u32 cumulative_wait_counter3;
-	u32 cumulative_wait_counter4;
-	u32 summed_priority_counter0;
-	u32 summed_priority_counter1;
-	u32 summed_priority_counter2;
-	u32 summed_priority_counter3;
-	u32 summed_priority_counter4;
-	u32 res2[0x3AD];
-} ddr512x_t;
-
-/* MDDRC SYS CFG and Timing CFG0 Registers */
-#define MDDRC_SYS_CFG_EN	0xF0000000
-#define MDDRC_SYS_CFG_CKE_MASK	0x40000000
-#define MDDRC_SYS_CFG_CMD_MASK	0x10000000
-#define MDDRC_REFRESH_ZERO_MASK	0x0000FFFF
-
-/*
- * DDR Memory Controller Configuration settings
- */
-typedef struct ddr512x_config {
-	u32 ddr_sys_config;	/* System Configuration Register */
-	u32 ddr_time_config0;	/* Timing Configuration Register */
-	u32 ddr_time_config1;	/* Timing Configuration Register */
-	u32 ddr_time_config2;	/* Timing Configuration Register */
-} ddr512x_config_t;
-
-typedef struct sdram_conf_s {
-	unsigned long size;
-	ddr512x_config_t cfg;
-} sdram_conf_t;
-
-/*
- * DMA/Messaging Unit
- */
-typedef struct dma512x {
-	u8 fixme[0x1800];
-} dma512x_t;
-
-/*
- * PCI Software Configuration Registers
- */
-typedef struct pciconf512x {
-	u32 config_address;
-	u32 config_data;
-	u32 int_ack;
-	u8 res[116];
-} pciconf512x_t;
-
-/*
- * PCI Outbound Translation Register
- */
-typedef struct pci_outbound_window {
-	u32 potar;
-	u8 res0[4];
-	u32 pobar;
-	u8 res1[4];
-	u32 pocmr;
-	u8 res2[4];
-} pot512x_t;
-
-/* POTAR - PCI Outbound Translation Address Register */
-#define POTAR_TA_MASK	0x000fffff
-
-/* POBAR - PCI Outbound Base Address Register */
-#define POBAR_BA_MASK	0x000fffff
-
-/* POCMR - PCI Outbound Comparision Mask Register */
-#define POCMR_EN	0x80000000
-#define POCMR_IO	0x40000000	/* 0-memory space 1-I/O space */
-#define POCMR_PRE	0x20000000	/* prefetch enable */
-#define POCMR_SBS	0x00100000	/* special byte swap enable */
-#define POCMR_CM_MASK	0x000fffff
-#define POCMR_CM_4G	0x00000000
-#define POCMR_CM_2G	0x00080000
-#define POCMR_CM_1G	0x000C0000
-#define POCMR_CM_512M	0x000E0000
-#define POCMR_CM_256M	0x000F0000
-#define POCMR_CM_128M	0x000F8000
-#define POCMR_CM_64M	0x000FC000
-#define POCMR_CM_32M	0x000FE000
-#define POCMR_CM_16M	0x000FF000
-#define POCMR_CM_8M	0x000FF800
-#define POCMR_CM_4M	0x000FFC00
-#define POCMR_CM_2M	0x000FFE00
-#define POCMR_CM_1M	0x000FFF00
-#define POCMR_CM_512K	0x000FFF80
-#define POCMR_CM_256K	0x000FFFC0
-#define POCMR_CM_128K	0x000FFFE0
-#define POCMR_CM_64K	0x000FFFF0
-#define POCMR_CM_32K	0x000FFFF8
-#define POCMR_CM_16K	0x000FFFFC
-#define POCMR_CM_8K	0x000FFFFE
-#define POCMR_CM_4K	0x000FFFFF
-
-/*
- * Sequencer
- */
-typedef struct ios512x {
-	pot512x_t pot[6];
-	u8 res0[0x60];
-	u32 pmcr;
-	u8 res1[4];
-	u32 dtcr;
-	u8 res2[4];
-} ios512x_t;
-
-/*
- * PCI Controller
- */
-typedef struct pcictrl512x {
-	u32 esr;
-	u32 ecdr;
-	u32 eer;
-	u32 eatcr;
-	u32 eacr;
-	u32 eeacr;
-	u32 edlcr;
-	u32 edhcr;
-	u32 gcr;
-	u32 ecr;
-	u32 gsr;
-	u8 res0[12];
-	u32 pitar2;
-	u8 res1[4];
-	u32 pibar2;
-	u32 piebar2;
-	u32 piwar2;
-	u8 res2[4];
-	u32 pitar1;
-	u8 res3[4];
-	u32 pibar1;
-	u32 piebar1;
-	u32 piwar1;
-	u8 res4[4];
-	u32 pitar0;
-	u8 res5[4];
-	u32 pibar0;
-	u8 res6[4];
-	u32 piwar0;
-	u8 res7[132];
-} pcictrl512x_t;
-
-
-/* PITAR - PCI Inbound Translation Address Register
- */
-#define PITAR_TA_MASK	0x000fffff
-
-/* PIBAR - PCI Inbound Base/Extended Address Register
- */
-#define PIBAR_MASK	0xffffffff
-#define PIEBAR_EBA_MASK	0x000fffff
-
-/* PIWAR - PCI Inbound Windows Attributes Register
- */
-#define PIWAR_EN	0x80000000
-#define PIWAR_SBS	0x40000000
-#define PIWAR_PF	0x20000000
-#define PIWAR_RTT_MASK	0x000f0000
-#define PIWAR_RTT_NO_SNOOP 0x00040000
-#define PIWAR_RTT_SNOOP	0x00050000
-#define PIWAR_WTT_MASK	0x0000f000
-#define PIWAR_WTT_NO_SNOOP 0x00004000
-#define PIWAR_WTT_SNOOP	0x00005000
-
-/*
- * MSCAN
- */
-typedef struct mscan512x {
-	u8 fixme[0x100];
-} mscan512x_t;
-
-/*
- * BDLC
- */
-typedef struct bdlc512x {
-	u8 fixme[0x100];
-} bdlc512x_t;
-
-/*
- * SDHC
- */
-typedef struct sdhc512x {
-	u8 fixme[0x100];
-} sdhc512x_t;
-
-/*
- * SPDIF
- */
-typedef struct spdif512x {
-	u8 fixme[0x100];
-} spdif512x_t;
-
-/*
- * I2C
- */
-typedef struct i2c512x_dev {
-	volatile u32 madr;		/* I2Cn + 0x00 */
-	volatile u32 mfdr;		/* I2Cn + 0x04 */
-	volatile u32 mcr;		/* I2Cn + 0x08 */
-	volatile u32 msr;		/* I2Cn + 0x0C */
-	volatile u32 mdr;		/* I2Cn + 0x10 */
-	u8 res0[0x0C];
-} i2c512x_dev_t;
-
-/* Number of I2C buses */
-#define I2C_BUS_CNT	3
-
-typedef struct i2c512x {
-	i2c512x_dev_t dev[I2C_BUS_CNT];
-	volatile u32 icr;
-	volatile u32 mifr;
-	u8 res0[0x98];
-} i2c512x_t;
-
-/* I2Cn control register bits */
-#define I2C_EN		0x80
-#define I2C_IEN		0x40
-#define I2C_STA		0x20
-#define I2C_TX		0x10
-#define I2C_TXAK	0x08
-#define I2C_RSTA	0x04
-#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
-
-/* I2Cn status register bits */
-#define I2C_CF		0x80
-#define I2C_AAS		0x40
-#define I2C_BB		0x20
-#define I2C_AL		0x10
-#define I2C_SRW		0x04
-#define I2C_IF		0x02
-#define I2C_RXAK	0x01
-
-/*
- * AXE
- */
-typedef struct axe512x {
-	u8 fixme[0x100];
-} axe512x_t;
-
-/*
- * DIU
- */
-typedef struct diu512x {
-	u8 fixme[0x100];
-} diu512x_t;
-
-/*
- * CFM
- */
-typedef struct cfm512x {
-	u8 fixme[0x100];
-} cfm512x_t;
-
-/*
- * FEC
- */
-typedef struct fec512x {
-	u32	fec_id;		/* FEC_ID register */
-	u32	ievent;		/* Interrupt event register */
-	u32	imask;		/* Interrupt mask register */
-	u32	reserved_01;
-	u32	r_des_active;	/* Receive ring updated flag */
-	u32	x_des_active;	/* Transmit ring updated flag */
-	u32	reserved_02[3];
-	u32	ecntrl;		/* Ethernet control register */
-	u32	reserved_03[6];
-	u32	mii_data;	/* MII data register */
-	u32	mii_speed;	/* MII speed register */
-	u32	reserved_04[7];
-	u32	mib_control;	/* MIB control/status register */
-	u32	reserved_05[7];
-	u32	r_cntrl;	/* Receive control register */
-	u32	r_hash;		/* Receive hash */
-	u32	reserved_06[14];
-	u32	x_cntrl;	/* Transmit control register */
-	u32	reserved_07[7];
-	u32	paddr1;		/* Physical address low */
-	u32	paddr2;		/* Physical address high + type field */
-	u32	op_pause;	/* Opcode + pause duration */
-	u32	reserved_08[10];
-	u32	iaddr1;		/* Upper 32 bits of individual hash table */
-	u32	iaddr2;		/* Lower 32 bits of individual hash table */
-	u32	gaddr1;		/* Upper 32 bits of group hash table */
-	u32	gaddr2;		/* Lower 32 bits of group hash table */
-	u32	reserved_09[7];
-	u32	x_wmrk;		/* Transmit FIFO watermark */
-	u32	reserved_10;
-	u32	r_bound;	/* End of RAM */
-	u32	r_fstart;	/* Receive FIFO start address */
-	u32	reserved_11[11];
-	u32	r_des_start;	/* Beginning of receive descriptor ring */
-	u32	x_des_start;	/* Pointer to beginning of transmit descriptor ring */
-	u32	r_buff_size;	/* Receive buffer size */
-	u32	reserved_12[26];
-	u32	dma_control;	/* DMA control for IP bus, AMBA IF + DMA revision */
-	u32	reserved_13[2];
-
-	u32	mib[128];	/* MIB Block Counters */
-
-	u32	fifo[256];	/*  used by FEC, can only be accessed by DMA */
-} fec512x_t;
-
-/*
- * ULPI
- */
-typedef struct ulpi512x {
-	u8 fixme[0x600];
-} ulpi512x_t;
-
-/*
- * UTMI
- */
-typedef struct utmi512x {
-	u8 fixme[0x3000];
-} utmi512x_t;
-
-/*
- * PCI DMA
- */
-typedef struct pcidma512x {
-	u8 fixme[0x300];
-} pcidma512x_t;
-
-/*
- * IO Control
- */
-typedef struct ioctrl512x {
-	u32	io_control_mem;			/* MEM pad ctrl reg */
-	u32	io_control_gp;			/* GP pad ctrl reg */
-	u32	io_control_lpc_clk;		/* LPC_CLK pad ctrl reg */
-	u32	io_control_lpc_oe;		/* LPC_OE pad ctrl reg */
-	u32	io_control_lpc_rw;		/* LPC_R/W pad ctrl reg */
-	u32	io_control_lpc_ack;		/* LPC_ACK pad ctrl reg */
-	u32	io_control_lpc_cs0;		/* LPC_CS0 pad ctrl reg */
-	u32	io_control_nfc_ce0;		/* NFC_CE0 pad ctrl reg */
-	u32	io_control_lpc_cs1;		/* LPC_CS1 pad ctrl reg */
-	u32	io_control_lpc_cs2;		/* LPC_CS2 pad ctrl reg */
-	u32	io_control_lpc_ax03;		/* LPC_AX03 pad ctrl reg */
-	u32	io_control_emb_ax02;		/* EMB_AX02 pad ctrl reg */
-	u32	io_control_emb_ax01;		/* EMB_AX01 pad ctrl reg */
-	u32	io_control_emb_ax00;		/* EMB_AX00 pad ctrl reg */
-	u32	io_control_emb_ad31;		/* EMB_AD31 pad ctrl reg */
-	u32	io_control_emb_ad30;		/* EMB_AD30 pad ctrl reg */
-	u32	io_control_emb_ad29;		/* EMB_AD29 pad ctrl reg */
-	u32	io_control_emb_ad28;		/* EMB_AD28 pad ctrl reg */
-	u32	io_control_emb_ad27;		/* EMB_AD27 pad ctrl reg */
-	u32	io_control_emb_ad26;		/* EMB_AD26 pad ctrl reg */
-	u32	io_control_emb_ad25;		/* EMB_AD25 pad ctrl reg */
-	u32	io_control_emb_ad24;		/* EMB_AD24 pad ctrl reg */
-	u32	io_control_emb_ad23;		/* EMB_AD23 pad ctrl reg */
-	u32	io_control_emb_ad22;		/* EMB_AD22 pad ctrl reg */
-	u32	io_control_emb_ad21;		/* EMB_AD21 pad ctrl reg */
-	u32	io_control_emb_ad20;		/* EMB_AD20 pad ctrl reg */
-	u32	io_control_emb_ad19;		/* EMB_AD19 pad ctrl reg */
-	u32	io_control_emb_ad18;		/* EMB_AD18 pad ctrl reg */
-	u32	io_control_emb_ad17;		/* EMB_AD17 pad ctrl reg */
-	u32	io_control_emb_ad16;		/* EMB_AD16 pad ctrl reg */
-	u32	io_control_emb_ad15;		/* EMB_AD15 pad ctrl reg */
-	u32	io_control_emb_ad14;		/* EMB_AD14 pad ctrl reg */
-	u32	io_control_emb_ad13;		/* EMB_AD13 pad ctrl reg */
-	u32	io_control_emb_ad12;		/* EMB_AD12 pad ctrl reg */
-	u32	io_control_emb_ad11;		/* EMB_AD11 pad ctrl reg */
-	u32	io_control_emb_ad10;		/* EMB_AD10 pad ctrl reg */
-	u32	io_control_emb_ad09;		/* EMB_AD09 pad ctrl reg */
-	u32	io_control_emb_ad08;		/* EMB_AD08 pad ctrl reg */
-	u32	io_control_emb_ad07;		/* EMB_AD07 pad ctrl reg */
-	u32	io_control_emb_ad06;		/* EMB_AD06 pad ctrl reg */
-	u32	io_control_emb_ad05;		/* EMB_AD05 pad ctrl reg */
-	u32	io_control_emb_ad04;		/* EMB_AD04 pad ctrl reg */
-	u32	io_control_emb_ad03;		/* EMB_AD03 pad ctrl reg */
-	u32	io_control_emb_ad02;		/* EMB_AD02 pad ctrl reg */
-	u32	io_control_emb_ad01;		/* EMB_AD01 pad ctrl reg */
-	u32	io_control_emb_ad00;		/* EMB_AD00 pad ctrl reg */
-	u32	io_control_pata_ce1;		/* PATA_CE1 pad ctrl reg */
-	u32	io_control_pata_ce2;		/* PATA_CE2 pad ctrl reg */
-	u32	io_control_pata_isolate;	/* PATA_ISOLATE pad ctrl reg */
-	u32	io_control_pata_ior;		/* PATA_IOR pad ctrl reg */
-	u32	io_control_pata_iow;		/* PATA_IOW pad ctrl reg */
-	u32	io_control_pata_iochrdy;	/* PATA_IOCHRDY pad ctrl reg */
-	u32	io_control_pata_intrq;		/* PATA_INTRQ pad ctrl reg */
-	u32	io_control_pata_drq;		/* PATA_DRQ pad ctrl reg */
-	u32	io_control_pata_dack;		/* PATA_DACK pad ctrl reg */
-	u32	io_control_nfc_wp;		/* NFC_WP pad ctrl reg */
-	u32	io_control_nfc_rb;		/* NFC_RB pad ctrl reg */
-	u32	io_control_nfc_ale;		/* NFC_ALE pad ctrl reg */
-	u32	io_control_nfc_cle;		/* NFC_CLE pad ctrl reg */
-	u32	io_control_nfc_we;		/* NFC_WE pad ctrl reg */
-	u32	io_control_nfc_re;		/* NFC_RE pad ctrl reg */
-	u32	io_control_pci_ad31;		/* PCI_AD31 pad ctrl reg */
-	u32	io_control_pci_ad30;		/* PCI_AD30 pad ctrl reg */
-	u32	io_control_pci_ad29;		/* PCI_AD29 pad ctrl reg */
-	u32	io_control_pci_ad28;		/* PCI_AD28 pad ctrl reg */
-	u32	io_control_pci_ad27;		/* PCI_AD27 pad ctrl reg */
-	u32	io_control_pci_ad26;		/* PCI_AD26 pad ctrl reg */
-	u32	io_control_pci_ad25;		/* PCI_AD25 pad ctrl reg */
-	u32	io_control_pci_ad24;		/* PCI_AD24 pad ctrl reg */
-	u32	io_control_pci_ad23;		/* PCI_AD23 pad ctrl reg */
-	u32	io_control_pci_ad22;		/* PCI_AD22 pad ctrl reg */
-	u32	io_control_pci_ad21;		/* PCI_AD21 pad ctrl reg */
-	u32	io_control_pci_ad20;		/* PCI_AD20 pad ctrl reg */
-	u32	io_control_pci_ad19;		/* PCI_AD19 pad ctrl reg */
-	u32	io_control_pci_ad18;		/* PCI_AD18 pad ctrl reg */
-	u32	io_control_pci_ad17;		/* PCI_AD17 pad ctrl reg */
-	u32	io_control_pci_ad16;		/* PCI_AD16 pad ctrl reg */
-	u32	io_control_pci_ad15;		/* PCI_AD15 pad ctrl reg */
-	u32	io_control_pci_ad14;		/* PCI_AD14 pad ctrl reg */
-	u32	io_control_pci_ad13;		/* PCI_AD13 pad ctrl reg */
-	u32	io_control_pci_ad12;		/* PCI_AD12 pad ctrl reg */
-	u32	io_control_pci_ad11;		/* PCI_AD11 pad ctrl reg */
-	u32	io_control_pci_ad10;		/* PCI_AD10 pad ctrl reg */
-	u32	io_control_pci_ad09;		/* PCI_AD09 pad ctrl reg */
-	u32	io_control_pci_ad08;		/* PCI_AD08 pad ctrl reg */
-	u32	io_control_pci_ad07;		/* PCI_AD07 pad ctrl reg */
-	u32	io_control_pci_ad06;		/* PCI_AD06 pad ctrl reg */
-	u32	io_control_pci_ad05;		/* PCI_AD05 pad ctrl reg */
-	u32	io_control_pci_ad04;		/* PCI_AD04 pad ctrl reg */
-	u32	io_control_pci_ad03;		/* PCI_AD03 pad ctrl reg */
-	u32	io_control_pci_ad02;		/* PCI_AD02 pad ctrl reg */
-	u32	io_control_pci_ad01;		/* PCI_AD01 pad ctrl reg */
-	u32	io_control_pci_ad00;		/* PCI_AD00 pad ctrl reg */
-	u32	io_control_pci_cbe0;		/* PCI_CBE0 pad ctrl reg */
-	u32	io_control_pci_cbe1;		/* PCI_CBE1 pad ctrl reg */
-	u32	io_control_pci_cbe2;		/* PCI_CBE2 pad ctrl reg */
-	u32	io_control_pci_cbe3;		/* PCI_CBE3 pad ctrl reg */
-	u32	io_control_pci_grant2;		/* PCI_GRANT2 pad ctrl reg */
-	u32	io_control_pci_req2;		/* PCI_REQ2 pad ctrl reg */
-	u32	io_control_pci_grant1;		/* PCI_GRANT1 pad ctrl reg */
-	u32	io_control_pci_req1;		/* PCI_REQ1 pad ctrl reg */
-	u32	io_control_pci_grant0;		/* PCI_GRANT0 pad ctrl reg */
-	u32	io_control_pci_req0;		/* PCI_REQ0 pad ctrl reg */
-	u32	io_control_pci_inta;		/* PCI_INTA pad ctrl reg */
-	u32	io_control_pci_clk;		/* PCI_CLK pad ctrl reg */
-	u32	io_control_pci_rst;		/* PCI_RST- pad ctrl reg */
-	u32	io_control_pci_frame;		/* PCI_FRAME pad ctrl reg */
-	u32	io_control_pci_idsel;		/* PCI_IDSEL pad ctrl reg */
-	u32	io_control_pci_devsel;		/* PCI_DEVSEL pad ctrl reg */
-	u32	io_control_pci_irdy;		/* PCI_IRDY pad ctrl reg */
-	u32	io_control_pci_trdy;		/* PCI_TRDY pad ctrl reg */
-	u32	io_control_pci_stop;		/* PCI_STOP pad ctrl reg */
-	u32	io_control_pci_par;		/* PCI_PAR pad ctrl reg */
-	u32	io_control_pci_perr;		/* PCI_PERR pad ctrl reg */
-	u32	io_control_pci_serr;		/* PCI_SERR pad ctrl reg */
-	u32	io_control_spdif_txclk;		/* SPDIF_TXCLK pad ctrl reg */
-	u32	io_control_spdif_tx;		/* SPDIF_TX pad ctrl reg */
-	u32	io_control_spdif_rx;		/* SPDIF_RX pad ctrl reg */
-	u32	io_control_i2c0_scl;		/* I2C0_SCL pad ctrl reg */
-	u32	io_control_i2c0_sda;		/* I2C0_SDA pad ctrl reg */
-	u32	io_control_i2c1_scl;		/* I2C1_SCL pad ctrl reg */
-	u32	io_control_i2c1_sda;		/* I2C1_SDA pad ctrl reg */
-	u32	io_control_i2c2_scl;		/* I2C2_SCL pad ctrl reg */
-	u32	io_control_i2c2_sda;		/* I2C2_SDA pad ctrl reg */
-	u32	io_control_irq0;		/* IRQ0 pad ctrl reg */
-	u32	io_control_irq1;		/* IRQ1 pad ctrl reg */
-	u32	io_control_can1_tx;		/* CAN1_TX pad ctrl reg */
-	u32	io_control_can2_tx;		/* CAN2_TX pad ctrl reg */
-	u32	io_control_j1850_tx;		/* J1850_TX pad ctrl reg */
-	u32	io_control_j1850_rx;		/* J1850_RX pad ctrl reg */
-	u32	io_control_psc_mclk_in;		/* PSC_MCLK_IN pad ctrl reg */
-	u32	io_control_psc0_0;		/* PSC0_0 pad ctrl reg */
-	u32	io_control_psc0_1;		/* PSC0_1 pad ctrl reg */
-	u32	io_control_psc0_2;		/* PSC0_2 pad ctrl reg */
-	u32	io_control_psc0_3;		/* PSC0_3 pad ctrl reg */
-	u32	io_control_psc0_4;		/* PSC0_4 pad ctrl reg */
-	u32	io_control_psc1_0;		/* PSC1_0 pad ctrl reg */
-	u32	io_control_psc1_1;		/* PSC1_1 pad ctrl reg */
-	u32	io_control_psc1_2;		/* PSC1_2 pad ctrl reg */
-	u32	io_control_psc1_3;		/* PSC1_3 pad ctrl reg */
-	u32	io_control_psc1_4;		/* PSC1_4 pad ctrl reg */
-	u32	io_control_psc2_0;		/* PSC2_0 pad ctrl reg */
-	u32	io_control_psc2_1;		/* PSC2_1 pad ctrl reg */
-	u32	io_control_psc2_2;		/* PSC2_2 pad ctrl reg */
-	u32	io_control_psc2_3;		/* PSC2_3 pad ctrl reg */
-	u32	io_control_psc2_4;		/* PSC2_4 pad ctrl reg */
-	u32	io_control_psc3_0;		/* PSC3_0 pad ctrl reg */
-	u32	io_control_psc3_1;		/* PSC3_1 pad ctrl reg */
-	u32	io_control_psc3_2;		/* PSC3_2 pad ctrl reg */
-	u32	io_control_psc3_3;		/* PSC3_3 pad ctrl reg */
-	u32	io_control_psc3_4;		/* PSC3_4 pad ctrl reg */
-	u32	io_control_psc4_0;		/* PSC4_0 pad ctrl reg */
-	u32	io_control_psc4_1;		/* PSC4_1 pad ctrl reg */
-	u32	io_control_psc4_2;		/* PSC4_2 pad ctrl reg */
-	u32	io_control_psc4_3;		/* PSC4_3 pad ctrl reg */
-	u32	io_control_psc4_4;		/* PSC4_4 pad ctrl reg */
-	u32	io_control_psc5_0;		/* PSC5_0 pad ctrl reg */
-	u32	io_control_psc5_1;		/* PSC5_1 pad ctrl reg */
-	u32	io_control_psc5_2;		/* PSC5_2 pad ctrl reg */
-	u32	io_control_psc5_3;		/* PSC5_3 pad ctrl reg */
-	u32	io_control_psc5_4;		/* PSC5_4 pad ctrl reg */
-	u32	io_control_psc6_0;		/* PSC6_0 pad ctrl reg */
-	u32	io_control_psc6_1;		/* PSC6_1 pad ctrl reg */
-	u32	io_control_psc6_2;		/* PSC6_2 pad ctrl reg */
-	u32	io_control_psc6_3;		/* PSC6_3 pad ctrl reg */
-	u32	io_control_psc6_4;		/* PSC6_4 pad ctrl reg */
-	u32	io_control_psc7_0;		/* PSC7_0 pad ctrl reg */
-	u32	io_control_psc7_1;		/* PSC7_1 pad ctrl reg */
-	u32	io_control_psc7_2;		/* PSC7_2 pad ctrl reg */
-	u32	io_control_psc7_3;		/* PSC7_3 pad ctrl reg */
-	u32	io_control_psc7_4;		/* PSC7_4 pad ctrl reg */
-	u32	io_control_psc8_0;		/* PSC8_0 pad ctrl reg */
-	u32	io_control_psc8_1;		/* PSC8_1 pad ctrl reg */
-	u32	io_control_psc8_2;		/* PSC8_2 pad ctrl reg */
-	u32	io_control_psc8_3;		/* PSC8_3 pad ctrl reg */
-	u32	io_control_psc8_4;		/* PSC8_4 pad ctrl reg */
-	u32	io_control_psc9_0;		/* PSC9_0 pad ctrl reg */
-	u32	io_control_psc9_1;		/* PSC9_1 pad ctrl reg */
-	u32	io_control_psc9_2;		/* PSC9_2 pad ctrl reg */
-	u32	io_control_psc9_3;		/* PSC9_3 pad ctrl reg */
-	u32	io_control_psc9_4;		/* PSC9_4 pad ctrl reg */
-	u32	io_control_psc10_0;		/* PSC10_0 pad ctrl reg */
-	u32	io_control_psc10_1;		/* PSC10_1 pad ctrl reg */
-	u32	io_control_psc10_2;		/* PSC10_2 pad ctrl reg */
-	u32	io_control_psc10_3;		/* PSC10_3 pad ctrl reg */
-	u32	io_control_psc10_4;		/* PSC10_4 pad ctrl reg */
-	u32	io_control_psc11_0;		/* PSC11_0 pad ctrl reg */
-	u32	io_control_psc11_1;		/* PSC11_1 pad ctrl reg */
-	u32	io_control_psc11_2;		/* PSC11_2 pad ctrl reg */
-	u32	io_control_psc11_3;		/* PSC11_3 pad ctrl reg */
-	u32	io_control_psc11_4;		/* PSC11_4 pad ctrl reg */
-	u32	io_control_ckstp_out;		/* CKSTP_OUT pad ctrl reg */
-	u32	io_control_usb_phy_drvvbus;	/* USB2_DRVVBUS pad ctrl reg */
-	u8	reserved[0x0cfc];		/* fill to 4096 bytes size */
-} ioctrl512x_t;
-
-/* IO pin fields */
-#define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
-#define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
-#define IO_PIN_PUD(v)	((v) << 4)	/* if PUE, 0=pull-down, 1=pull-up */
-#define IO_PIN_PUE(v)	((v) << 3)	/* pull up/down enable */
-#define IO_PIN_ST(v)	((v) << 2)	/* schmitt trigger */
-#define IO_PIN_DS(v)	((v))		/* slew rate */
-
-typedef struct iopin_t {
-	int p_offset;		/* offset from IOCTL_MEM_OFFSET */
-	int nr_pins;		/* number of pins to set this way */
-	int bit_or;		/* or in the value instead of overwrite */
-	u_long val;		/* value to write or or */
-}iopin_t;
-
-void iopin_initialize(iopin_t *,int);
-
-/*
- * support to adjust individual parts of the IO pin setup
- */
-
-#define IO_PIN_OVER_EACH	(1 << 0) /* for compatibility */
-#define IO_PIN_OVER_FMUX	(1 << 1)
-#define IO_PIN_OVER_HOLD	(1 << 2)
-#define IO_PIN_OVER_PULL	(1 << 3)
-#define IO_PIN_OVER_STRIG	(1 << 4)
-#define IO_PIN_OVER_DRVSTR	(1 << 5)
-
-void iopin_initialize_bits(iopin_t *, int);
-
-/*
- * IIM
- */
-typedef struct iim512x {
-	u32 stat;		/* IIM status register */
-	u32 statm;		/* IIM status IRQ mask */
-	u32 err;		/* IIM errors register */
-	u32 emask;		/* IIM error IRQ mask  */
-	u32 fctl;		/* IIM fuse control register */
-	u32 ua;			/* IIM upper address register */
-	u32 la;			/* IIM lower address register */
-	u32 sdat;		/* IIM explicit sense data */
-	u8 res0[0x08];
-	u32 prg_p;		/* IIM program protection register */
-	u8 res1[0x10];
-	u32 divide;		/* IIM divide factor register */
-	u8 res2[0x7c0];
-	u32 fbac0;		/* IIM fuse bank 0 prot (for Freescale use) */
-	u32 fb0w0[0x1f];	/* IIM fuse bank 0 data (for Freescale use) */
-	u8 res3[0x380];
-	u32 fbac1;		/* IIM fuse bank 1 protection */
-	u32 fb1w1[0x01f];	/* IIM fuse bank 1 data */
-	u8 res4[0x380];
-} iim512x_t;
-
-/*
- * LPC
- */
-typedef struct lpc512x {
-	u32	cs_cfg[8];	/* Chip Select N Configuration Registers
-				   No dedicated entry for CS Boot as == CS0 */
-	u32	cs_cr;		/* Chip Select Control Register */
-	u32	cs_sr;		/* Chip Select Status Register */
-	u32	cs_bcr;		/* Chip Select Burst Control Register */
-	u32	cs_dccr;	/* Chip Select Deadcycle Control Register */
-	u32	cs_hccr;	/* Chip Select Holdcycle Control Register */
-	u32	altr;		/* Address Latch Timing Register */
-	u8	res0[0xc8];
-	u32	sclpc_psr;	/* SCLPC Packet Size Register */
-	u32	sclpc_sar;	/* SCLPC Start Address Register */
-	u32	sclpc_cr;	/* SCLPC Control Register */
-	u32	sclpc_er;	/* SCLPC Enable Register */
-	u32	sclpc_nar;	/* SCLPC NextAddress Register */
-	u32	sclpc_sr;	/* SCLPC Status Register */
-	u32	sclpc_bdr;	/* SCLPC Bytes Done Register */
-	u32	emb_scr;	/* EMB Share Counter Register */
-	u32	emb_pcr;	/* EMB Pause Control Register */
-	u8	res1[0x1c];
-	u32	lpc_fdwr;	/* LPC RX/TX FIFO Data Word Register */
-	u32	lpc_fsr;	/* LPC RX/TX FIFO Status Register */
-	u32	lpc_cr;		/* LPC RX/TX FIFO Control Register */
-	u32	lpc_ar;		/* LPC RX/TX FIFO Alarm Register */
-	u8	res2[0xb0];
-} lpc512x_t;
-
-/*
- * PATA
- */
-typedef struct pata512x {
-	/* LOCAL Registers */
-	u32 pata_time1;		/* Time register 1: PIO and tx timing parameter */
-	u32 pata_time2;		/* Time register 2: PIO timing parameter */
-	u32 pata_time3;		/* Time register 3: PIO and MDMA timing parameter */
-	u32 pata_time4;		/* Time register 4: MDMA and UDMA timing parameter */
-	u32 pata_time5;		/* Time register 5: UDMA timing parameter */
-	u32 pata_time6;		/* Time register 6: UDMA timing parameter */
-	u32 pata_fifo_data32;   /* 32bit wide dataport to/from FIFO */
-	u32 pata_fifo_data16;   /* 16bit wide dataport to/from FIFO */
-	u32 pata_fifo_fill;	/* FIFO filling in halfwords (READONLY)*/
-	u32 pata_ata_control;   /* ATA Interface control register */
-	u32 pata_irq_pending;   /* Interrupt pending register (READONLY) */
-	u32 pata_irq_enable;	/* Interrupt enable register */
-	u32 pata_irq_clear;	/* Interrupt clear register (WRITEONLY)*/
-	u32 pata_fifo_alarm;	/* fifo alarm threshold */
-	u32 res1[0x1A];
-	/* DRIVE Registers */
-	u32 pata_drive_data;	/* drive data register*/
-	u32 pata_drive_features;/* drive features register */
-	u32 pata_drive_sectcnt; /* drive sector count register */
-	u32 pata_drive_sectnum; /* drive sector number register */
-	u32 pata_drive_cyllow;  /* drive cylinder low register */
-	u32 pata_drive_cylhigh; /* drive cylinder high register */
-	u32 pata_drive_dev_head;/* drive device head register */
-	u32 pata_drive_command; /* write = drive command, read = drive status reg */
-	u32 res2[0x06];
-	u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
-	u32 res3[0x09];
-} pata512x_t;
-
-/*
- * PSC
- */
-typedef struct psc512x {
-	volatile u8	mode;		/* PSC + 0x00 */
-	volatile u8	res0[3];
-	union {				/* PSC + 0x04 */
-		volatile u16	status;
-		volatile u16	clock_select;
-	} sr_csr;
-#define psc_status	sr_csr.status
-#define psc_clock_select sr_csr.clock_select
-	volatile u16	res1;
-	volatile u8	command;	/* PSC + 0x08 */
-	volatile u8	res2[3];
-	union {				/* PSC + 0x0c */
-		volatile u8	buffer_8;
-		volatile u16	buffer_16;
-		volatile u32	buffer_32;
-	} buffer;
-#define psc_buffer_8	buffer.buffer_8
-#define psc_buffer_16	buffer.buffer_16
-#define psc_buffer_32	buffer.buffer_32
-	union {				/* PSC + 0x10 */
-		volatile u8	ipcr;
-		volatile u8	acr;
-	} ipcr_acr;
-#define psc_ipcr	ipcr_acr.ipcr
-#define psc_acr		ipcr_acr.acr
-	volatile u8	res3[3];
-	union {				/* PSC + 0x14 */
-		volatile u16	isr;
-		volatile u16	imr;
-	} isr_imr;
-#define psc_isr		isr_imr.isr
-#define psc_imr		isr_imr.imr
-	volatile u16	res4;
-	volatile u8	ctur;		/* PSC + 0x18 */
-	volatile u8	res5[3];
-	volatile u8	ctlr;		/* PSC + 0x1c */
-	volatile u8	res6[3];
-	volatile u32	ccr;		/* PSC + 0x20 */
-	volatile u8	res7[12];
-	volatile u8	ivr;		/* PSC + 0x30 */
-	volatile u8	res8[3];
-	volatile u8	ip;		/* PSC + 0x34 */
-	volatile u8	res9[3];
-	volatile u8	op1;		/* PSC + 0x38 */
-	volatile u8	res10[3];
-	volatile u8	op0;		/* PSC + 0x3c */
-	volatile u8	res11[3];
-	volatile u32	sicr;		/* PSC + 0x40 */
-	volatile u8	res12[60];
-	volatile u32	tfcmd;		/* PSC + 0x80 */
-	volatile u32	tfalarm;	/* PSC + 0x84 */
-	volatile u32	tfstat;		/* PSC + 0x88 */
-	volatile u32	tfintstat;	/* PSC + 0x8C */
-	volatile u32	tfintmask;	/* PSC + 0x90 */
-	volatile u32	tfcount;	/* PSC + 0x94 */
-	volatile u16	tfwptr;		/* PSC + 0x98 */
-	volatile u16	tfrptr;		/* PSC + 0x9A */
-	volatile u32	tfsize;		/* PSC + 0x9C */
-	volatile u8	res13[28];
-	union {				/* PSC + 0xBC */
-		volatile u8	buffer_8;
-		volatile u16	buffer_16;
-		volatile u32	buffer_32;
-	} tfdata_buffer;
-#define tfdata_8	tfdata_buffer.buffer_8
-#define tfdata_16	tfdata_buffer.buffer_16
-#define tfdata_32	tfdata_buffer.buffer_32
-
-	volatile u32	rfcmd;		/* PSC + 0xC0 */
-	volatile u32	rfalarm;	/* PSC + 0xC4 */
-	volatile u32	rfstat;		/* PSC + 0xC8 */
-	volatile u32	rfintstat;	/* PSC + 0xCC */
-	volatile u32	rfintmask;	/* PSC + 0xD0 */
-	volatile u32	rfcount;	/* PSC + 0xD4 */
-	volatile u16	rfwptr;		/* PSC + 0xD8 */
-	volatile u16	rfrptr;		/* PSC + 0xDA */
-	volatile u32	rfsize;		/* PSC + 0xDC */
-	volatile u8	res18[28];
-	union {				/* PSC + 0xFC */
-		volatile u8	buffer_8;
-		volatile u16	buffer_16;
-		volatile u32	buffer_32;
-	} rfdata_buffer;
-#define rfdata_8	rfdata_buffer.buffer_8
-#define rfdata_16	rfdata_buffer.buffer_16
-#define rfdata_32	rfdata_buffer.buffer_32
-} psc512x_t;
-
-/* PSC FIFO Command values */
-#define PSC_FIFO_RESET_SLICE		0x80
-#define PSC_FIFO_ENABLE_SLICE		0x01
-
-/* PSC FIFO Controller Command values */
-#define FIFOC_ENABLE_CLOCK_GATE		0x01
-#define FIFOC_DISABLE_CLOCK_GATE	0x00
-
-/* PSC FIFO status */
-#define PSC_FIFO_EMPTY			0x01
-
-/* PSC Command values */
-#define PSC_RX_ENABLE		0x01
-#define PSC_RX_DISABLE		0x02
-#define PSC_TX_ENABLE		0x04
-#define PSC_TX_DISABLE		0x08
-#define PSC_SEL_MODE_REG_1	0x10
-#define PSC_RST_RX		0x20
-#define PSC_RST_TX		0x30
-#define PSC_RST_ERR_STAT	0x40
-#define PSC_RST_BRK_CHG_INT	0x50
-#define PSC_START_BRK		0x60
-#define PSC_STOP_BRK		0x70
-
-/* PSC status register bits */
-#define PSC_SR_CDE		0x0080
-#define PSC_SR_TXEMP		0x0800
-#define PSC_SR_OE		0x1000
-#define PSC_SR_PE		0x2000
-#define PSC_SR_FE		0x4000
-#define PSC_SR_RB		0x8000
-
-/* PSC mode fields */
-#define PSC_MODE_5_BITS		0x00
-#define PSC_MODE_6_BITS		0x01
-#define PSC_MODE_7_BITS		0x02
-#define PSC_MODE_8_BITS		0x03
-#define PSC_MODE_PAREVEN	0x00
-#define PSC_MODE_PARODD		0x04
-#define PSC_MODE_PARFORCE	0x08
-#define PSC_MODE_PARNONE	0x10
-#define PSC_MODE_ENTIMEOUT	0x20
-#define PSC_MODE_RXRTS		0x80
-#define PSC_MODE_1_STOPBIT	0x07
-
-/*
- * FIFOC
- */
-typedef struct fifoc512x {
-	u32 fifoc_cmd;
-	u32 fifoc_int;
-	u32 fifoc_dma;
-	u32 fifoc_axe;
-	u32 fifoc_debug;
-	u8 fixme[0xEC];
-} fifoc512x_t;
-
-/*
- * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
- *
- * NOTE: individual PSC units are free to use whatever area (and size) of the
- * FIFOC internal memory, so make sure memory areas for FIFO slices used by
- * different PSCs do not overlap!
- *
- * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
- * tests indicate that it is 1024 words total.
- *
- * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice.
- */
-#define FIFOC_PSC0_TX_SIZE	0x04
-#define FIFOC_PSC0_TX_ADDR	0x0
-#define FIFOC_PSC0_RX_SIZE	0x04
-#define FIFOC_PSC0_RX_ADDR	0x10
-
-#define FIFOC_PSC1_TX_SIZE	0x04
-#define FIFOC_PSC1_TX_ADDR	0x20
-#define FIFOC_PSC1_RX_SIZE	0x04
-#define FIFOC_PSC1_RX_ADDR	0x30
-
-#define FIFOC_PSC2_TX_SIZE	0x04
-#define FIFOC_PSC2_TX_ADDR	0x40
-#define FIFOC_PSC2_RX_SIZE	0x04
-#define FIFOC_PSC2_RX_ADDR	0x50
-
-#define FIFOC_PSC3_TX_SIZE	0x04
-#define FIFOC_PSC3_TX_ADDR	0x60
-#define FIFOC_PSC3_RX_SIZE	0x04
-#define FIFOC_PSC3_RX_ADDR	0x70
-
-#define FIFOC_PSC4_TX_SIZE	0x04
-#define FIFOC_PSC4_TX_ADDR	0x80
-#define FIFOC_PSC4_RX_SIZE	0x04
-#define FIFOC_PSC4_RX_ADDR	0x90
-
-#define FIFOC_PSC5_TX_SIZE	0x04
-#define FIFOC_PSC5_TX_ADDR	0xa0
-#define FIFOC_PSC5_RX_SIZE	0x04
-#define FIFOC_PSC5_RX_ADDR	0xb0
-
-#define FIFOC_PSC6_TX_SIZE	0x04
-#define FIFOC_PSC6_TX_ADDR	0xc0
-#define FIFOC_PSC6_RX_SIZE	0x04
-#define FIFOC_PSC6_RX_ADDR	0xd0
-
-#define FIFOC_PSC7_TX_SIZE	0x04
-#define FIFOC_PSC7_TX_ADDR	0xe0
-#define FIFOC_PSC7_RX_SIZE	0x04
-#define FIFOC_PSC7_RX_ADDR	0xf0
-
-#define FIFOC_PSC8_TX_SIZE	0x04
-#define FIFOC_PSC8_TX_ADDR	0x100
-#define FIFOC_PSC8_RX_SIZE	0x04
-#define FIFOC_PSC8_RX_ADDR	0x110
-
-#define FIFOC_PSC9_TX_SIZE	0x04
-#define FIFOC_PSC9_TX_ADDR	0x120
-#define FIFOC_PSC9_RX_SIZE	0x04
-#define FIFOC_PSC9_RX_ADDR	0x130
-
-#define FIFOC_PSC10_TX_SIZE	0x04
-#define FIFOC_PSC10_TX_ADDR	0x140
-#define FIFOC_PSC10_RX_SIZE	0x04
-#define FIFOC_PSC10_RX_ADDR	0x150
-
-#define FIFOC_PSC11_TX_SIZE	0x04
-#define FIFOC_PSC11_TX_ADDR	0x160
-#define FIFOC_PSC11_RX_SIZE	0x04
-#define FIFOC_PSC11_RX_ADDR	0x170
-
-/*
- * SATA
- */
-typedef struct sata512x {
-	u8 fixme[0x2000];
-} sata512x_t;
-
-typedef struct immap {
-	sysconf512x_t		sysconf;	/* System configuration */
-	u8			res0[0x700];
-	wdt512x_t		wdt;		/* Watch Dog Timer (WDT) */
-	rtclk512x_t		rtc;		/* Real Time Clock Module */
-	gpt512x_t		gpt;		/* General Purpose Timer */
-	ipic512x_t		ipic;		/* Integrated Programmable Interrupt Controller */
-	arbiter512x_t		arbiter;	/* CSB Arbiter */
-	reset512x_t		reset;		/* Reset Module */
-	clk512x_t		clk;		/* Clock Module */
-	pmc512x_t		pmc;		/* Power Management Control Module */
-	gpio512x_t		gpio;		/* General purpose I/O module */
-	u8			res1[0x100];
-	mscan512x_t		mscan;		/* MSCAN */
-	bdlc512x_t		bdlc;		/* BDLC */
-	sdhc512x_t		sdhc;		/* SDHC */
-	spdif512x_t		spdif;		/* SPDIF */
-	i2c512x_t		i2c;		/* I2C Controllers */
-	u8			res2[0x800];
-	axe512x_t		axe;		/* AXE */
-	diu512x_t		diu;		/* Display Interface Unit */
-	cfm512x_t		cfm;		/* Clock Frequency Measurement */
-	u8			res3[0x500];
-	fec512x_t		fec;		/* Fast Ethernet Controller */
-	ulpi512x_t		ulpi;		/* USB ULPI */
-	u8			res4[0xa00];
-	utmi512x_t		utmi;		/* USB UTMI */
-	u8			res5[0x1000];
-	pcidma512x_t		pci_dma;	/* PCI DMA */
-	pciconf512x_t		pci_conf;	/* PCI Configuration */
-	u8			res6[0x80];
-	ios512x_t		ios;		/* PCI Sequencer */
-	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control and Status */
-	u8			res7[0xa00];
-	ddr512x_t		mddrc;		/* Multi-port DDR Memory Controller */
-	ioctrl512x_t		io_ctrl;	/* IO Control */
-	iim512x_t		iim;		/* IC Identification module */
-	u8			res8[0x4000];
-	lpc512x_t		lpc;		/* LocalPlus Controller */
-	pata512x_t		pata;		/* Parallel ATA */
-	u8			res9[0xd00];
-	psc512x_t		psc[12];	/* PSCs */
-	u8			res10[0x300];
-	fifoc512x_t		fifoc;		/* FIFO Controller */
-	u8			res11[0x2000];
-	dma512x_t		dma;		/* DMA */
-	u8			res12[0xa800];
-	sata512x_t		sata;		/* Serial ATA */
-	u8			res13[0xde000];
-} immap_t;
-
-/* provide interface to get PATA base address */
-static inline u32 get_pata_base (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	return (u32)(&im->pata);
-}
-#endif	/* __ASSEMBLY__ */
-
-#define CONFIG_SYS_MPC512x_USB1_OFFSET   0x4000
-#define CONFIG_SYS_MPC512x_USB1_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET)
-
-#define IIM_BASE_ADDR	(CONFIG_SYS_IMMR + offsetof(immap_t, iim))
-
-#endif /* __IMMAP_512x__ */
diff --git a/arch/powerpc/include/asm/immap_8260.h b/arch/powerpc/include/asm/immap_8260.h
deleted file mode 100644
index c7021a7095..0000000000
--- a/arch/powerpc/include/asm/immap_8260.h
+++ /dev/null
@@ -1,604 +0,0 @@
-/*
- * MPC8260 Internal Memory Map
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * The Internal Memory Map of the 8260.	 I don't know how generic
- * this will be, as I don't have any knowledge of the subsequent
- * parts at this time.	I copied this from the 8xx_immap.h.
- */
-#ifndef __IMMAP_82XX__
-#define __IMMAP_82XX__
-
-/* System configuration registers.
-*/
-typedef struct sys_conf {
-	uint	sc_siumcr;
-	uint	sc_sypcr;
-	char	res1[6];
-	ushort	sc_swsr;
-	char	res2[20];
-	uint	sc_bcr;
-	u_char	sc_ppc_acr;
-	char	res3[3];
-	uint	sc_ppc_alrh;
-	uint	sc_ppc_alrl;
-	u_char	sc_lcl_acr;
-	char	res4[3];
-	uint	sc_lcl_alrh;
-	uint	sc_lcl_alrl;
-	uint	sc_tescr1;
-	uint	sc_tescr2;
-	uint	sc_ltescr1;
-	uint	sc_ltescr2;
-	uint	sc_pdtea;
-	u_char	sc_pdtem;
-	char	res5[3];
-	uint	sc_ldtea;
-	u_char	sc_ldtem;
-	char	res6[163];
-} sysconf8260_t;
-
-
-/* Memory controller registers.
-*/
-typedef struct	mem_ctlr {
-	uint	memc_br0;
-	uint	memc_or0;
-	uint	memc_br1;
-	uint	memc_or1;
-	uint	memc_br2;
-	uint	memc_or2;
-	uint	memc_br3;
-	uint	memc_or3;
-	uint	memc_br4;
-	uint	memc_or4;
-	uint	memc_br5;
-	uint	memc_or5;
-	uint	memc_br6;
-	uint	memc_or6;
-	uint	memc_br7;
-	uint	memc_or7;
-	uint	memc_br8;
-	uint	memc_or8;
-	uint	memc_br9;
-	uint	memc_or9;
-	uint	memc_br10;
-	uint	memc_or10;
-	uint	memc_br11;
-	uint	memc_or11;
-	char	res1[8];
-	uint	memc_mar;
-	char	res2[4];
-	uint	memc_mamr;
-	uint	memc_mbmr;
-	uint	memc_mcmr;
-	char	res3[8];
-	ushort	memc_mptpr;
-	char	res4[2];
-	uint	memc_mdr;
-	char	res5[4];
-	uint	memc_psdmr;
-	uint	memc_lsdmr;
-	u_char	memc_purt;
-	char	res6[3];
-	u_char	memc_psrt;
-	char	res7[3];
-	u_char	memc_lurt;
-	char	res8[3];
-	u_char	memc_lsrt;
-	char	res9[3];
-	uint	memc_immr;
-	uint	memc_pcibr0;
-	uint	memc_pcibr1;
-	char	res10[16];
-	uint	memc_pcimsk0;
-	uint	memc_pcimsk1;
-	char	res11[52];
-} memctl8260_t;
-
-/* System Integration Timers.
-*/
-typedef struct	sys_int_timers {
-	char	res1[32];
-	ushort	sit_tmcntsc;
-	char	res2[2];
-	uint	sit_tmcnt;
-	char	res3[4];
-	uint	sit_tmcntal;
-	char	res4[16];
-	ushort	sit_piscr;
-	char	res5[2];
-	uint	sit_pitc;
-	uint	sit_pitr;
-	char	res6[94];
-	char	res7[390];
-} sit8260_t;
-
-/* PCI
- */
-typedef struct pci_config {
-	uint	pci_omisr;
-	uint	pci_ominr;
-	char	res1[8];
-	uint	pci_ifqpr;
-	uint	pci_ofqpr;
-	char	res2[8];
-	uint	pci_imr0;
-	uint	pci_imr1;
-	uint	pci_omr0;
-	uint	pci_omr1;
-	uint	pci_odr;
-	char	res3[4];
-	uint	pci_idr;
-	char	res4[20];
-	uint	pci_imisr;
-	uint	pci_imimr;
-	char	res5[24];
-	uint	pci_ifhpr;
-	char	res5_2[4];
-	uint	pci_iftpr;
-	char	res6[4];
-	uint	pci_iphpr;
-	char	res6_2[4];
-	uint	pci_iptpr;
-	char	res7[4];
-	uint	pci_ofhpr;
-	char	res7_2[4];
-	uint	pci_oftpr;
-	char	res8[4];
-	uint	pci_ophpr;
-	char	res8_2[4];
-	uint	pci_optpr;
-	char	res9[8];
-	uint	pci_mucr;
-	char	res10[8];
-	uint	pci_qbar;
-	char	res11[12];
-	uint	pci_dmamr0;
-	uint	pci_dmasr0;
-	uint	pci_dmacdar0;
-	char	res12[4];
-	uint	pci_dmasar0;
-	char	res13[4];
-	uint	pci_dmadar0;
-	char	res14[4];
-	uint	pci_dmabcr0;
-	uint	pci_dmandar0;
-	char	res15[88];
-	uint	pci_dmamr1;
-	uint	pci_dmasr1;
-	uint	pci_dmacdar1;
-	char	res16[4];
-	uint	pci_dmasar1;
-	char	res17[4];
-	uint	pci_dmadar1;
-	char	res18[4];
-	uint	pci_dmabcr1;
-	uint	pci_dmandar1;
-	char	res19[88];
-	uint	pci_dmamr2;
-	uint	pci_dmasr2;
-	uint	pci_dmacdar2;
-	char	res20[4];
-	uint	pci_dmasar2;
-	char	res21[4];
-	uint	pci_dmadar2;
-	char	res22[4];
-	uint	pci_dmabcr2;
-	uint	pci_dmandar2;
-	char	res23[88];
-	uint	pci_dmamr3;
-	uint	pci_dmasr3;
-	uint	pci_dmacdar3;
-	char	res24[4];
-	uint	pci_dmasar3;
-	char	res25[4];
-	uint	pci_dmadar3;
-	char	res26[4];
-	uint	pci_dmabcr3;
-	uint	pci_dmandar3;
-	char	res27[344];
-	uint	pci_potar0;
-	char	res28[4];
-	uint	pci_pobar0;
-	char	res29[4];
-	uint	pci_pocmr0;
-	char	res30[4];
-	uint	pci_potar1;
-	char	res31[4];
-	uint	pci_pobar1;
-	char	res32[4];
-	uint	pci_pocmr1;
-	char	res33[4];
-	uint	pci_potar2;
-	char	res34[4];
-	uint	pci_pobar2;
-	char	res35[4];
-	uint	pci_pocmr2;
-	char	res36[52];
-	uint	pci_ptcr;
-	uint	pci_gpcr;
-	uint	pci_gcr;
-	uint	pci_esr;
-	uint	pci_emr;
-	uint	pci_ecr;
-	uint	pci_eacr;
-	char	res37[4];
-	uint	pci_edcr;
-	char	res38[4];
-	uint	pci_eccr;
-	char	res39[44];
-	uint	pci_pitar1;
-	char	res40[4];
-	uint	pci_pibar1;
-	char	res41[4];
-	uint	pci_picmr1;
-	char	res42[4];
-	uint	pci_pitar0;
-	char	res43[4];
-	uint	pci_pibar0;
-	char	res44[4];
-	uint	pci_picmr0;
-	char	res45[4];
-	uint	pci_cfg_addr;
-	uint	pci_cfg_data;
-	uint	pci_int_ack;
-	char	res46[756];
-}pci8260_t;
-#define PISCR_PIRQ_MASK		((ushort)0xff00)
-#define PISCR_PS		((ushort)0x0080)
-#define PISCR_PIE		((ushort)0x0004)
-#define PISCR_PTF		((ushort)0x0002)
-#define PISCR_PTE		((ushort)0x0001)
-
-/* Interrupt Controller.
-*/
-typedef struct interrupt_controller {
-	ushort	ic_sicr;
-	char	res1[2];
-	uint	ic_sivec;
-	uint	ic_sipnrh;
-	uint	ic_sipnrl;
-	uint	ic_siprr;
-	uint	ic_scprrh;
-	uint	ic_scprrl;
-	uint	ic_simrh;
-	uint	ic_simrl;
-	uint	ic_siexr;
-	char	res2[88];
-} intctl8260_t;
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-	uint	car_sccr;
-	char	res1[4];
-	uint	car_scmr;
-	char	res2[4];
-	uint	car_rsr;
-	uint	car_rmr;
-	char	res[104];
-} car8260_t;
-
-/* Input/Output Port control/status registers.
- * Names consistent with processor manual, although they are different
- * from the original 8xx names.......
- */
-typedef struct io_port {
-	uint	iop_pdira;
-	uint	iop_ppara;
-	uint	iop_psora;
-	uint	iop_podra;
-	uint	iop_pdata;
-	char	res1[12];
-	uint	iop_pdirb;
-	uint	iop_pparb;
-	uint	iop_psorb;
-	uint	iop_podrb;
-	uint	iop_pdatb;
-	char	res2[12];
-	uint	iop_pdirc;
-	uint	iop_pparc;
-	uint	iop_psorc;
-	uint	iop_podrc;
-	uint	iop_pdatc;
-	char	res3[12];
-	uint	iop_pdird;
-	uint	iop_ppard;
-	uint	iop_psord;
-	uint	iop_podrd;
-	uint	iop_pdatd;
-	char	res4[12];
-} iop8260_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-	u_char	cpmt_tgcr1;
-	char	res1[3];
-	u_char	cpmt_tgcr2;
-	char	res2[11];
-	ushort	cpmt_tmr1;
-	ushort	cpmt_tmr2;
-	ushort	cpmt_trr1;
-	ushort	cpmt_trr2;
-	ushort	cpmt_tcr1;
-	ushort	cpmt_tcr2;
-	ushort	cpmt_tcn1;
-	ushort	cpmt_tcn2;
-	ushort	cpmt_tmr3;
-	ushort	cpmt_tmr4;
-	ushort	cpmt_trr3;
-	ushort	cpmt_trr4;
-	ushort	cpmt_tcr3;
-	ushort	cpmt_tcr4;
-	ushort	cpmt_tcn3;
-	ushort	cpmt_tcn4;
-	ushort	cpmt_ter1;
-	ushort	cpmt_ter2;
-	ushort	cpmt_ter3;
-	ushort	cpmt_ter4;
-	char	res3[584];
-} cpmtimer8260_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-	char	res0[24];
-	u_char	sdma_sdsr;
-	char	res1[3];
-	u_char	sdma_sdmr;
-	char	res2[3];
-	u_char	sdma_idsr1;
-	char	res3[3];
-	u_char	sdma_idmr1;
-	char	res4[3];
-	u_char	sdma_idsr2;
-	char	res5[3];
-	u_char	sdma_idmr2;
-	char	res6[3];
-	u_char	sdma_idsr3;
-	char	res7[3];
-	u_char	sdma_idmr3;
-	char	res8[3];
-	u_char	sdma_idsr4;
-	char	res9[3];
-	u_char	sdma_idmr4;
-	char	res10[707];
-} sdma8260_t;
-
-/* Fast controllers
-*/
-typedef struct fcc {
-	uint	fcc_gfmr;
-	uint	fcc_fpsmr;
-	ushort	fcc_ftodr;
-	char	res1[2];
-	ushort	fcc_fdsr;
-	char	res2[2];
-	ushort	fcc_fcce;
-	char	res3[2];
-	ushort	fcc_fccm;
-	char	res4[2];
-	u_char	fcc_fccs;
-	char	res5[3];
-	u_char	fcc_ftirr_phy[4];
-} fcc_t;
-
-/* Fast controllers continued
- */
-typedef struct fcc_c {
-	uint	fcc_firper;
-	uint	fcc_firer;
-	uint	fcc_firsr_hi;
-	uint	fcc_firsr_lo;
-	u_char	fcc_gfemr;
-	char	res1[15];
-} fcc_c_t;
-
-/* TC Layer
- */
-typedef struct tclayer {
-	ushort	tc_tcmode;
-	ushort	tc_cdsmr;
-	ushort	tc_tcer;
-	ushort	tc_rcc;
-	ushort	tc_tcmr;
-	ushort	tc_fcc;
-	ushort	tc_ccc;
-	ushort	tc_icc;
-	ushort	tc_tcc;
-	ushort	tc_ecc;
-	char	res1[12];
-} tclayer_t;
-
-/* I2C
-*/
-typedef struct i2c {
-	u_char	i2c_i2mod;
-	char	res1[3];
-	u_char	i2c_i2add;
-	char	res2[3];
-	u_char	i2c_i2brg;
-	char	res3[3];
-	u_char	i2c_i2com;
-	char	res4[3];
-	u_char	i2c_i2cer;
-	char	res5[3];
-	u_char	i2c_i2cmr;
-	char	res6[331];
-} i2c8260_t;
-
-typedef struct scc {		/* Serial communication channels */
-	uint	scc_gsmrl;
-	uint	scc_gsmrh;
-	ushort	scc_psmr;
-	char	res1[2];
-	ushort	scc_todr;
-	ushort	scc_dsr;
-	ushort	scc_scce;
-	char	res2[2];
-	ushort	scc_sccm;
-	char	res3;
-	u_char	scc_sccs;
-	char	res4[8];
-} scc_t;
-
-typedef struct smc {		/* Serial management channels */
-	char	res1[2];
-	ushort	smc_smcmr;
-	char	res2[2];
-	u_char	smc_smce;
-	char	res3[3];
-	u_char	smc_smcm;
-	char	res4[5];
-} smc_t;
-
-/* Serial Peripheral Interface.
-*/
-typedef struct im_spi {
-	ushort	spi_spmode;
-	char	res1[4];
-	u_char	spi_spie;
-	char	res2[3];
-	u_char	spi_spim;
-	char	res3[2];
-	u_char	spi_spcom;
-	char	res4[82];
-} im_spi_t;
-
-/* CPM Mux.
-*/
-typedef struct cpmux {
-	u_char	cmx_si1cr;
-	char	res1;
-	u_char	cmx_si2cr;
-	char	res2;
-	uint	cmx_fcr;
-	uint	cmx_scr;
-	u_char	cmx_smr;
-	char	res3;
-	ushort	cmx_uar;
-	char	res4[16];
-} cpmux_t;
-
-/* SIRAM control
-*/
-typedef struct siram {
-	ushort	si_amr;
-	ushort	si_bmr;
-	ushort	si_cmr;
-	ushort	si_dmr;
-	u_char	si_gmr;
-	char	res1;
-	u_char	si_cmdr;
-	char	res2;
-	u_char	si_str;
-	char	res3;
-	ushort	si_rsr;
-} siramctl_t;
-
-typedef struct mcc {
-	ushort	mcc_mcce;
-	char	res1[2];
-	ushort	mcc_mccm;
-	char	res2[2];
-	u_char	mcc_mccf;
-	char	res3[7];
-} mcc_t;
-
-typedef struct comm_proc {
-	uint	cp_cpcr;
-	uint	cp_rccr;
-	char	res1[14];
-	ushort	cp_rter;
-	char	res2[2];
-	ushort	cp_rtmr;
-	ushort	cp_rtscr;
-	char	res3[2];
-	uint	cp_rtsr;
-	char	res4[12];
-} cpm8260_t;
-
-/* ...and the whole thing wrapped up....
-*/
-typedef struct immap {
-	/* Some references are into the unique and known dpram spaces,
-	 * others are from the generic base.
-	 */
-	union {
-		struct {
-			u_char		im_dpram1[16 * 1024];
-			char		res1[16 * 1024];
-			u_char		im_dpram2[4 * 1024];
-			char		res2[8 * 1024];
-			u_char		im_dpram3[4 * 1024];
-			char		res3[16 * 1024];
-		};
-		u8	im_dprambase[64 * 1024];
-		u16	im_dprambase16[32 * 1024];
-	};
-
-	sysconf8260_t	im_siu_conf;	/* SIU Configuration */
-	memctl8260_t	im_memctl;	/* Memory Controller */
-	sit8260_t	im_sit;		/* System Integration Timers */
-	pci8260_t	im_pci;		/* PCI Configuration */
-	intctl8260_t	im_intctl;	/* Interrupt Controller */
-	car8260_t	im_clkrst;	/* Clocks and reset */
-	iop8260_t	im_ioport;	/* IO Port control/status */
-	cpmtimer8260_t	im_cpmtimer;	/* CPM timers */
-	sdma8260_t	im_sdma;	/* SDMA control/status */
-
-	fcc_t		im_fcc[3];	/* Three FCCs */
-
-	char		res4[32];
-	fcc_c_t		im_fcc_c[3];	/* Continued FCCs */
-	char		res4a[32];
-
-	tclayer_t	im_tclayer[8];	/* Eight TCLayers */
-	ushort		tc_tcgsr;
-	ushort		tc_tcger;
-
-	/* First set of baud rate generators.
-	*/
-	char		res4b[236];
-	uint		im_brgc5;
-	uint		im_brgc6;
-	uint		im_brgc7;
-	uint		im_brgc8;
-
-	char		res5[608];
-
-	i2c8260_t	im_i2c;		/* I2C control/status */
-	cpm8260_t	im_cpm;		/* Communication processor */
-
-	/* Second set of baud rate generators.
-	*/
-	uint		im_brgc1;
-	uint		im_brgc2;
-	uint		im_brgc3;
-	uint		im_brgc4;
-
-	scc_t		im_scc[4];	/* Four SCCs */
-	smc_t		im_smc[2];	/* Couple of SMCs */
-	im_spi_t	im_spi;		/* A SPI */
-	cpmux_t		im_cpmux;	/* CPM clock route mux */
-	siramctl_t	im_siramctl1;	/* First SI RAM Control */
-	mcc_t		im_mcc1;	/* First MCC */
-	siramctl_t	im_siramctl2;	/* Second SI RAM Control */
-	mcc_t		im_mcc2;	/* Second MCC */
-
-	char		res6[1184];
-
-	ushort		im_si1txram[256];
-	char		res7[512];
-	ushort		im_si1rxram[256];
-	char		res8[512];
-	ushort		im_si2txram[256];
-	char		res9[512];
-	ushort		im_si2rxram[256];
-	char		res10[512];
-	char		res11[4096];
-} immap_t;
-
-#endif /* __IMMAP_82XX__ */
diff --git a/arch/powerpc/include/asm/iopin_8260.h b/arch/powerpc/include/asm/iopin_8260.h
deleted file mode 100644
index 617584d7c7..0000000000
--- a/arch/powerpc/include/asm/iopin_8260.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * MPC8260 I/O port pin manipulation functions
- */
-
-#ifndef _ASM_IOPIN_8260_H_
-#define _ASM_IOPIN_8260_H_
-
-#include <linux/types.h>
-#include <asm/immap_8260.h>
-
-#ifdef __KERNEL__
-
-typedef
-    struct {
-	u_char port:2;	/* port number (A=0, B=1, C=2, D=3) */
-	u_char pin:5;	/* port pin (0-31) */
-	u_char flag:1;	/* for whatever */
-    }
-iopin_t;
-
-#define IOPIN_PORTA	0
-#define IOPIN_PORTB	1
-#define IOPIN_PORTC	2
-#define IOPIN_PORTD	3
-
-static __inline__ void
-iopin_set_high(iopin_t *iopin)
-{
-    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
-    datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_low(iopin_t *iopin)
-{
-    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
-    datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_high(iopin_t *iopin)
-{
-    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
-    return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_low(iopin_t *iopin)
-{
-    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
-    return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-static __inline__ void
-iopin_set_out(iopin_t *iopin)
-{
-    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
-    dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_in(iopin_t *iopin)
-{
-    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
-    dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_out(iopin_t *iopin)
-{
-    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
-    return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_in(iopin_t *iopin)
-{
-    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
-    return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-static __inline__ void
-iopin_set_odr(iopin_t *iopin)
-{
-    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
-    odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_act(iopin_t *iopin)
-{
-    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
-    odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_odr(iopin_t *iopin)
-{
-    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
-    return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_act(iopin_t *iopin)
-{
-    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
-    return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-static __inline__ void
-iopin_set_ded(iopin_t *iopin)
-{
-    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
-    parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_gen(iopin_t *iopin)
-{
-    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
-    parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_ded(iopin_t *iopin)
-{
-    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
-    return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_gen(iopin_t *iopin)
-{
-    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
-    return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-static __inline__ void
-iopin_set_opt2(iopin_t *iopin)
-{
-    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
-    sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_opt1(iopin_t *iopin)
-{
-    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
-    sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_opt2(iopin_t *iopin)
-{
-    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
-    return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_opt1(iopin_t *iopin)
-{
-    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
-    return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IOPIN_8260_H_ */
diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h
deleted file mode 100644
index 8db0fa2a1c..0000000000
--- a/arch/powerpc/include/asm/iopin_8xx.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * MPC8xx I/O port pin manipulation functions
- * Roughly based on iopin_8260.h
- */
-
-#ifndef _ASM_IOPIN_8XX_H_
-#define _ASM_IOPIN_8XX_H_
-
-#include <linux/types.h>
-#include <asm/8xx_immap.h>
-
-#ifdef __KERNEL__
-
-typedef struct {
-	u_char port:2;	/* port number (A=0, B=1, C=2, D=3) */
-	u_char pin:5;	/* port pin (0-31) */
-	u_char flag:1;	/* for whatever */
-} iopin_t;
-
-#define IOPIN_PORTA	0
-#define IOPIN_PORTB	1
-#define IOPIN_PORTC	2
-#define IOPIN_PORTD	3
-
-static __inline__ void
-iopin_set_high(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
-		*datp |= (1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
-		*datp |= (1 << (31 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
-		*datp |= (1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
-		*datp |= (1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ void
-iopin_set_low(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
-		*datp &= ~(1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
-		*datp &= ~(1 << (31 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
-		*datp &= ~(1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
-		*datp &= ~(1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ uint
-iopin_is_high(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
-		return (*datp >> (15 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
-		return (*datp >> (31 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
-		return (*datp >> (15 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
-		return (*datp >> (15 - iopin->pin)) & 1;
-	}
-	return 0;
-}
-
-static __inline__ uint
-iopin_is_low(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
-		return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
-		return ((*datp >> (31 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
-		return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
-		return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
-	}
-	return 0;
-}
-
-static __inline__ void
-iopin_set_out(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
-		*dirp |= (1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
-		*dirp |= (1 << (31 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
-		*dirp |= (1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
-		*dirp |= (1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ void
-iopin_set_in(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
-		*dirp &= ~(1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
-		*dirp &= ~(1 << (31 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
-		*dirp &= ~(1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
-		*dirp &= ~(1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ uint
-iopin_is_out(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
-		return (*dirp >> (15 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
-		return (*dirp >> (31 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
-		return (*dirp >> (15 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
-		return (*dirp >> (15 - iopin->pin)) & 1;
-	}
-	return 0;
-}
-
-static __inline__ uint
-iopin_is_in(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
-		return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
-		return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
-		return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
-		return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
-	}
-	return 0;
-}
-
-static __inline__ void
-iopin_set_odr(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
-		*odrp |= (1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
-		*odrp |= (1 << (31 - iopin->pin));
-	}
-}
-
-static __inline__ void
-iopin_set_act(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
-		*odrp &= ~(1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
-		*odrp &= ~(1 << (31 - iopin->pin));
-	}
-}
-
-static __inline__ uint
-iopin_is_odr(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
-		return (*odrp >> (15 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
-		return (*odrp >> (31 - iopin->pin)) & 1;
-	}
-	return 0;
-}
-
-static __inline__ uint
-iopin_is_act(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
-		return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
-		return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1;
-	}
-	return 0;
-}
-
-static __inline__ void
-iopin_set_ded(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
-		*parp |= (1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
-		*parp |= (1 << (31 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
-		*parp |= (1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
-		*parp |= (1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ void
-iopin_set_gen(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
-		*parp &= ~(1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
-		*parp &= ~(1 << (31 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
-		*parp &= ~(1 << (15 - iopin->pin));
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
-		*parp &= ~(1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ uint
-iopin_is_ded(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
-		return (*parp >> (15 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
-		return (*parp >> (31 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
-		return (*parp >> (15 - iopin->pin)) & 1;
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
-		return (*parp >> (15 - iopin->pin)) & 1;
-	}
-	return 0;
-}
-
-static __inline__ uint
-iopin_is_gen(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
-		return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
-		return ((*parp >> (31 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
-		return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
-	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
-		return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
-	}
-	return 0;
-}
-
-static __inline__ void
-iopin_set_opt2(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
-		*sorp |= (1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ void
-iopin_set_opt1(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
-		*sorp &= ~(1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ uint
-iopin_is_opt2(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
-		return (*sorp >> (15 - iopin->pin)) & 1;
-	}
-	return 0;
-}
-
-static __inline__ uint
-iopin_is_opt1(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
-		return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1;
-	}
-	return 0;
-}
-
-static __inline__ void
-iopin_set_falledge(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
-		*intp |= (1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ void
-iopin_set_anyedge(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
-		*intp &= ~(1 << (15 - iopin->pin));
-	}
-}
-
-static __inline__ uint
-iopin_is_falledge(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
-		return (*intp >> (15 - iopin->pin)) & 1;
-	}
-	return 0;
-}
-
-static __inline__ uint
-iopin_is_anyedge(iopin_t *iopin)
-{
-	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
-		return ((*intp >> (15 - iopin->pin)) & 1) ^ 1;
-	}
-	return 0;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IOPIN_8XX_H_ */
diff --git a/arch/powerpc/include/asm/m8260_pci.h b/arch/powerpc/include/asm/m8260_pci.h
deleted file mode 100644
index 6daca4f99b..0000000000
--- a/arch/powerpc/include/asm/m8260_pci.h
+++ /dev/null
@@ -1,165 +0,0 @@
-#ifndef _PPC_KERNEL_M8260_PCI_H
-#define _PPC_KERNEL_M8260_PCI_H
-
-#define M8265_PCIBR0	0x101ac
-#define M8265_PCIBR1	0x101b0
-#define M8265_PCIMSK0	0x101c4
-#define M8265_PCIMSK1	0x101c8
-
-/* Bit definitions for PCIBR registers */
-
-#define PCIBR_ENABLE        0x00000001
-
-/* Bit definitions for PCIMSK registers */
-
-#define PCIMSK_32KB         0xFFFF8000  /* Size of window, smallest */
-#define PCIMSK_64KB         0xFFFF0000
-#define PCIMSK_128KB        0xFFFE0000
-#define PCIMSK_256KB        0xFFFC0000
-#define PCIMSK_512KB        0xFFF80000
-#define PCIMSK_1MB          0xFFF00000
-#define PCIMSK_2MB          0xFFE00000
-#define PCIMSK_4MB          0xFFC00000
-#define PCIMSK_8MB          0xFF800000
-#define PCIMSK_16MB         0xFF000000
-#define PCIMSK_32MB         0xFE000000
-#define PCIMSK_64MB         0xFC000000
-#define PCIMSK_128MB        0xF8000000
-#define PCIMSK_256MB        0xF0000000
-#define PCIMSK_512MB        0xE0000000
-#define PCIMSK_1GB          0xC0000000  /* Size of window, largest */
-
-
-#define M826X_SCCR_PCI_MODE_EN 0x100
-
-
-/*
- * Outbound ATU registers (3 sets). These registers control how 60x bus (local)
- * addresses are translated to PCI addresses when the MPC826x is a PCI bus
- * master (initiator).
- */
-
-#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
-#define POTAR_REG1          0x10818
-#define POTAR_REG2          0x10830
-
-#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
-#define POBAR_REG1          0x10820
-#define POBAR_REG2          0x10838
-
-#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
-#define POCMR_REG1          0x10828
-#define POCMR_REG2          0x10840
-
-/* Bit definitions for POMCR registers */
-
-#define POCMR_MASK_4KB      0x000FFFFF
-#define POCMR_MASK_8KB      0x000FFFFE
-#define POCMR_MASK_16KB     0x000FFFFC
-#define POCMR_MASK_32KB     0x000FFFF8
-#define POCMR_MASK_64KB     0x000FFFF0
-#define POCMR_MASK_128KB    0x000FFFE0
-#define POCMR_MASK_256KB    0x000FFFC0
-#define POCMR_MASK_512KB    0x000FFF80
-#define POCMR_MASK_1MB      0x000FFF00
-#define POCMR_MASK_2MB      0x000FFE00
-#define POCMR_MASK_4MB      0x000FFC00
-#define POCMR_MASK_8MB      0x000FF800
-#define POCMR_MASK_16MB     0x000FF000
-#define POCMR_MASK_32MB     0x000FE000
-#define POCMR_MASK_64MB     0x000FC000
-#define POCMR_MASK_128MB    0x000F8000
-#define POCMR_MASK_256MB    0x000F0000
-#define POCMR_MASK_512MB    0x000E0000
-#define POCMR_MASK_1GB      0x000C0000
-
-#define POCMR_ENABLE        0x80000000
-#define POCMR_PCI_IO        0x40000000
-#define POCMR_PREFETCH_EN   0x20000000
-
-/* Soft PCI reset */
-
-#define PCI_GCR_REG         0x10880
-
-/* Bit definitions for PCI_GCR registers */
-
-#define PCIGCR_PCI_BUS_EN   0x1
-
-/*
- * Inbound ATU registers (2 sets). These registers control how PCI addresses
- * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
- */
-
-#define PITAR_REG1          0x108D0
-#define PIBAR_REG1          0x108D8
-#define PICMR_REG1          0x108E0
-#define PITAR_REG0          0x108E8
-#define PIBAR_REG0          0x108F0
-#define PICMR_REG0          0x108F8
-
-/* Bit definitions for PCI Inbound Comparison Mask registers */
-
-#define PICMR_MASK_4KB       0x000FFFFF
-#define PICMR_MASK_8KB       0x000FFFFE
-#define PICMR_MASK_16KB      0x000FFFFC
-#define PICMR_MASK_32KB      0x000FFFF8
-#define PICMR_MASK_64KB      0x000FFFF0
-#define PICMR_MASK_128KB     0x000FFFE0
-#define PICMR_MASK_256KB     0x000FFFC0
-#define PICMR_MASK_512KB     0x000FFF80
-#define PICMR_MASK_1MB       0x000FFF00
-#define PICMR_MASK_2MB       0x000FFE00
-#define PICMR_MASK_4MB       0x000FFC00
-#define PICMR_MASK_8MB       0x000FF800
-#define PICMR_MASK_16MB      0x000FF000
-#define PICMR_MASK_32MB      0x000FE000
-#define PICMR_MASK_64MB      0x000FC000
-#define PICMR_MASK_128MB     0x000F8000
-#define PICMR_MASK_256MB     0x000F0000
-#define PICMR_MASK_512MB     0x000E0000
-#define PICMR_MASK_1GB       0x000C0000
-
-#define PICMR_ENABLE         0x80000000
-#define PICMR_NO_SNOOP_EN    0x40000000
-#define PICMR_PREFETCH_EN    0x20000000
-
-/* PCI error Registers */
-
-#define	PCI_ERROR_STATUS_REG		0x10884
-#define	PCI_ERROR_MASK_REG		0x10888
-#define	PCI_ERROR_CONTROL_REG		0x1088C
-#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
-#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
-#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
-
-/* PCI error Register bit defines */
-
-#define	PCI_ERROR_PCI_ADDR_PAR			0x00000001
-#define	PCI_ERROR_PCI_DATA_PAR_WR		0x00000002
-#define	PCI_ERROR_PCI_DATA_PAR_RD		0x00000004
-#define	PCI_ERROR_PCI_NO_RSP			0x00000008
-#define	PCI_ERROR_PCI_TAR_ABT			0x00000010
-#define	PCI_ERROR_PCI_SERR			0x00000020
-#define	PCI_ERROR_PCI_PERR_RD			0x00000040
-#define	PCI_ERROR_PCI_PERR_WR			0x00000080
-#define	PCI_ERROR_I2O_OFQO			0x00000100
-#define	PCI_ERROR_I2O_IPQO			0x00000200
-#define	PCI_ERROR_IRA				0x00000400
-#define	PCI_ERROR_NMI				0x00000800
-#define	PCI_ERROR_I2O_DBMC			0x00001000
-
-/*
- * Register pair used to generate configuration cycles on the PCI bus
- * and access the MPC826x's own PCI configuration registers.
- */
-
-#define PCI_CFG_ADDR_REG     0x10900
-#define PCI_CFG_DATA_REG     0x10904
-
-/* Bus parking decides where the bus control sits when idle */
-/* If modifying memory controllers for PCI park on the core */
-
-#define PPC_ACR_BUS_PARK_CORE 0x6
-#define PPC_ACR_BUS_PARK_PCI  0x3
-
-#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc512x.h
deleted file mode 100644
index 9167a57544..0000000000
--- a/arch/powerpc/include/asm/mpc512x.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-ppc/mpc512x.h
- *
- * Prototypes, etc. for the Freescale MPC512x embedded cpu chips
- *
- * 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASMPPC_MPC512X_H
-#define __ASMPPC_MPC512X_H
-
-/*
- * macros for manipulating CSx_START/STOP
- */
-#define CSAW_START(start)	((start) & 0xFFFF0000)
-#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
-
-/*
- * Inlines
- */
-
-/*
- * According to MPC5121e RM, configuring local access windows should
- * be followed by a dummy read of the config register that was
- * modified last and an isync.
- */
-static inline void sync_law(volatile void *addr)
-{
-	in_be32(addr);
-	__asm__ __volatile__ ("isync");
-}
-
-/*
- * Prototypes
- */
-extern long int fixed_sdram(ddr512x_config_t *mddrc_config,
-				u32 *dram_init_seq, int seq_sz);
-extern int mpc5121_diu_init(void);
-extern void ide_set_reset(int idereset);
-
-#endif /* __ASMPPC_MPC512X_H */
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
new file mode 100644
index 0000000000..4d9af6c37c
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc.h
@@ -0,0 +1,107 @@
+/*
+ * Ugly header containing required header files. This could  be adjusted
+ * so that including asm/arch/hardware includes the correct file.
+ *
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_PPC_H
+#define __ASM_PPC_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_MPC86xx
+#include <mpc86xx.h>
+#include <asm/immap_86xx.h>
+#endif
+#ifdef CONFIG_MPC85xx
+#include <mpc85xx.h>
+#include <asm/immap_85xx.h>
+#endif
+#ifdef CONFIG_MPC83xx
+#include <mpc83xx.h>
+#include <asm/immap_83xx.h>
+#endif
+#ifdef	CONFIG_4xx
+#include <asm/ppc4xx.h>
+#endif
+#ifdef CONFIG_SOC_DA8XX
+#include <asm/arch/hardware.h>
+#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#endif
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
+
+uint get_pvr(void);
+uint get_svr(void);
+uint rd_ic_cst(void);
+void wr_ic_cst(uint);
+void wr_ic_adr(uint);
+uint rd_dc_cst(void);
+void wr_dc_cst(uint);
+void wr_dc_adr(uint);
+
+#if defined(CONFIG_4xx)	|| \
+	defined(CONFIG_MPC85xx)	|| \
+	defined(CONFIG_MPC86xx)	|| \
+	defined(CONFIG_MPC83xx)
+unsigned char	in8(unsigned int);
+void		out8(unsigned int, unsigned char);
+unsigned short	in16(unsigned int);
+unsigned short	in16r(unsigned int);
+void		out16(unsigned int, unsigned short value);
+void		out16r(unsigned int, unsigned short value);
+unsigned long	in32(unsigned int);
+unsigned long	in32r(unsigned int);
+void		out32(unsigned int, unsigned long value);
+void		out32r(unsigned int, unsigned long value);
+void		ppcDcbf(unsigned long value);
+void		ppcDcbi(unsigned long value);
+void		ppcSync(void);
+void		ppcDcbz(unsigned long value);
+#endif
+#if defined(CONFIG_MPC83xx)
+void		ppcDWload(unsigned int *addr, unsigned int *ret);
+void		ppcDWstore(unsigned int *addr, unsigned int *value);
+void disable_addr_trans(void);
+void enable_addr_trans(void);
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+#endif
+
+#if defined(CONFIG_MPC85xx)
+typedef MPC85xx_SYS_INFO sys_info_t;
+void get_sys_info(sys_info_t *);
+void ft_fixup_cpu(void *, u64);
+void ft_fixup_num_cores(void *);
+#endif
+#if defined(CONFIG_MPC86xx)
+ulong get_bus_freq(ulong);
+typedef MPC86xx_SYS_INFO sys_info_t;
+void   get_sys_info(sys_info_t *);
+static inline ulong get_ddr_freq(ulong dummy)
+{
+	return get_bus_freq(dummy);
+}
+#else
+ulong get_ddr_freq(ulong);
+#endif
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef CONFIG_PPC
+/*
+ * Has to be included outside of the #ifndef __ASSEMBLY__ section.
+ * Otherwise might lead to compilation errors in assembler files.
+ */
+#include <asm/cache.h>
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h
index b8b0ff9f25..45ff5dbacd 100644
--- a/arch/powerpc/include/asm/ppc4xx.h
+++ b/arch/powerpc/include/asm/ppc4xx.h
@@ -289,6 +289,13 @@ static inline void set_mcsr(u32 val)
 
 int ppc4xx_pci_sync_clock_config(u32 async);
 
+unsigned long get_OPB_freq(void);
+unsigned long get_PCI_freq(void);
+
+typedef PPC4xx_SYS_INFO sys_info_t;
+int ppc440spe_revB(void);
+void get_sys_info(sys_info_t *);
+
 #endif	/* __ASSEMBLY__ */
 
 /* for multi-cpu support */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fd38da9fe5..6549a0936f 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1361,15 +1361,9 @@ int prt_8260_clks(void);
 #endif /* ndef ASSEMBLY*/
 
 #ifdef CONFIG_MACH_SPECIFIC
-#if defined(CONFIG_8xx)
-#define _machine _MACH_8xx
-#define have_of 0
-#elif defined(CONFIG_WALNUT)
+#if defined(CONFIG_WALNUT)
 #define _machine _MACH_walnut
 #define have_of 0
-#elif defined(CONFIG_MPC8260)
-#define _machine _MACH_8260
-#define have_of 0
 #else
 #error "Machine not defined correctly"
 #endif
diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h
deleted file mode 100644
index 1ae1b17e2d..0000000000
--- a/arch/powerpc/include/asm/status_led.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * asm/status_led.h
- *
- * MPC8xx/MPC8260/MPC5xx based status led support functions
- */
-
-#ifndef __ASM_STATUS_LED_H__
-#define __ASM_STATUS_LED_H__
-
-/* if not overridden */
-#ifndef CONFIG_LED_STATUS_BOARD_SPECIFIC
-# if defined(CONFIG_8xx)
-#  include <mpc8xx.h>
-# elif defined(CONFIG_MPC8260)
-#  include <mpc8260.h>
-# elif defined(CONFIG_5xx)
-#  include <mpc5xx.h>
-# else
-#  error CPU specific Status LED header file missing.
-#endif
-
-/* led_id_t is unsigned long mask */
-typedef unsigned long led_id_t;
-
-static inline void __led_init (led_id_t mask, int state)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
-#ifdef STATUS_LED_PAR
-	immr->STATUS_LED_PAR &= ~mask;
-#endif
-#ifdef STATUS_LED_ODR
-	immr->STATUS_LED_ODR &= ~mask;
-#endif
-
-#if (STATUS_LED_ACTIVE == 0)
-	if (state == CONFIG_LED_STATUS_ON)
-		immr->STATUS_LED_DAT &= ~mask;
-	else
-		immr->STATUS_LED_DAT |= mask;
-#else
-	if (state == CONFIG_LED_STATUS_ON)
-		immr->STATUS_LED_DAT |= mask;
-	else
-		immr->STATUS_LED_DAT &= ~mask;
-#endif
-#ifdef STATUS_LED_DIR
-	immr->STATUS_LED_DIR |= mask;
-#endif
-}
-
-static inline void __led_toggle (led_id_t mask)
-{
-	((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask;
-}
-
-static inline void __led_set (led_id_t mask, int state)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
-#if (STATUS_LED_ACTIVE == 0)
-	if (state == CONFIG_LED_STATUS_ON)
-		immr->STATUS_LED_DAT &= ~mask;
-	else
-		immr->STATUS_LED_DAT |= mask;
-#else
-	if (state == CONFIG_LED_STATUS_ON)
-		immr->STATUS_LED_DAT |= mask;
-	else
-		immr->STATUS_LED_DAT &= ~mask;
-#endif
-
-}
-
-#endif
-
-#endif	/* __ASM_STATUS_LED_H__ */
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index 74b620294e..34e44e18c2 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -16,6 +16,7 @@
 
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
+#include <asm/ppc.h>
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_PPC