diff options
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 8 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_lbc.h | 6 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_mpc83xx_serdes.h | 36 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_512x.h | 117 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 53 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/mmu.h | 5 |
6 files changed, 160 insertions, 65 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 3216a50633..02920dbfd7 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -24,6 +24,12 @@ #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ #define DDR_BL8 8 /* burst length 8 */ +#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ +#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ +#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ +#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ +#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ + #if defined(CONFIG_FSL_DDR1) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 5723de643a..dfe8f793a3 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -125,8 +125,12 @@ #define OR_GPCM_SETA_SHIFT 3 #define OR_GPCM_TRLX 0x00000004 #define OR_GPCM_TRLX_SHIFT 2 +#define OR_GPCM_TRLX_CLEAR 0x00000000 +#define OR_GPCM_TRLX_SET 0x00000004 #define OR_GPCM_EHTR 0x00000002 #define OR_GPCM_EHTR_SHIFT 1 +#define OR_GPCM_EHTR_CLEAR 0x00000000 +#define OR_GPCM_EHTR_SET 0x00000002 #define OR_GPCM_EAD 0x00000001 #define OR_GPCM_EAD_SHIFT 0 diff --git a/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h new file mode 100644 index 0000000000..2d813f4188 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h @@ -0,0 +1,36 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_MPC83XX_SERDES_H +#define __FSL_MPC83XX_SERDES_H + +#include <config.h> + +#define FSL_SERDES_CLK_100 (0 << 28) +#define FSL_SERDES_CLK_125 (1 << 28) +#define FSL_SERDES_CLK_150 (3 << 28) +#define FSL_SERDES_PROTO_SATA 0 +#define FSL_SERDES_PROTO_PEX 1 +#define FSL_SERDES_PROTO_PEX_X2 2 +#define FSL_SERDES_PROTO_SGMII 3 +#define FSL_SERDES_VDD_1V 1 + +extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd); + +#endif /* __FSL_MPC83XX_SERDES_H */ diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index 95350fd9b8..7f9db8bae3 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -356,6 +356,11 @@ typedef struct ddr512x_config { u32 ddr_time_config2; /* Timing Configuration Register */ } ddr512x_config_t; +typedef struct sdram_conf_s { + unsigned long size; + ddr512x_config_t cfg; +} sdram_conf_t; + /* * DMA/Messaging Unit */ @@ -848,10 +853,6 @@ typedef struct ioctrl512x { u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ } ioctrl512x_t; -/* Indexes in regs array */ -/* Set for DDR */ -#define IOCTRL_MUX_DDR 0x00000036 - /* IO pin fields */ #define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ #define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ @@ -1116,66 +1117,68 @@ typedef struct fifoc512x { * * Overall size of FIFOC memory is not documented in the MPC5121e RM, but * tests indicate that it is 1024 words total. + * + * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice. */ -#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */ +#define FIFOC_PSC0_TX_SIZE 0x04 #define FIFOC_PSC0_TX_ADDR 0x0 -#define FIFOC_PSC0_RX_SIZE 0x0 -#define FIFOC_PSC0_RX_ADDR 0x0 +#define FIFOC_PSC0_RX_SIZE 0x04 +#define FIFOC_PSC0_RX_ADDR 0x10 -#define FIFOC_PSC1_TX_SIZE 0x0 -#define FIFOC_PSC1_TX_ADDR 0x0 -#define FIFOC_PSC1_RX_SIZE 0x0 -#define FIFOC_PSC1_RX_ADDR 0x0 +#define FIFOC_PSC1_TX_SIZE 0x04 +#define FIFOC_PSC1_TX_ADDR 0x20 +#define FIFOC_PSC1_RX_SIZE 0x04 +#define FIFOC_PSC1_RX_ADDR 0x30 -#define FIFOC_PSC2_TX_SIZE 0x0 -#define FIFOC_PSC2_TX_ADDR 0x0 -#define FIFOC_PSC2_RX_SIZE 0x0 -#define FIFOC_PSC2_RX_ADDR 0x0 +#define FIFOC_PSC2_TX_SIZE 0x04 +#define FIFOC_PSC2_TX_ADDR 0x40 +#define FIFOC_PSC2_RX_SIZE 0x04 +#define FIFOC_PSC2_RX_ADDR 0x50 #define FIFOC_PSC3_TX_SIZE 0x04 -#define FIFOC_PSC3_TX_ADDR 0x0 +#define FIFOC_PSC3_TX_ADDR 0x60 #define FIFOC_PSC3_RX_SIZE 0x04 -#define FIFOC_PSC3_RX_ADDR 0x10 - -#define FIFOC_PSC4_TX_SIZE 0x0 -#define FIFOC_PSC4_TX_ADDR 0x0 -#define FIFOC_PSC4_RX_SIZE 0x0 -#define FIFOC_PSC4_RX_ADDR 0x0 - -#define FIFOC_PSC5_TX_SIZE 0x0 -#define FIFOC_PSC5_TX_ADDR 0x0 -#define FIFOC_PSC5_RX_SIZE 0x0 -#define FIFOC_PSC5_RX_ADDR 0x0 - -#define FIFOC_PSC6_TX_SIZE 0x0 -#define FIFOC_PSC6_TX_ADDR 0x0 -#define FIFOC_PSC6_RX_SIZE 0x0 -#define FIFOC_PSC6_RX_ADDR 0x0 - -#define FIFOC_PSC7_TX_SIZE 0x0 -#define FIFOC_PSC7_TX_ADDR 0x0 -#define FIFOC_PSC7_RX_SIZE 0x0 -#define FIFOC_PSC7_RX_ADDR 0x0 - -#define FIFOC_PSC8_TX_SIZE 0x0 -#define FIFOC_PSC8_TX_ADDR 0x0 -#define FIFOC_PSC8_RX_SIZE 0x0 -#define FIFOC_PSC8_RX_ADDR 0x0 - -#define FIFOC_PSC9_TX_SIZE 0x0 -#define FIFOC_PSC9_TX_ADDR 0x0 -#define FIFOC_PSC9_RX_SIZE 0x0 -#define FIFOC_PSC9_RX_ADDR 0x0 - -#define FIFOC_PSC10_TX_SIZE 0x0 -#define FIFOC_PSC10_TX_ADDR 0x0 -#define FIFOC_PSC10_RX_SIZE 0x0 -#define FIFOC_PSC10_RX_ADDR 0x0 - -#define FIFOC_PSC11_TX_SIZE 0x0 -#define FIFOC_PSC11_TX_ADDR 0x0 -#define FIFOC_PSC11_RX_SIZE 0x0 -#define FIFOC_PSC11_RX_ADDR 0x0 +#define FIFOC_PSC3_RX_ADDR 0x70 + +#define FIFOC_PSC4_TX_SIZE 0x04 +#define FIFOC_PSC4_TX_ADDR 0x80 +#define FIFOC_PSC4_RX_SIZE 0x04 +#define FIFOC_PSC4_RX_ADDR 0x90 + +#define FIFOC_PSC5_TX_SIZE 0x04 +#define FIFOC_PSC5_TX_ADDR 0xa0 +#define FIFOC_PSC5_RX_SIZE 0x04 +#define FIFOC_PSC5_RX_ADDR 0xb0 + +#define FIFOC_PSC6_TX_SIZE 0x04 +#define FIFOC_PSC6_TX_ADDR 0xc0 +#define FIFOC_PSC6_RX_SIZE 0x04 +#define FIFOC_PSC6_RX_ADDR 0xd0 + +#define FIFOC_PSC7_TX_SIZE 0x04 +#define FIFOC_PSC7_TX_ADDR 0xe0 +#define FIFOC_PSC7_RX_SIZE 0x04 +#define FIFOC_PSC7_RX_ADDR 0xf0 + +#define FIFOC_PSC8_TX_SIZE 0x04 +#define FIFOC_PSC8_TX_ADDR 0x100 +#define FIFOC_PSC8_RX_SIZE 0x04 +#define FIFOC_PSC8_RX_ADDR 0x110 + +#define FIFOC_PSC9_TX_SIZE 0x04 +#define FIFOC_PSC9_TX_ADDR 0x120 +#define FIFOC_PSC9_RX_SIZE 0x04 +#define FIFOC_PSC9_RX_ADDR 0x130 + +#define FIFOC_PSC10_TX_SIZE 0x04 +#define FIFOC_PSC10_TX_ADDR 0x140 +#define FIFOC_PSC10_RX_SIZE 0x04 +#define FIFOC_PSC10_RX_ADDR 0x150 + +#define FIFOC_PSC11_TX_SIZE 0x04 +#define FIFOC_PSC11_TX_ADDR 0x160 +#define FIFOC_PSC11_RX_SIZE 0x04 +#define FIFOC_PSC11_RX_ADDR 0x170 /* * SATA diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 957ad76a79..e7954e657c 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1,7 +1,7 @@ /* * MPC85xx Internal Memory Map * - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) @@ -1647,7 +1647,7 @@ typedef struct ccsr_gur { u8 res4[12]; u32 gpindr; /* General-purpose input data */ u8 res5[12]; - u32 pmuxcr; /* Alt function signal multiplex control */ + u32 alt_pmuxcr; /* Alt function signal multiplex control */ u8 res6[12]; u32 devdisr; /* Device disable control */ #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 @@ -1672,7 +1672,23 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR_I2C2 0x00000010 #define FSL_CORENET_DEVDISR_DUART1 0x00000002 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 - u8 res7[12]; + u32 devdisr2; /* Device disable control 2 */ +#define FSL_CORENET_DEVDISR2_PME 0x80000000 +#define FSL_CORENET_DEVDISR2_SEC 0x40000000 +#define FSL_CORENET_DEVDISR2_QMBM 0x08000000 +#define FSL_CORENET_DEVDISR2_FM1 0x02000000 +#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000 +#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000 +#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000 +#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000 +#define FSL_CORENET_DEVDISR2_FM2 0x00020000 +#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000 +#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000 +#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 +#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 +#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 + u8 res7[8]; u32 powmgtcsr; /* Power management status & control */ u8 res8[12]; u32 coredisru; /* uppper portion for support of 64 cores */ @@ -1697,8 +1713,9 @@ typedef struct ccsr_gur { u8 res17[24]; u32 rcwsr[16]; /* Reset control word status */ #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 -#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000 -#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15 +#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 +#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 +#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 @@ -1750,7 +1767,17 @@ typedef struct ccsr_gur { u32 cgencrl; /* Core general control */ u8 res31[184]; u32 sriopstecr; /* SRIO prescaler timer enable control */ - u8 res32[2300]; + u8 res32[1788]; + u32 pmuxcr; /* Pin multiplexing control */ + u8 res33[60]; + u32 iovselsr; /* I/O voltage selection status */ + u8 res34[28]; + u32 ddrclkdr; /* DDR clock disable */ + u8 res35; + u32 elbcclkdr; /* eLBC clock disable */ + u8 res36[20]; + u32 sdhcpcr; /* eSDHC polarity configuration */ + u8 res37[380]; } ccsr_gur_t; typedef struct ccsr_clk { @@ -1846,8 +1873,13 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 +#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 +#else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 +#endif #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 @@ -1942,7 +1974,15 @@ typedef struct serdes_corenet { #define SRDS_RSTCTL_RST 0x80000000 #define SRDS_RSTCTL_RSTDONE 0x40000000 #define SRDS_RSTCTL_RSTERR 0x20000000 +#define SRDS_RSTCTL_SDPD 0x00000020 u32 pllcr0; /* PLL Control Register 0 */ +#define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 +#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 +#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 +#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 +#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 u32 pllcr1; /* PLL Control Register 1 */ #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 u32 res[5]; @@ -2018,6 +2058,7 @@ enum { #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */ #else #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index ce7f081005..5166507f92 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -577,11 +577,16 @@ extern int num_tlb_entries; #define SA_M 0x00000200 /* Memory coherence */ #define SA_G 0x00000100 /* Guarded */ #define SA_E 0x00000080 /* Endian */ +/* Some additional macros for combinations often used */ +#define SA_IG (SA_I | SA_G) /* Access control */ #define AC_X 0x00000024 /* Execute */ #define AC_W 0x00000012 /* Write */ #define AC_R 0x00000009 /* Read */ +/* Some additional macros for combinations often used */ +#define AC_RW (AC_R | AC_W) +#define AC_RWX (AC_R | AC_W | AC_X) /* Some handy macros */ |