diff options
Diffstat (limited to 'arch/powerpc/include')
22 files changed, 149 insertions, 110 deletions
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h index 01129ed4f0..dfaddb6f1d 100644 --- a/arch/powerpc/include/asm/8xx_immap.h +++ b/arch/powerpc/include/asm/8xx_immap.h @@ -1,4 +1,3 @@ - /* * MPC8xx Internal Memory Map * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h index 23f22df1b7..43a2bb2b3e 100644 --- a/arch/powerpc/include/asm/atomic.h +++ b/arch/powerpc/include/asm/atomic.h @@ -5,8 +5,6 @@ #ifndef _ASM_PPC_ATOMIC_H_ #define _ASM_PPC_ATOMIC_H_ -#include <linux/config.h> - #ifdef CONFIG_SMP typedef struct { volatile int counter; } atomic_t; #else diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index adaf091492..a6bcf3c3fe 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -5,7 +5,6 @@ #ifndef _PPC_BITOPS_H #define _PPC_BITOPS_H -#include <linux/config.h> #include <asm/byteorder.h> extern void set_bit(int nr, volatile void *addr); diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index 5f9c640aa2..cdc1f10872 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -4,7 +4,6 @@ #ifndef __ARCH_PPC_CACHE_H #define __ARCH_PPC_CACHE_H -#include <linux/config.h> #include <asm/processor.h> /* bytes per L1 cache line */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index bec8966fde..4cc12ee70f 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -20,6 +20,7 @@ #define CONFIG_PPC_SPINTABLE_COMPATIBLE #define FSL_DDR_VER_4_7 47 +#define FSL_DDR_VER_5_0 50 /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) @@ -132,6 +133,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -152,6 +154,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -161,6 +164,7 @@ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -177,6 +181,7 @@ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -195,6 +200,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 @@ -209,6 +215,7 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -227,6 +234,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 @@ -242,6 +250,7 @@ #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 @@ -249,6 +258,7 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -262,6 +272,7 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -279,6 +290,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -288,6 +300,7 @@ #elif defined(CONFIG_P1025) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -306,6 +319,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -325,7 +339,7 @@ #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #define CONFIG_SYS_FSL_ERRATUM_A005125 - +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -337,6 +351,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -380,6 +395,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_USB14 @@ -412,6 +428,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" @@ -459,6 +476,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -494,6 +512,7 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" @@ -518,6 +537,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 @@ -534,6 +554,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 @@ -557,6 +578,7 @@ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #ifdef CONFIG_PPC_T4240 #define CONFIG_MAX_CPUS 12 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_NUM_FM2_DTSEC 8 @@ -564,6 +586,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 3 #else #define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 7 @@ -578,9 +601,13 @@ #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM1_CLK 3 +#define CONFIG_SYS_FM2_CLK 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" @@ -593,6 +620,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -608,6 +636,8 @@ #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 @@ -617,6 +647,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 @@ -624,9 +655,11 @@ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -635,6 +668,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 #define CONFIG_NUM_DDR_CONTROLLERS 1 @@ -646,22 +680,31 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) #define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 +#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) +#define CONFIG_MAX_CPUS 2 +#endif +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CONFIG_SYS_SDHC_CLOCK 0 #define CONFIG_SYS_FSL_NUM_LAWS 16 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_PME_PLAT_CLK_DIV 2 +#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_FM_PLAT_CLK_DIV 1 +#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h index 6a4a51a9aa..4f78186d9d 100644 --- a/arch/powerpc/include/asm/cpm_8260.h +++ b/arch/powerpc/include/asm/cpm_8260.h @@ -1,4 +1,3 @@ - /* * MPC8260 Communication Processor Module. * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h index 1681ecd507..b137a71450 100644 --- a/arch/powerpc/include/asm/cpm_85xx.h +++ b/arch/powerpc/include/asm/cpm_85xx.h @@ -1,4 +1,3 @@ - /* * MPC85xx Communication Processor Module * Copyright (c) 2003,Motorola Inc. diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h index bd312ad5c5..99a72bc6e1 100644 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h @@ -45,48 +45,49 @@ typedef struct dimm_params_s { unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ - unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */ - unsigned int tFAW_ps; /* four active window delay, only for ddr3 */ + unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ + unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ /* * SDRAM clock periods * The range for these are 1000-10000 so a short should be sufficient */ - unsigned int tCKmin_X_ps; - unsigned int tCKmin_X_minus_1_ps; - unsigned int tCKmin_X_minus_2_ps; - unsigned int tCKmax_ps; + unsigned int tckmin_x_ps; + unsigned int tckmin_x_minus_1_ps; + unsigned int tckmin_x_minus_2_ps; + unsigned int tckmax_ps; /* SPD-defined CAS latencies */ - unsigned int caslat_X; - unsigned int caslat_X_minus_1; - unsigned int caslat_X_minus_2; + unsigned int caslat_x; + unsigned int caslat_x_minus_1; + unsigned int caslat_x_minus_2; unsigned int caslat_lowest_derated; /* Derated CAS latency */ /* basic timing parameters */ - unsigned int tRCD_ps; - unsigned int tRP_ps; - unsigned int tRAS_ps; + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; - unsigned int tWR_ps; /* maximum = 63750 ps */ - unsigned int tWTR_ps; /* maximum = 63750 ps */ - unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns = 511750 ps */ - unsigned int tRRD_ps; /* maximum = 63750 ps */ - unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ unsigned int refresh_rate_ps; + unsigned int extended_op_srt; /* DDR3 doesn't need these as below */ - unsigned int tIS_ps; /* byte 32, spd->ca_setup */ - unsigned int tIH_ps; /* byte 33, spd->ca_hold */ - unsigned int tDS_ps; /* byte 34, spd->data_setup */ - unsigned int tDH_ps; /* byte 35, spd->data_hold */ - unsigned int tRTP_ps; /* byte 38, spd->trtp */ - unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tQHS_ps; /* byte 45, spd->tqhs */ + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ /* DDR3 RDIMM */ unsigned char rcw[16]; /* Register Control Word 0-15 */ diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index f4eec82d5d..2c3c514ba3 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -219,13 +219,13 @@ typedef struct fsl_ddr_cfg_regs_s { } fsl_ddr_cfg_regs_t; typedef struct memctl_options_partial_s { - unsigned int all_DIMMs_ECC_capable; - unsigned int all_DIMMs_tCKmax_ps; - unsigned int all_DIMMs_burst_lengths_bitmask; - unsigned int all_DIMMs_registered; - unsigned int all_DIMMs_unbuffered; + unsigned int all_dimms_ecc_capable; + unsigned int all_dimms_tckmax_ps; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; /* unsigned int lowest_common_SPD_caslat; */ - unsigned int all_DIMMs_minimum_tRCD_ps; + unsigned int all_dimms_minimum_trcd_ps; } memctl_options_partial_t; #define DDR_DATA_BUS_WIDTH_64 0 @@ -261,10 +261,10 @@ typedef struct memctl_options_s { unsigned int addr_hash; /* Operational mode parameters */ - unsigned int ECC_mode; /* Use ECC? */ + unsigned int ecc_mode; /* Use ECC? */ /* Initialize ECC using memory controller? */ - unsigned int ECC_init_using_memctl; - unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */ + unsigned int ecc_init_using_memctl; + unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ /* SREN - self-refresh during sleep */ unsigned int self_refresh_in_sleep; unsigned int dynamic_power; /* DYN_PWR */ @@ -272,7 +272,7 @@ typedef struct memctl_options_s { unsigned int data_bus_width; unsigned int burst_length; /* BL4, OTF and BL8 */ /* On-The-Fly Burst Chop enable */ - unsigned int OTF_burst_chop_en; + unsigned int otf_burst_chop_en; /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; unsigned int quad_rank_present; @@ -297,11 +297,11 @@ typedef struct memctl_options_s { unsigned int wrlvl_ctl_3; unsigned int half_strength_driver_enable; - unsigned int twoT_en; - unsigned int threeT_en; + unsigned int twot_en; + unsigned int threet_en; unsigned int bstopre; - unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ - unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + unsigned int tcke_clock_pulse_width_ps; /* tCKE */ + unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ /* Rtt impedance */ unsigned int rtt_override; /* rtt_override enable */ diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h new file mode 100644 index 0000000000..3cac2d4310 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_FSL_ERRATA_H +#define _ASM_FSL_ERRATA_H + +#include <common.h> +#include <asm/processor.h> + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 +static inline bool has_erratum_a006379(void) +{ + u32 svr = get_svr(); + if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2)) + return true; + + return false; +} +#endif + +#endif diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 749411c101..5be718b162 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -18,24 +18,6 @@ /* Freescale-specific PCI config registers */ #define FSL_PCI_PBFR 0x44 -#ifdef CONFIG_SYS_FSL_PCI_VER_3_X -/* Currently only the PCIe capability is used, so hardcode the offset. - * if more capabilities need to be justified, the capability link method - * should be applied here - */ -#define FSL_PCIE_CAP_ID 0x70 -#define PCI_DCR 0x78 /* PCIe Device Control Register */ -#define PCI_DSR 0x7a /* PCIe Device Status Register */ -#define PCI_LSR 0x82 /* PCIe Link Status Register */ -#define PCI_LCR 0x80 /* PCIe Link Control Register */ -#else -#define FSL_PCIE_CAP_ID 0x4c -#define PCI_DCR 0x54 /* PCIe Device Control Register */ -#define PCI_DSR 0x56 /* PCIe Device Status Register */ -#define PCI_LSR 0x5e /* PCIe Link Status Register */ -#define PCI_LCR 0x5c /* PCIe Link Control Register */ -#endif - #define FSL_PCIE_CFG_RDY 0x4b0 #define FSL_PROG_IF_AGENT 0x1 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index c36f3c388a..4c7f0b1cae 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -7,6 +7,7 @@ #ifndef __FSL_SECURE_BOOT_H #define __FSL_SECURE_BOOT_H +#ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 #else @@ -15,3 +16,4 @@ #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 #endif +#endif diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 1106d28058..cce892ce90 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -86,6 +86,7 @@ enum srds { int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); +const char *serdes_clock_to_string(u32 clock); #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index 01c9efff97..bed80aa933 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -279,8 +279,8 @@ typedef struct ddr512x { u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ - u32 DQS_config_offset_count; /* DQS Config Offset Count */ - u32 DQS_config_offset_time; /* DQS Config Offset Time */ + u32 dqs_config_offset_count; /* DQS Config Offset Count */ + u32 dqs_config_offset_time; /* DQS Config Offset Time */ u32 DQS_delay_status; /* DQS Delay Status */ u32 res0[0xF]; u32 prioman_config1; /* Priority Manager Configuration */ @@ -1255,9 +1255,9 @@ static inline u32 get_pata_base (void) } #endif /* __ASSEMBLY__ */ -#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000 -#define CONFIG_SYS_MPC512x_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET) +#define CONFIG_SYS_MPC512x_USB1_OFFSET 0x4000 +#define CONFIG_SYS_MPC512x_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET) #define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim)) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 57189c9136..3c86ff66fd 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -764,9 +764,11 @@ typedef struct immap { } immap_t; #ifdef CONFIG_HAS_FSL_MPH_USB -#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */ +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ +#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 #else -#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */ +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 +#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ #endif #elif defined(CONFIG_MPC8313) @@ -1031,11 +1033,15 @@ typedef struct immap { #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) -#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET -#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 +#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000 +#endif +#define CONFIG_SYS_MPC83xx_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) +#if defined(CONFIG_MPC834x) +#define CONFIG_SYS_MPC83xx_USB2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) #endif -#define CONFIG_SYS_MPC83xx_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define CONFIG_SYS_TSEC1_OFFSET 0x24000 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3a10d778f1..060e0d769b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1671,6 +1671,7 @@ typedef struct cpc_corenet { #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 +#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ @@ -2016,20 +2017,13 @@ typedef struct ccsr_clk { u8 res_004[0x0c]; u32 clkcgnhwacsr;/* clock generator n hardware accelerator */ u8 res_014[0x0c]; - } clkcsr[8]; - u8 res_100[0x700]; /* 0x100 */ - u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */ - u8 res10[0x1c]; - u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */ - u8 res11[0x1c]; - u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */ - u8 res12[0x1c]; - u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */ - u8 res13[0x1c]; - u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */ - u8 res14[0x1c]; - u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */ - u8 res15[0x35c]; + } clkcsr[12]; + u8 res_100[0x680]; /* 0x100 */ + struct { + u32 pllcngsr; + u8 res10[0x1c]; + } pllcgsr[12]; + u8 res21[0x280]; u32 pllpgsr; /* 0xc00 Platform PLL General Status */ u8 res16[0x1c]; u32 plldgsr; /* 0xc20 DDR PLL General Status */ @@ -2938,7 +2932,6 @@ struct ccsr_pman { #endif #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 -#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 @@ -2991,7 +2984,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 -#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 +#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 #ifdef CONFIG_TSECV2 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 @@ -3092,8 +3085,10 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_MPC85xx_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET) +#define CONFIG_SYS_MPC85xx_USB2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET) #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 1f12c29ba8..d8b7b974d4 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -7,7 +7,6 @@ #ifndef _PPC_IO_H #define _PPC_IO_H -#include <linux/config.h> #include <asm/byteorder.h> #ifdef CONFIG_ADDR_MAP diff --git a/arch/powerpc/include/asm/m8260_pci.h b/arch/powerpc/include/asm/m8260_pci.h index 45f01de820..6daca4f99b 100644 --- a/arch/powerpc/include/asm/m8260_pci.h +++ b/arch/powerpc/include/asm/m8260_pci.h @@ -1,4 +1,3 @@ - #ifndef _PPC_KERNEL_M8260_PCI_H #define _PPC_KERNEL_M8260_PCI_H diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index b700a3a0be..cadaeef85a 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -5,8 +5,6 @@ #ifndef _PPC_MMU_H_ #define _PPC_MMU_H_ -#include <linux/config.h> - #ifndef __ASSEMBLY__ /* Hardware Page Table Entry */ typedef struct _PTE { diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index 04fc8916eb..4d1106b124 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -1,4 +1,3 @@ - /* * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index c0fb51993e..81f9d38e79 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -7,8 +7,6 @@ */ #define current_text_addr() ({ __label__ _l; _l: &&_l;}) -#include <linux/config.h> - #include <asm/ptrace.h> #include <asm/types.h> diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h index cf09edf156..2d56de61d1 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h @@ -17,8 +17,6 @@ * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. */ -#include <linux/config.h> - #ifndef __ASSEMBLY__ #ifdef CONFIG_PPC64BRIDGE #define PPC_REG unsigned long /*long*/ |