diff options
Diffstat (limited to 'arch/powerpc/lib/ppccache.S')
| -rw-r--r-- | arch/powerpc/lib/ppccache.S | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index 349a1c1985..b96dbc60e0 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -9,6 +9,9 @@ #include <config.h> #include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> /*------------------------------------------------------------------------------- */ /* Function: ppcDcbf */ @@ -54,3 +57,48 @@ ppcDcbz: ppcSync: sync blr + +/* + * Write any modified data cache blocks out to memory and invalidate them. + * Does not invalidate the corresponding instruction cache blocks. + * + * flush_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + +1: dcbf 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Like above, but invalidate the D-cache. This is used by the 8xx + * to invalidate the cache so the PPC core doesn't get stale data + * from the CPM (no cache snooping here :-). + * + * invalidate_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(invalidate_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + + sync +1: dcbi 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbi's to get to ram */ + blr + |