diff options
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 5 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_pci.h | 4 |
3 files changed, 12 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index b0f34b6f15..615d7e13a9 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -831,6 +831,7 @@ config ARCH_T2080 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007186 select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 @@ -893,6 +894,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007186 select SYS_FSL_ERRATUM_A007798 + select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 @@ -1081,6 +1083,9 @@ config SYS_FSL_ERRATUM_A007186 config SYS_FSL_ERRATUM_A007212 bool +config SYS_FSL_ERRATUM_A007815 + bool + config SYS_FSL_ERRATUM_A007798 bool diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 822ae7251b..b8be59659e 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -333,6 +333,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A007907 puts("Work-around for Erratum A007907 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + puts("Work-around for Erratum A007815 enabled\n"); +#endif + return 0; } diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 8bee8ca998..cad341e72c 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -79,7 +79,9 @@ typedef struct ccsr_pci { u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ u32 pm_command; /* 0x02c - PCIE PM Command register */ - char res4[3016]; /* (- #xbf8 #x30)3016 */ + char res3[2188]; /* (0x8bc - 0x30 = 2188) */ + u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */ + char res4[824]; /* (0xbf8 - 0x8c0 = 824) */ u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ |