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-rw-r--r--arch/powerpc/cpu/mpc5xx/cpu_init.c2
-rw-r--r--arch/powerpc/cpu/mpc5xxx/spl_boot.c4
-rw-r--r--arch/powerpc/cpu/mpc8260/cpu.c9
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu.c5
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu_init.c1
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c14
-rw-r--r--arch/powerpc/cpu/mpc8xx/speed.c93
-rw-r--r--arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c24
-rw-r--r--arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c14
-rw-r--r--arch/powerpc/cpu/ppc4xx/sdram.c18
-rw-r--r--arch/powerpc/cpu/ppc4xx/spl_boot.c2
-rw-r--r--arch/powerpc/include/asm/processor.h4
-rw-r--r--arch/powerpc/lib/Makefile1
-rw-r--r--arch/powerpc/lib/setup.c32
-rw-r--r--arch/powerpc/lib/time.c2
15 files changed, 150 insertions, 75 deletions
diff --git a/arch/powerpc/cpu/mpc5xx/cpu_init.c b/arch/powerpc/cpu/mpc5xx/cpu_init.c
index 0f62c13f86..5bae39f8c0 100644
--- a/arch/powerpc/cpu/mpc5xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc5xx/cpu_init.c
@@ -43,7 +43,7 @@ void cpu_init_f (volatile immap_t * immr)
immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR;
/* Time base and decrementer will be enables (TBE) */
- /* in init_timebase() in time.c called from board_init_f(). */
+ /* in timer_init() in time.c called from board_init_f(). */
/* Initialize the PIT. Unlock PISCRK */
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
diff --git a/arch/powerpc/cpu/mpc5xxx/spl_boot.c b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
index e182dfbd45..2d7f6c4a93 100644
--- a/arch/powerpc/cpu/mpc5xxx/spl_boot.c
+++ b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
@@ -32,7 +32,7 @@ void board_init_f(ulong bootflag)
/*
* On MPC5200, the initial RAM (and gd) is located in the internal
* SRAM. So we can actually call the preloader console init code
- * before calling initdram(). This makes serial output (printf)
+ * before calling dram_init(). This makes serial output (printf)
* available very early, even before SDRAM init, which has been
* an U-Boot priciple from day 1.
*/
@@ -62,7 +62,7 @@ void board_init_f(ulong bootflag)
* First we need to initialize the SDRAM, so that the real
* U-Boot or the OS (Linux) can be loaded
*/
- initdram(0);
+ dram_init();
/* Clear bss */
memset(__bss_start, '\0', __bss_end - __bss_start);
diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c
index 9f2be3cb22..58d1c0261c 100644
--- a/arch/powerpc/cpu/mpc8260/cpu.c
+++ b/arch/powerpc/cpu/mpc8260/cpu.c
@@ -50,7 +50,14 @@ int checkcpu (void)
uint pvr = get_pvr ();
uint immr, rev, m, k;
char buf[32];
-
+ int ret;
+
+ ret = prt_8260_rsr();
+ if (ret)
+ return ret;
+ ret = prt_8260_clks();
+ if (ret)
+ return ret;
puts ("CPU: ");
switch (pvr) {
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index c87f0fdd29..cb82621ec4 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -33,6 +33,7 @@ int checkcpu(void)
u32 pvr = get_pvr();
u32 spridr;
char buf[32];
+ int ret;
int i;
const struct cpu_type {
@@ -61,6 +62,10 @@ int checkcpu(void)
immr = (immap_t *)CONFIG_SYS_IMMR;
+ ret = prt_83xx_rsr();
+ if (ret)
+ return ret;
+
puts("CPU: ");
switch (pvr & 0xffff0000) {
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 3a0916bdbf..2a9db0c51b 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -8,6 +8,7 @@
#include <mpc83xx.h>
#include <ioports.h>
#include <asm/io.h>
+#include <asm/processor.h>
#ifdef CONFIG_USB_EHCI_FSL
#include <usb/ehci-ci.h>
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index cc30fa6e17..e3ef4ae816 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -401,17 +401,19 @@ void mpc85xx_reginfo(void)
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
!defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
defined(CONFIG_ARCH_QEMU_E500)
- return fsl_ddr_sdram_size();
+ gd->ram_size = fsl_ddr_sdram_size();
#else
- return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
+
+ return 0;
}
#else /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
phys_size_t dram_size = 0;
@@ -460,7 +462,9 @@ phys_size_t initdram(int board_type)
#endif
debug("DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
#endif
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index 42442b8c98..e2295d253f 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -237,18 +237,61 @@ int get_clocks (void)
static long init_pll_866 (long clk);
+/* Adjust sdram refresh rate to actual CPU clock.
+ */
+static int sdram_adjust_866(void)
+{
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ long mamr;
+
+ mamr = immr->im_memctl.memc_mamr;
+ mamr &= ~MAMR_PTA_MSK;
+ mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ immr->im_memctl.memc_mamr = mamr;
+
+ return 0;
+}
+
+/*
+ * Adjust sdram refresh rate to actual CPU clock
+ * and set timebase source according to actual CPU clock
+ */
+static int adjust_sdram_tbs_8xx(void)
+{
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) && \
+ !defined(CONFIG_TQM885D)
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ long mamr;
+ long sccr;
+
+ mamr = immr->im_memctl.memc_mamr;
+ mamr &= ~MAMR_PTA_MSK;
+ mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ immr->im_memctl.memc_mamr = mamr;
+
+ if (gd->cpu_clk < 67000000) {
+ sccr = immr->im_clkrst.car_sccr;
+ sccr |= SCCR_TBS;
+ immr->im_clkrst.car_sccr = sccr;
+ }
+#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
+
+ return 0;
+}
+
/* This function sets up PLL (init_pll_866() is called) and
* fills gd->cpu_clk and gd->bus_clk according to the environment
* variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
* contains invalid value).
* This functions requires an MPC866 or newer series CPU.
*/
-int get_clocks_866 (void)
+int get_clocks(void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
char tmp[64];
long cpuclk = 0;
long sccr_reg;
+ int ret;
if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0)
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
@@ -278,22 +321,11 @@ int get_clocks_866 (void)
}
immr->im_clkrst.car_sccr = sccr_reg;
- return (0);
-}
-
-/* Adjust sdram refresh rate to actual CPU clock.
- */
-int sdram_adjust_866 (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- long mamr;
-
- mamr = immr->im_memctl.memc_mamr;
- mamr &= ~MAMR_PTA_MSK;
- mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
- immr->im_memctl.memc_mamr = mamr;
+ ret = sdram_adjust_866();
+ if (ret)
+ return ret;
- return (0);
+ return adjust_sdram_tbs_8xx();
}
/* Configure PLL for MPC866/859/885 CPU series
@@ -369,32 +401,3 @@ static long init_pll_866 (long clk)
}
#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
-
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
- && !defined(CONFIG_TQM885D)
-/*
- * Adjust sdram refresh rate to actual CPU clock
- * and set timebase source according to actual CPU clock
- */
-int adjust_sdram_tbs_8xx (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- long mamr;
- long sccr;
-
- mamr = immr->im_memctl.memc_mamr;
- mamr &= ~MAMR_PTA_MSK;
- mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
- immr->im_memctl.memc_mamr = mamr;
-
- if (gd->cpu_clk < 67000000) {
- sccr = immr->im_clkrst.car_sccr;
- sccr |= SCCR_TBS;
- immr->im_clkrst.car_sccr = sccr;
- }
-
- return (0);
-}
-#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
-
-/* ------------------------------------------------------------------------- */
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 7202c3fc46..ffc62a5849 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -33,6 +33,8 @@
#include "ecc.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
do { \
u32 data; \
@@ -401,20 +403,20 @@ static unsigned char spd_read(uchar chip, uint addr)
}
/*-----------------------------------------------------------------------------+
- * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
+ * dram_init. Initializes the 440SP Memory Queue and DDR SDRAM controller.
* Note: This routine runs from flash with a stack set up in the chip's
* sram space. It is important that the routine does not require .sbss, .bss or
* .data sections. It also cannot call routines that require these sections.
*-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
- * Function: initdram
+ * Function: dram_init
* Description: Configures SDRAM memory banks for DDR operation.
* Auto Memory Configuration option reads the DDR SDRAM EEPROMs
* via the IIC bus and then configures the DDR SDRAM memory
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
@@ -429,7 +431,9 @@ phys_size_t initdram(int board_type)
* Reduce RAM size to avoid overwriting memory used by
* current stack? Not sure what is happening.
*/
- return sdram_memsize() / 2;
+ gd->ram_size = sdram_memsize() / 2;
+
+ return 0;
}
num_dimm_banks = sizeof(iic0_dimm_addr);
@@ -650,7 +654,9 @@ phys_size_t initdram(int board_type)
*/
set_mcsr(get_mcsr());
- return sdram_memsize();
+ gd->ram_size = sdram_memsize();
+
+ return 0;
}
static void get_spd_info(unsigned long *dimm_populated,
@@ -2849,13 +2855,13 @@ static void test(void)
#else /* CONFIG_SPD_EEPROM */
/*-----------------------------------------------------------------------------
- * Function: initdram
+ * Function: dram_init
* Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
* The configuration is performed using static, compile-
* time parameters.
* Configures the PPC405EX(r) and PPC460EX/GT
*---------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
unsigned long val;
@@ -3011,7 +3017,9 @@ phys_size_t initdram(int board_type)
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
- return (CONFIG_SYS_MBYTES_SDRAM << 20);
+ gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+ return 0;
}
#endif /* CONFIG_SPD_EEPROM */
diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
index 455136c68c..c477853fb8 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
@@ -30,6 +30,8 @@
#include <asm/mmu.h>
#include <asm/cache.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
@@ -985,20 +987,20 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
}
/*-----------------------------------------------------------------------------+
- * initdram. Initializes the 440EPx/GPx DDR SDRAM controller.
+ * dram_init. Initializes the 440EPx/GPx DDR SDRAM controller.
* Note: This routine runs from flash with a stack set up in the chip's
* sram space. It is important that the routine does not require .sbss, .bss or
* .data sections. It also cannot call routines that require these sections.
*-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
- * Function: initdram
+ * Function: dram_init
* Description: Configures SDRAM memory banks for DDR operation.
* Auto Memory Configuration option reads the DDR SDRAM EEPROMs
* via the IIC bus and then configures the DDR SDRAM memory
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_ranks[MAXDIMMS];
@@ -1012,7 +1014,7 @@ phys_size_t initdram(int board_type)
unsigned long cas_latency = 0; /* to quiet initialization warning */
unsigned long dram_size;
- debug("\nEntering initdram()\n");
+ debug("\nEntering dram_init()\n");
/*------------------------------------------------------------------
* Stop the DDR-SDRAM controller.
@@ -1212,7 +1214,9 @@ phys_size_t initdram(int board_type)
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
void board_add_ram_info(int use_default)
diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c
index cd63456e70..c416bcebf6 100644
--- a/arch/powerpc/cpu/ppc4xx/sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/sdram.c
@@ -17,6 +17,8 @@
#include "sdram.h"
#include "ecc.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_SDRAM_BANK0
#ifndef CONFIG_440
@@ -148,7 +150,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
/*
* Autodetect onboard SDRAM on 405 platforms
*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
ulong speed;
ulong sdtr1;
@@ -226,11 +228,13 @@ phys_size_t initdram(int board_type)
/*
* OK, size detected -> all done
*/
- return size;
+ gd->ram_size = size;
+
+ return 0;
}
}
- return 0;
+ return -ENXIO;
}
#else /* CONFIG_440 */
@@ -349,7 +353,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
* so this should be extended for other future boards
* using this routine!
*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
int i;
int tr1_bank1;
@@ -440,11 +444,13 @@ phys_size_t initdram(int board_type)
/*
* OK, size detected -> all done
*/
- return size;
+ gd->ram_size = size;
+
+ return 0;
}
}
- return 0; /* nothing found ! */
+ return -ENXIO; /* nothing found ! */
}
#endif /* CONFIG_440 */
diff --git a/arch/powerpc/cpu/ppc4xx/spl_boot.c b/arch/powerpc/cpu/ppc4xx/spl_boot.c
index 318f23b646..b30f169e89 100644
--- a/arch/powerpc/cpu/ppc4xx/spl_boot.c
+++ b/arch/powerpc/cpu/ppc4xx/spl_boot.c
@@ -26,7 +26,7 @@ void board_init_f(ulong bootflag)
* First we need to initialize the SDRAM, so that the real
* U-Boot or the OS (Linux) can be loaded
*/
- initdram(0);
+ dram_init();
/* Clear bss */
memset(__bss_start, '\0', __bss_end - __bss_start);
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 81bae6f008..fd38da9fe5 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1354,6 +1354,10 @@ void ll_puts(const char *);
/* In misc.c */
void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
+int prt_83xx_rsr(void);
+int prt_8260_rsr(void);
+int prt_8260_clks(void);
+
#endif /* ndef ASSEMBLY*/
#ifdef CONFIG_MACH_SPECIFIC
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 3c97476a83..4f68613a41 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -17,6 +17,7 @@ MINIMAL=y
endif
endif
+obj-$(CONFIG_SYS_EXTBDINFO) += setup.o
ifdef MINIMAL
obj-y += cache.o time.o
obj-y += ticks.o
diff --git a/arch/powerpc/lib/setup.c b/arch/powerpc/lib/setup.c
new file mode 100644
index 0000000000..a4213359e2
--- /dev/null
+++ b/arch/powerpc/lib/setup.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int setup_board_extra(void)
+{
+ bd_t *bd = gd->bd;
+
+ strncpy((char *)bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
+ strncpy((char *)bd->bi_r_version, U_BOOT_VERSION,
+ sizeof(bd->bi_r_version));
+
+ bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
+ bd->bi_plb_busfreq = gd->bus_clk;
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ bd->bi_pci_busfreq = get_PCI_freq();
+ bd->bi_opbfreq = get_OPB_freq();
+#elif defined(CONFIG_XILINX_405)
+ bd->bi_pci_busfreq = get_PCI_freq();
+#endif
+
+ return 0;
+}
diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c
index 62b6c72f4e..de5f0be66d 100644
--- a/arch/powerpc/lib/time.c
+++ b/arch/powerpc/lib/time.c
@@ -60,7 +60,7 @@ unsigned long ticks2usec(unsigned long ticks)
#endif
/* ------------------------------------------------------------------------- */
-int init_timebase (void)
+int timer_init(void)
{
unsigned long temp;
generated by cgit (git 2.34.1) at 2025-01-13 19:09:23 +0000