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-rw-r--r--arch/powerpc/Kconfig7
-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig6
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig653
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile4
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c22
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c18
-rw-r--r--arch/powerpc/cpu/mpc86xx/Kconfig4
-rw-r--r--arch/powerpc/include/asm/config.h11
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h331
-rw-r--r--arch/powerpc/include/asm/config_mpc86xx.h2
-rw-r--r--arch/powerpc/include/asm/fsl_secure_boot.h7
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h6
13 files changed, 688 insertions, 385 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 18451d3e45..0033c35261 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -23,13 +23,20 @@ config MPC8260
config MPC83xx
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config MPC85xx
bool "MPC85xx"
select CREATE_ARCH_SYMLINK
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
config MPC86xx
bool "MPC86xx"
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
config 8xx
bool "MPC8xx"
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 3ea62caada..184063c40b 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -22,6 +22,7 @@ config TARGET_VME8349
config TARGET_MPC8308RDB
bool "Support MPC8308RDB"
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
@@ -38,6 +39,9 @@ config TARGET_MPC832XEMDS
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
+ select SYS_FSL_DDR
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_DDR_BE
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
@@ -66,9 +70,11 @@ config TARGET_TQM834X
config TARGET_HRCON
bool "Support hrcon"
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER
bool "Support strider"
+ select SYS_FSL_ERRATUM_ESDHC111
endchoice
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index e4873f5e82..704f65b093 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -68,6 +68,8 @@ config TARGET_P5040DS
config TARGET_MPC8536DS
bool "Support MPC8536DS"
select ARCH_MPC8536
+# Use DDR3 controller with DDR2 DIMMs on this board
+ select SYS_FSL_DDRC_GEN3
config TARGET_MPC8540ADS
bool "Support MPC8540ADS"
@@ -104,6 +106,8 @@ config TARGET_MPC8569MDS
config TARGET_MPC8572DS
bool "Support MPC8572DS"
select ARCH_MPC8572
+# Use DDR3 controller with DDR2 DIMMs on this board
+ select SYS_FSL_DDRC_GEN3
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
@@ -300,6 +304,8 @@ config TARGET_XPEDITE520X
config TARGET_XPEDITE537X
bool "Support xpedite537x"
select ARCH_MPC8572
+# Use DDR3 controller with DDR2 DIMMs on this board
+ select SYS_FSL_DDRC_GEN3
config TARGET_XPEDITE550X
bool "Support xpedite550x"
@@ -323,154 +329,595 @@ endchoice
config ARCH_B4420
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006384
+ select SYS_FSL_ERRATUM_A006475
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_B4860
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006384
+ select SYS_FSL_ERRATUM_A006475
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_BSC9131
bool
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9132
bool
select FSL_LAW
+ select SYS_FSL_DDR_VER_46
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_A005434
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_IFC_A002769
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_C29X
bool
select FSL_LAW
+ select SYS_FSL_DDR_VER_46
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_6
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8536
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8540
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
config ARCH_MPC8541
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8544
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8548
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_NMG_DDR120
+ select SYS_FSL_ERRATUM_NMG_LBC103
+ select SYS_FSL_ERRATUM_NMG_ETSEC129
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8555
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8560
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
config ARCH_MPC8568
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8569
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8572
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_DDR_115
+ select SYS_FSL_ERRATUM_DDR111_DDR134
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1010
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_IFC_A002769
+ select SYS_FSL_ERRATUM_P1010_A003549
+ select SYS_FSL_ERRATUM_SEC_A003571
+ select SYS_FSL_ERRATUM_IFC_A003399
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1011
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1020
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1021
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1022
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_SATA_A001
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1023
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P1024
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1025
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2020
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC_A001
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2041
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_CPU_A003999
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_NMG_CPU_A011
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P3041
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A005812
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_CPU_A003999
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_NMG_CPU_A011
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P4080
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004580
+ select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A005812
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_CPC_A002
+ select SYS_FSL_ERRATUM_CPC_A003
+ select SYS_FSL_ERRATUM_CPU_A003999
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC13
+ select SYS_FSL_ERRATUM_ESDHC135
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_NMG_CPU_A011
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_P4080_ERRATUM_CPU22
+ select SYS_P4080_ERRATUM_PCIE_A003
+ select SYS_P4080_ERRATUM_SERDES8
+ select SYS_P4080_ERRATUM_SERDES9
+ select SYS_P4080_ERRATUM_SERDES_A001
+ select SYS_P4080_ERRATUM_SERDES_A005
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P5020
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_P5040
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004699
+ select SYS_FSL_ERRATUM_A005812
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_QEMU_E500
bool
config ARCH_T1023
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T1024
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T1040
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008044
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T1042
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008044
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T2080
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_T2081
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_T4160
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004468
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007798
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_T4240
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004468
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007798
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config BOOKE
+ bool
+ default y
+
+config E500
+ bool
+ default y
+ help
+ Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
+
+config E500MC
+ bool
+ help
+ Enble PowerPC E500MC core
+
+config E6500
+ bool
+ help
+ Enable PowerPC E6500 core
config FSL_LAW
bool
@@ -507,8 +954,6 @@ config MAX_CPUS
ARCH_P1025 || \
ARCH_P2020 || \
ARCH_P5020 || \
- ARCH_T1020 || \
- ARCH_T1022 || \
ARCH_T1023 || \
ARCH_T1024
default 1
@@ -550,10 +995,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P4080 || \
ARCH_P5020 || \
ARCH_P5040 || \
- ARCH_T1013 || \
- ARCH_T1014 || \
- ARCH_T1020 || \
- ARCH_T1022 || \
ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
@@ -569,6 +1010,157 @@ config SYS_CCSRBAR_DEFAULT
if changed by pre-boot regime. The value here must match
the current value in SoC. If not sure, do not change.
+config SYS_FSL_ERRATUM_A004468
+ bool
+
+config SYS_FSL_ERRATUM_A004477
+ bool
+
+config SYS_FSL_ERRATUM_A004508
+ bool
+
+config SYS_FSL_ERRATUM_A004580
+ bool
+
+config SYS_FSL_ERRATUM_A004699
+ bool
+
+config SYS_FSL_ERRATUM_A004849
+ bool
+
+config SYS_FSL_ERRATUM_A004510
+ bool
+
+config SYS_FSL_ERRATUM_A004510_SVR_REV
+ hex
+ depends on SYS_FSL_ERRATUM_A004510
+ default 0x20 if ARCH_P4080
+ default 0x10
+
+config SYS_FSL_ERRATUM_A004510_SVR_REV2
+ hex
+ depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
+ default 0x11
+
+config SYS_FSL_ERRATUM_A005125
+ bool
+
+config SYS_FSL_ERRATUM_A005434
+ bool
+
+config SYS_FSL_ERRATUM_A005812
+ bool
+
+config SYS_FSL_ERRATUM_A005871
+ bool
+
+config SYS_FSL_ERRATUM_A006261
+ bool
+
+config SYS_FSL_ERRATUM_A006379
+ bool
+
+config SYS_FSL_ERRATUM_A006384
+ bool
+
+config SYS_FSL_ERRATUM_A006475
+ bool
+
+config SYS_FSL_ERRATUM_A006593
+ bool
+
+config SYS_FSL_ERRATUM_A007075
+ bool
+
+config SYS_FSL_ERRATUM_A007186
+ bool
+
+config SYS_FSL_ERRATUM_A007212
+ bool
+
+config SYS_FSL_ERRATUM_A007798
+ bool
+
+config SYS_FSL_ERRATUM_A008044
+ bool
+
+config SYS_FSL_ERRATUM_CPC_A002
+ bool
+
+config SYS_FSL_ERRATUM_CPC_A003
+ bool
+
+config SYS_FSL_ERRATUM_CPU_A003999
+ bool
+
+config SYS_FSL_ERRATUM_ELBC_A001
+ bool
+
+config SYS_FSL_ERRATUM_I2C_A004447
+ bool
+
+config SYS_FSL_A004447_SVR_REV
+ hex
+ depends on SYS_FSL_ERRATUM_I2C_A004447
+ default 0x00 if ARCH_MPC8548
+ default 0x10 if ARCH_P1010
+ default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
+ default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
+
+config SYS_FSL_ERRATUM_IFC_A002769
+ bool
+
+config SYS_FSL_ERRATUM_IFC_A003399
+ bool
+
+config SYS_FSL_ERRATUM_NMG_CPU_A011
+ bool
+
+config SYS_FSL_ERRATUM_NMG_ETSEC129
+ bool
+
+config SYS_FSL_ERRATUM_NMG_LBC103
+ bool
+
+config SYS_FSL_ERRATUM_P1010_A003549
+ bool
+
+config SYS_FSL_ERRATUM_SATA_A001
+ bool
+
+config SYS_FSL_ERRATUM_SEC_A003571
+ bool
+
+config SYS_FSL_ERRATUM_SRIO_A004034
+ bool
+
+config SYS_FSL_ERRATUM_USB14
+ bool
+
+config SYS_P4080_ERRATUM_CPU22
+ bool
+
+config SYS_P4080_ERRATUM_PCIE_A003
+ bool
+
+config SYS_P4080_ERRATUM_SERDES8
+ bool
+
+config SYS_P4080_ERRATUM_SERDES9
+ bool
+
+config SYS_P4080_ERRATUM_SERDES_A001
+ bool
+
+config SYS_P4080_ERRATUM_SERDES_A005
+ bool
+
+config SYS_FSL_QORIQ_CHASSIS1
+ bool
+
+config SYS_FSL_QORIQ_CHASSIS2
+ bool
+
config SYS_FSL_NUM_LAWS
int "Number of local access windows"
depends on FSL_LAW
@@ -583,11 +1175,7 @@ config SYS_FSL_NUM_LAWS
ARCH_T2081 || \
ARCH_T4160 || \
ARCH_T4240
- default 16 if ARCH_T1013 || \
- ARCH_T1014 || \
- ARCH_T1020 || \
- ARCH_T1022 || \
- ARCH_T1023 || \
+ default 16 if ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042
@@ -617,6 +1205,49 @@ config SYS_FSL_NUM_LAWS
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
+config SYS_FSL_THREADS_PER_CORE
+ int
+ default 2 if E6500
+ default 1
+
+config SYS_NUM_TLBCAMS
+ int "Number of TLB CAM entries"
+ default 64 if E500MC
+ default 16
+ help
+ Number of TLB CAM entries for Book-E chips. 64 for E500MC,
+ 16 for other E500 SoCs.
+
+config SYS_PPC64
+ bool
+
+config SYS_PPC_E500_USE_DEBUG_TLB
+ bool
+
+config SYS_PPC_E500_DEBUG_TLB
+ int "Temporary TLB entry for external debugger"
+ depends on SYS_PPC_E500_USE_DEBUG_TLB
+ default 0 if ARCH_MPC8544 || ARCH_MPC8548
+ default 1 if ARCH_MPC8536
+ default 2 if ARCH_MPC8572 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 3 if ARCH_P1010 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X
+ help
+ Select a temporary TLB entry to be used during boot to work
+ around limitations in e500v1 and e500v2 external debugger
+ support. This reduces the portions of the boot code where
+ breakpoints and single stepping do not work. The value of this
+ symbol should be set to the TLB1 entry to be used for this
+ purpose. If unsure, do not change.
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 46ed22cafc..04585d0608 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -50,8 +50,6 @@ obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
-obj-$(CONFIG_PPC_T1020) += t1040_ids.o
-obj-$(CONFIG_PPC_T1022) += t1040_ids.o
obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
@@ -92,8 +90,6 @@ obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 402a1ff33c..54b5b33222 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -136,7 +136,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#endif
__maybe_unused u32 svr = get_svr();
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
if (IS_SVR_REV(svr, 1, 0)) {
switch (SVR_SOC_VER(svr)) {
case SVR_P1013:
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index d180c73929..cc30fa6e17 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -482,17 +482,17 @@ static void dump_spd_ddr_reg(void)
int i, j, k, m;
u8 *p_8;
u32 *p_32;
- struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+ struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
generic_spd_eeprom_t
- spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+ spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
puts("SPD data of all dimms (zero value is omitted)...\n");
puts("Byte (hex) ");
k = 1;
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
printf("Dimm%d ", k++);
}
@@ -500,7 +500,7 @@ static void dump_spd_ddr_reg(void)
for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
m = 0;
printf("%3d (0x%02x) ", k, k);
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
p_8 = (u8 *) &spd[i][j];
if (p_8[k]) {
@@ -516,22 +516,22 @@ static void dump_spd_ddr_reg(void)
puts("\r");
}
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
@@ -545,13 +545,13 @@ static void dump_spd_ddr_reg(void)
printf("DDR registers dump for all controllers "
"(zero value is omitted)...\n");
puts("Offset (hex) ");
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
p_32 = (u32 *) ddr[i];
if (p_32[k]) {
printf(" 0x%08x", p_32[k]);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d1b6699a6a..822844dfa9 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -378,10 +378,10 @@ void fsl_erratum_a007212_workaround(void)
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
#endif
@@ -409,25 +409,25 @@ void fsl_erratum_a007212_workaround(void)
ddr_pll_ratio >>= 1;
setbits_be32(plldadcr1, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
setbits_be32(plldadcr2, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
setbits_be32(plldadcr3, 0x02000001);
#endif
#endif
setbits_be32(dpdovrcr4, 0xe0000000);
out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
#endif
#endif
udelay(100);
clrbits_be32(plldadcr1, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
clrbits_be32(plldadcr2, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
clrbits_be32(plldadcr3, 0x02000001);
#endif
#endif
@@ -975,7 +975,7 @@ int cpu_init_r(void)
#endif
#endif
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
* controller is configured in legacy mode instead of the
diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index 11afffa830..ff21c4823b 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -29,10 +29,14 @@ endchoice
config ARCH_MPC8610
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_DDR2
config ARCH_MPC8641
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_DDR2
config FSL_LAW
bool
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 9d3a3b45c0..55686a1abf 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -9,16 +9,13 @@
#ifdef CONFIG_MPC85xx
#include <asm/config_mpc85xx.h>
-#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC86xx
#include <asm/config_mpc86xx.h>
-#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC83xx
-#define CONFIG_SYS_FSL_DDR
#endif
#ifndef HWCONFIG_BUFFER_SIZE
@@ -67,14 +64,6 @@
#endif
#endif
-/*
- * SEC (crypto unit) major compatible version determination
- */
-#if defined(CONFIG_MPC83xx)
-#define CONFIG_SYS_FSL_SEC_BE
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#endif
-
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 8cfc6127a7..6fd218a428 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -16,66 +16,20 @@
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
#include <fsl_ddrc_version.h>
-#define CONFIG_SYS_FSL_DDR_BE
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SEC_MON_BE
-/* Number of TLB CAM entries we have on FSL Book-E chips */
-#if defined(CONFIG_E500MC)
-#define CONFIG_SYS_NUM_TLBCAMS 64
-#elif defined(CONFIG_E500)
-#define CONFIG_SYS_NUM_TLBCAMS 16
-#endif
-
-#if defined(CONFIG_ARCH_MPC8536)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_ARCH_MPC8540)
-#define CONFIG_SYS_FSL_DDRC_GEN1
-
-#elif defined(CONFIG_ARCH_MPC8541)
-#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-
-#elif defined(CONFIG_ARCH_MPC8544)
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_ARCH_MPC8548)
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
-#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
-#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+#if defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
-
-#elif defined(CONFIG_ARCH_MPC8555)
-#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-
-#elif defined(CONFIG_ARCH_MPC8560)
-#define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8568)
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
@@ -86,7 +40,6 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_MPC8569)
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x20000UL
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
@@ -95,159 +48,80 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_ARCH_MPC8572)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_DDR_115
-#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
-#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1020)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#elif defined(CONFIG_ARCH_P1021)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_FSL_SATA_ERRATUM_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_ARCH_P1023)
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
@@ -255,35 +129,17 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_A004849
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#elif defined(CONFIG_ARCH_P3041)
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
@@ -291,85 +147,36 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_A004849
-#define CONFIG_SYS_FSL_ERRATUM_A005812
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
-#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
-#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
-#define CONFIG_SYS_P4080_ERRATUM_CPU22
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_P4080_ERRATUM_SERDES8
-#define CONFIG_SYS_P4080_ERRATUM_SERDES9
-#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
-#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_A004849
-#define CONFIG_SYS_FSL_ERRATUM_A004580
-#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
-#define CONFIG_SYS_FSL_ERRATUM_A005812
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A007075
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
-#define CONFIG_SYS_PPC64 /* 64-bit core */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
@@ -377,34 +184,19 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_SYS_PPC64
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -412,40 +204,21 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_ERRATUM_A004699
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
-#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
@@ -453,21 +226,12 @@
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A005434
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
-#define CONFIG_E6500
-#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#ifdef CONFIG_ARCH_T4240
@@ -476,14 +240,11 @@
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 3
-#define CONFIG_SYS_FSL_ERRATUM_A006261
#else
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#if defined(CONFIG_ARCH_T4160)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#endif
@@ -493,11 +254,9 @@
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRDS_3
#define CONFIG_SYS_FSL_SRDS_4
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_PME_CLK 0
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM1_CLK 3
@@ -511,21 +270,11 @@
#define CONFIG_SYS_FSL_SRIO_LIODN
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_A004468
-#define CONFIG_SYS_FSL_ERRATUM_A005871
-#define CONFIG_SYS_FSL_ERRATUM_A006379
-#define CONFIG_SYS_FSL_ERRATUM_A007186
-#define CONFIG_SYS_FSL_ERRATUM_A006593
-#define CONFIG_SYS_FSL_ERRATUM_A007798
-#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_E6500
-#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
@@ -535,30 +284,18 @@
#define CONFIG_SYS_MAPLE
#define CONFIG_SYS_CPRI
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_CPRI_CLK 3
#define CONFIG_SYS_ULB_CLK 4
#define CONFIG_SYS_ETVPE_CLK 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A005871
-#define CONFIG_SYS_FSL_ERRATUM_A006379
-#define CONFIG_SYS_FSL_ERRATUM_A007186
-#define CONFIG_SYS_FSL_ERRATUM_A006593
-#define CONFIG_SYS_FSL_ERRATUM_A007075
-#define CONFIG_SYS_FSL_ERRATUM_A006475
-#define CONFIG_SYS_FSL_ERRATUM_A006384
-#define CONFIG_SYS_FSL_ERRATUM_A007212
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_ARCH_B4860
@@ -569,7 +306,6 @@
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
@@ -582,32 +318,22 @@
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#endif
-#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
-defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FSL_ERRATUM_A008044
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
@@ -620,38 +346,26 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
-defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#define CONFIG_SYS_FMAN_V3
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
@@ -663,25 +377,17 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009942
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
-#define CONFIG_E6500
-#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_QMAN_V3
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
@@ -699,14 +405,12 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
per rcw field value */
#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
@@ -714,48 +418,19 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A006593
-#define CONFIG_SYS_FSL_ERRATUM_A007186
-#define CONFIG_SYS_FSL_ERRATUM_A006379
-#define CONFIG_SYS_FSL_ERRATUM_A009942
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 6
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
-#elif defined(CONFIG_ARCH_QEMU_E500)
-
-#else
-#error Processor type not defined for this platform
-#endif
-
-#ifdef CONFIG_E6500
-#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
-#else
-#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
-#endif
-
-#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN4)
-#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
#if !defined(CONFIG_ARCH_C29X)
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
index f053b9cf5e..5eabe6df41 100644
--- a/arch/powerpc/include/asm/config_mpc86xx.h
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -7,6 +7,4 @@
#ifndef _ASM_MPC86xx_CONFIG_H_
#define _ASM_MPC86xx_CONFIG_H_
-#define CONFIG_SYS_FSL_DDR_86XX
-
#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 808adae82d..10e26d6cd5 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -29,10 +29,9 @@
defined(CONFIG_TARGET_B4420QDS) || \
defined(CONFIG_TARGET_T4160QDS) || \
defined(CONFIG_TARGET_T4240QDS) || \
- defined(CONFIG_T2080QDS) || \
- defined(CONFIG_T2080RDB) || \
- defined(CONFIG_T1040QDS) || \
- defined(CONFIG_T104xD4QDS) || \
+ defined(CONFIG_TARGET_T2080QDS) || \
+ defined(CONFIG_TARGET_T2080RDB) || \
+ defined(CONFIG_TARGET_T1040QDS) || \
defined(CONFIG_TARGET_T1040RDB) || \
defined(CONFIG_TARGET_T1040D4RDB) || \
defined(CONFIG_TARGET_T1042RDB) || \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 786e4f6765..762b174b2d 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1775,8 +1775,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
-#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
-defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
@@ -1796,8 +1795,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) || \
- defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
generated by cgit (git 2.34.1) at 2025-01-23 22:35:07 +0000