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Diffstat (limited to 'arch/riscv/cpu/ax25/cache.c')
-rw-r--r--arch/riscv/cpu/ax25/cache.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 8d6ae170b8..228fc55f56 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -6,6 +6,28 @@
#include <common.h>
+void flush_dcache_all(void)
+{
+ /*
+ * Andes' AX25 does not have a coherence agent. U-Boot must use data
+ * cache flush and invalidate functions to keep data in the system
+ * coherent.
+ * The implementation of the fence instruction in the AX25 flushes the
+ * data cache and is used for this purpose.
+ */
+ asm volatile ("fence" ::: "memory");
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ flush_dcache_all();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ flush_dcache_all();
+}
+
void icache_enable(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF