diff options
Diffstat (limited to 'arch/riscv/cpu')
-rw-r--r-- | arch/riscv/cpu/Makefile | 7 | ||||
-rw-r--r-- | arch/riscv/cpu/ax25/Makefile | 2 | ||||
-rw-r--r-- | arch/riscv/cpu/ax25/cpu.c | 9 | ||||
-rw-r--r-- | arch/riscv/cpu/cpu.c | 49 | ||||
-rw-r--r-- | arch/riscv/cpu/qemu/Makefile | 6 | ||||
-rw-r--r-- | arch/riscv/cpu/qemu/cpu.c | 21 | ||||
-rw-r--r-- | arch/riscv/cpu/qemu/dram.c | 17 | ||||
-rw-r--r-- | arch/riscv/cpu/start.S (renamed from arch/riscv/cpu/ax25/start.S) | 0 | ||||
-rw-r--r-- | arch/riscv/cpu/u-boot.lds (renamed from arch/riscv/cpu/ax25/u-boot.lds) | 60 |
9 files changed, 129 insertions, 42 deletions
diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile new file mode 100644 index 0000000000..2cc6757fcf --- /dev/null +++ b/arch/riscv/cpu/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + +extra-y = start.o + +obj-y += cpu.o diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile index c3f164c122..2ab0342fe8 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/ax25/Makefile @@ -3,6 +3,4 @@ # Copyright (C) 2017 Andes Technology Corporation # Rick Chen, Andes Technology Corporation <rick@andestech.com> -extra-y = start.o - obj-y := cpu.o diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index ab05b57d4f..fddcc156c3 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -6,9 +6,6 @@ /* CPU specific code */ #include <common.h> -#include <command.h> -#include <watchdog.h> -#include <asm/cache.h> /* * cleanup_before_linux() is called just before we call linux @@ -24,9 +21,3 @@ int cleanup_before_linux(void) return 0; } - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - disable_interrupts(); - panic("ax25-ae350 wdt not support yet.\n"); -} diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c new file mode 100644 index 0000000000..ae57fb8313 --- /dev/null +++ b/arch/riscv/cpu/cpu.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <asm/csr.h> + +enum { + ISA_INVALID = 0, + ISA_32BIT, + ISA_64BIT, + ISA_128BIT +}; + +static const char * const isa_bits[] = { + [ISA_INVALID] = NULL, + [ISA_32BIT] = "32", + [ISA_64BIT] = "64", + [ISA_128BIT] = "128" +}; + +static inline bool supports_extension(char ext) +{ + return csr_read(misa) & (1 << (ext - 'a')); +} + +int print_cpuinfo(void) +{ + char name[32]; + char *s = name; + int bit; + + s += sprintf(name, "rv"); + bit = csr_read(misa) >> (sizeof(long) * 8 - 2); + s += sprintf(s, isa_bits[bit]); + + supports_extension('i') ? *s++ = 'i' : 'r'; + supports_extension('m') ? *s++ = 'm' : 'i'; + supports_extension('a') ? *s++ = 'a' : 's'; + supports_extension('f') ? *s++ = 'f' : 'c'; + supports_extension('d') ? *s++ = 'd' : '-'; + supports_extension('c') ? *s++ = 'c' : 'v'; + *s++ = '\0'; + + printf("CPU: %s\n", name); + + return 0; +} diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/qemu/Makefile new file mode 100644 index 0000000000..258e4620dd --- /dev/null +++ b/arch/riscv/cpu/qemu/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c new file mode 100644 index 0000000000..6c7a32755a --- /dev/null +++ b/arch/riscv/cpu/qemu/cpu.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + /* turn off I/D-cache */ + + return 0; +} diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/qemu/dram.c new file mode 100644 index 0000000000..84d87d2a7f --- /dev/null +++ b/arch/riscv/cpu/qemu/dram.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <fdtdec.h> + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/arch/riscv/cpu/ax25/start.S b/arch/riscv/cpu/start.S index 7cd7755190..7cd7755190 100644 --- a/arch/riscv/cpu/ax25/start.S +++ b/arch/riscv/cpu/start.S diff --git a/arch/riscv/cpu/ax25/u-boot.lds b/arch/riscv/cpu/u-boot.lds index c50b9642f1..11bc4a738b 100644 --- a/arch/riscv/cpu/ax25/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -3,28 +3,27 @@ * Copyright (C) 2017 Andes Technology Corporation * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ + OUTPUT_ARCH("riscv") ENTRY(_start) SECTIONS { . = ALIGN(4); - .text : - { - arch/riscv/cpu/ax25/start.o (.text) + .text : { + arch/riscv/cpu/start.o (.text) } /* This needs to come before *(.text*) */ .efi_runtime : { - __efi_runtime_start = .; + __efi_runtime_start = .; *(.text.efi_runtime*) *(.rodata.efi_runtime*) *(.data.efi_runtime*) - __efi_runtime_stop = .; + __efi_runtime_stop = .; } - .text_rest : - { + .text_rest : { *(.text*) } @@ -39,10 +38,10 @@ SECTIONS . = ALIGN(4); .got : { - __got_start = .; - *(.got.plt) *(.got) - __got_end = .; - } + __got_start = .; + *(.got.plt) *(.got) + __got_end = .; + } . = ALIGN(4); @@ -50,41 +49,40 @@ SECTIONS KEEP(*(SORT(.u_boot_list*))); } - . = ALIGN(4); + . = ALIGN(4); .efi_runtime_rel : { - __efi_runtime_rel_start = .; + __efi_runtime_rel_start = .; *(.rel*.efi_runtime) *(.rel*.efi_runtime.*) - __efi_runtime_rel_stop = .; + __efi_runtime_rel_stop = .; } - . = ALIGN(4); + . = ALIGN(4); - /DISCARD/ : { *(.rela.plt*) } - .rela.dyn : { - __rel_dyn_start = .; - *(.rela*) - __rel_dyn_end = .; - } + /DISCARD/ : { *(.rela.plt*) } + .rela.dyn : { + __rel_dyn_start = .; + *(.rela*) + __rel_dyn_end = .; + } - . = ALIGN(4); + . = ALIGN(4); - .dynsym : { - __dyn_sym_start = .; - *(.dynsym) - __dyn_sym_end = .; - } + .dynsym : { + __dyn_sym_start = .; + *(.dynsym) + __dyn_sym_end = .; + } - . = ALIGN(4); + . = ALIGN(4); _end = .; .bss : { - __bss_start = .; - *(.bss*) + __bss_start = .; + *(.bss*) . = ALIGN(4); __bss_end = .; } - } |