diff options
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/ax25/cache.c | 22 | ||||
| -rw-r--r-- | arch/riscv/lib/cache.c | 10 |
2 files changed, 26 insertions, 6 deletions
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 8d6ae170b8..228fc55f56 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -6,6 +6,28 @@ #include <common.h> +void flush_dcache_all(void) +{ + /* + * Andes' AX25 does not have a coherence agent. U-Boot must use data + * cache flush and invalidate functions to keep data in the system + * coherent. + * The implementation of the fence instruction in the AX25 flushes the + * data cache and is used for this purpose. + */ + asm volatile ("fence" ::: "memory"); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + void icache_enable(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index ae5c60716f..78b19da2c5 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -11,13 +11,12 @@ void invalidate_icache_all(void) asm volatile ("fence.i" ::: "memory"); } -void flush_dcache_all(void) +__weak void flush_dcache_all(void) { - asm volatile ("fence" :::"memory"); } -void flush_dcache_range(unsigned long start, unsigned long end) + +__weak void flush_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +__weak void invalidate_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void cache_flush(void) |