diff options
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/Kconfig | 37 | ||||
| -rw-r--r-- | arch/riscv/cpu/ax25/cache.c | 8 | ||||
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 4 | ||||
| -rw-r--r-- | arch/riscv/cpu/start.S | 8 | ||||
| -rw-r--r-- | arch/riscv/include/asm/global_data.h | 2 | ||||
| -rw-r--r-- | arch/riscv/lib/Makefile | 1 | ||||
| -rw-r--r-- | arch/riscv/lib/asm-offsets.c | 2 | ||||
| -rw-r--r-- | arch/riscv/lib/image.c | 55 | ||||
| -rw-r--r-- | arch/riscv/lib/smp.c | 2 |
9 files changed, 115 insertions, 4 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae8ff7b765..8cfc7d0faa 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_AX25_AE350 bool "Support ax25-ae350" +config TARGET_MICROCHIP_ICICLE + bool "Support Microchip PolarFire-SoC Icicle Board" + config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" @@ -19,9 +22,36 @@ config TARGET_SIFIVE_FU540 endchoice +config SYS_ICACHE_OFF + bool "Do not enable icache" + default n + help + Do not enable instruction cache in U-Boot. + +config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default SYS_ICACHE_OFF + help + Do not enable instruction cache in SPL. + +config SYS_DCACHE_OFF + bool "Do not enable dcache" + default n + help + Do not enable data cache in U-Boot. + +config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default SYS_DCACHE_OFF + help + Do not enable data cache in SPL. + # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" +source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/fu540/Kconfig" # platform-specific options below @@ -162,6 +192,13 @@ config SBI_IPI default y if RISCV_SMODE depends on SMP +config XIP + bool "XIP mode" + help + XIP (eXecute In Place) is a method for executing code directly + from a NOR flash memory without copying the code to ram. + Say yes here if U-Boot boots from flash directly. + config STACK_SIZE_SHIFT int default 13 diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 228fc55f56..cd95058d9d 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -30,7 +30,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) void icache_enable(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -43,7 +43,7 @@ void icache_enable(void) void icache_disable(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "fence.i\n\t" @@ -57,7 +57,7 @@ void icache_disable(void) void dcache_enable(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -70,7 +70,7 @@ void dcache_enable(void) void dcache_disable(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "fence\n\t" diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c32de8a4c3..e9a8b437ed 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -15,7 +15,10 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ +#ifdef CONFIG_OF_PRIOR_STAGE phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#endif +#ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* @@ -23,6 +26,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0; * finished initialization of global data. */ u32 available_harts_lock = 1; +#endif static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a4433fbd6b..60ac8c621e 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -98,6 +98,7 @@ call_board_init_f_0: mv sp, a0 #endif +#ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -106,15 +107,21 @@ call_board_init_f_0: li s2, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else + bnez tp, secondary_hart_loop +#endif +#ifdef CONFIG_OF_PRIOR_STAGE la t0, prior_stage_fdt_address SREG s1, 0(t0) +#endif jal board_init_f_init_reserve /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp) +#ifndef CONFIG_XIP la t0, available_harts_lock fence rw, w amoswap.w zero, zero, 0(t0) @@ -141,6 +148,7 @@ wait_for_gd_init: * secondary_hart_loop. */ bnez s2, secondary_hart_loop +#endif /* Enable cache */ jal icache_enable diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index dffcd45bf0..b74bd7e738 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -27,7 +27,9 @@ struct arch_global_data { #ifdef CONFIG_SMP struct ipi_data ipi[CONFIG_NR_CPUS]; #endif +#ifndef CONFIG_XIP ulong available_harts; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 1c332db436..6ae6ebbeaf 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -7,6 +7,7 @@ # Rick Chen, Andes Technology Corporation <rick@andestech.com> obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_RISCV_RDTIME) += rdtime.o diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f998402bd1..4fa4fd3714 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -14,7 +14,9 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); +#ifndef CONFIG_XIP DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); +#endif return 0; } diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c new file mode 100644 index 0000000000..d063beb7df --- /dev/null +++ b/arch/riscv/lib/image.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * Authors: + * Atish Patra <atish.patra@wdc.com> + * Based on arm/lib/image.c + */ + +#include <common.h> +#include <mapmem.h> +#include <errno.h> +#include <linux/sizes.h> +#include <linux/stddef.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ASCII version of "RISCV" defined in Linux kernel */ +#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952 + +struct linux_image_h { + uint32_t code0; /* Executable code */ + uint32_t code1; /* Executable code */ + uint64_t text_offset; /* Image load offset */ + uint64_t image_size; /* Effective Image size */ + uint64_t res1; /* reserved */ + uint64_t res2; /* reserved */ + uint64_t res3; /* reserved */ + uint64_t magic; /* Magic number */ + uint32_t res4; /* reserved */ + uint32_t res5; /* reserved */ +}; + +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc) +{ + struct linux_image_h *lhdr; + + lhdr = (struct linux_image_h *)map_sysmem(image, 0); + + if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) { + puts("Bad Linux RISCV Image magic!\n"); + return -EINVAL; + } + + if (lhdr->image_size == 0) { + puts("Image lacks image_size field, error!\n"); + return -EINVAL; + } + *size = lhdr->image_size; + *relocated_addr = gd->ram_base + lhdr->text_offset; + + unmap_sysmem(lhdr); + + return 0; +} diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index caa292ccd2..cc66f15567 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi) continue; } +#ifndef CONFIG_XIP /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; +#endif gd->arch.ipi[reg].addr = ipi->addr; gd->arch.ipi[reg].arg0 = ipi->arg0; |