diff options
Diffstat (limited to 'arch/sh/include/asm')
| -rw-r--r-- | arch/sh/include/asm/cpu_sh2.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh4.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7269.h | 26 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7734.h | 70 | ||||
| -rw-r--r-- | arch/sh/include/asm/io.h | 43 |
5 files changed, 140 insertions, 3 deletions
diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h index 767e18901b..28be591e79 100644 --- a/arch/sh/include/asm/cpu_sh2.h +++ b/arch/sh/include/asm/cpu_sh2.h @@ -35,6 +35,8 @@ # include <asm/cpu_sh7203.h> #elif defined(CONFIG_CPU_SH7264) # include <asm/cpu_sh7264.h> +#elif defined(CONFIG_CPU_SH7269) +# include <asm/cpu_sh7269.h> #else # error "Unknown SH2 variant" #endif diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index 4351e8edff..f1f49fe7fa 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -46,6 +46,8 @@ # include <asm/cpu_sh7723.h> #elif defined (CONFIG_CPU_SH7724) # include <asm/cpu_sh7724.h> +#elif defined (CONFIG_CPU_SH7734) +# include <asm/cpu_sh7734.h> #elif defined (CONFIG_CPU_SH7757) # include <asm/cpu_sh7757.h> #elif defined (CONFIG_CPU_SH7763) diff --git a/arch/sh/include/asm/cpu_sh7269.h b/arch/sh/include/asm/cpu_sh7269.h new file mode 100644 index 0000000000..4dea7086d4 --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7269.h @@ -0,0 +1,26 @@ +#ifndef _ASM_CPU_SH7269_H_ +#define _ASM_CPU_SH7269_H_ + +/* Cache */ +#define CCR1 0xFFFC1000 +#define CCR CCR1 + +/* SCIF */ +#define SCSMR_0 0xE8007000 +#define SCIF0_BASE SCSMR_0 +#define SCSMR_1 0xE8007800 +#define SCIF1_BASE SCSMR_1 +#define SCSMR_2 0xE8008000 +#define SCIF2_BASE SCSMR_2 +#define SCSMR_3 0xE8008800 +#define SCIF3_BASE SCSMR_3 +#define SCSMR_7 0xE800A800 +#define SCIF7_BASE SCSMR_7 + +/* Timer(CMT) */ +#define CMSTR 0xFFFEC000 +#define CMCSR_0 0xFFFEC002 +#define CMCNT_0 0xFFFEC004 +#define CMCOR_0 0xFFFEC006 + +#endif /* _ASM_CPU_SH7269_H_ */ diff --git a/arch/sh/include/asm/cpu_sh7734.h b/arch/sh/include/asm/cpu_sh7734.h new file mode 100644 index 0000000000..0f84b4f57c --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7734.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2008, 2011 Renesas Solutions Corp. + * + * SH7734 Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH7734_H_ +#define _ASM_CPU_SH7734_H_ + +#define CCR 0xFF00001C + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000090d + +/* SCIF */ +#define SCIF0_BASE 0xFFE40000 +#define SCIF1_BASE 0xFFE41000 +#define SCIF2_BASE 0xFFE42000 +#define SCIF3_BASE 0xFFE43000 +#define SCIF4_BASE 0xFFE44000 +#define SCIF5_BASE 0xFFE45000 + +/* Timer */ +#define TSTR 0xFFD80004 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 + +/* PFC */ +#define PMMR (0xFFFC0000) +#define MODESEL0 (0xFFFC004C) +#define MODESEL2 (MODESEL0 + 0x4) +#define MODESEL2_INIT (0x00003000) + +#define IPSR0 (0xFFFC001C) +#define IPSR1 (IPSR0 + 0x4) +#define IPSR2 (IPSR0 + 0x8) +#define IPSR3 (IPSR0 + 0xC) +#define IPSR4 (IPSR0 + 0x10) +#define IPSR5 (IPSR0 + 0x14) +#define IPSR6 (IPSR0 + 0x18) +#define IPSR7 (IPSR0 + 0x1C) +#define IPSR8 (IPSR0 + 0x20) +#define IPSR9 (IPSR0 + 0x24) +#define IPSR10 (IPSR0 + 0x28) +#define IPSR11 (IPSR0 + 0x2C) + +#define GPSR0 (0xFFFC0004) +#define GPSR1 (GPSR0 + 0x4) +#define GPSR2 (GPSR0 + 0x8) +#define GPSR3 (GPSR0 + 0xC) +#define GPSR4 (GPSR0 + 0x10) +#define GPSR5 (GPSR0 + 0x14) + + +#endif /* _ASM_CPU_SH7734_H_ */ diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index ca598a60f3..0a00db3617 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -147,13 +147,13 @@ extern void __iounmap(void *addr); */ #ifdef iomem_valid_addr #define __arch_ioremap(off, sz, nocache) \ - ({ \ +({ \ unsigned long _off = (off), _size = (sz); \ void *_ret = (void *)0; \ if (iomem_valid_addr(_off, _size)) \ _ret = __ioremap(iomem_to_phys(_off), _size, 0); \ _ret; \ - }) +}) #define __arch_iounmap __iounmap #endif @@ -238,6 +238,43 @@ static inline void sync(void) } /* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +/* * Given a physical address and a length, return a virtual address * that can be used to access the memory range with the caching * properties specified by "flags". @@ -261,7 +298,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } -static inline phys_addr_t virt_to_phys(void * vaddr) +static inline phys_addr_t virt_to_phys(void *vaddr) { return (phys_addr_t)(vaddr); } |