diff options
Diffstat (limited to 'arch/x86/Kconfig')
| -rw-r--r-- | arch/x86/Kconfig | 96 |
1 files changed, 90 insertions, 6 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 90e828a26e..fef11f3552 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -41,6 +41,30 @@ config TARGET_CROWNBAY Intel Platform Controller Hub EG20T, other system components and peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. +config TARGET_MINNOWMAX + bool "Support Intel Minnowboard MAX" + help + This is the Intel Minnowboard MAX. It contains an Atom E3800 + processor in a small form factor with Ethernet, micro-SD, USB 2, + USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + +config TARGET_GALILEO + bool "Support Intel Galileo" + help + This is the Intel Galileo board, which is the first in a family of + Arduino-certified development and prototyping boards based on Intel + architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit + single-core, single-thread, Intel Pentium processor instrunction set + architecture (ISA) compatible, operating at speeds up to 400Mhz, + along with 256MB DDR3 memory. It supports a wide range of industry + standard I/O interfaces, including a full-sized mini-PCIe slot, + one 100Mb Ethernet port, a microSD card slot, a USB host port and + a USB client port. + endchoice config RAMBASE @@ -324,6 +348,54 @@ config FRAMEBUFFER_VESA_MODE endmenu +config HAVE_FSP + bool "Add an Firmware Support Package binary" + help + Select this option to add an Firmware Support Package binary to + the resulting U-Boot image. It is a binary blob which U-Boot uses + to set up SDRAM and other chipset specific initialization. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config FSP_FILE + string "Firmware Support Package binary filename" + depends on HAVE_FSP + default "fsp.bin" + help + The filename of the file to use as Firmware Support Package binary + in the board directory. + +config FSP_ADDR + hex "Firmware Support Package binary location" + depends on HAVE_FSP + default 0xfffc0000 + help + FSP is not Position Independent Code (PIC) and the whole FSP has to + be rebased if it is placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + + The default base address of 0xfffc0000 indicates that the binary must + be located at offset 0xc0000 from the beginning of a 1MB flash device. + +config FSP_TEMP_RAM_ADDR + hex + default 0x2000000 + help + Stack top address which is used in FspInit after DRAM is ready and + CAR is disabled. + +source "arch/x86/cpu/baytrail/Kconfig" + +source "arch/x86/cpu/coreboot/Kconfig" + +source "arch/x86/cpu/ivybridge/Kconfig" + +source "arch/x86/cpu/quark/Kconfig" + +source "arch/x86/cpu/queensbay/Kconfig" + config TSC_CALIBRATION_BYPASS bool "Bypass Time-Stamp Counter (TSC) calibration" default n @@ -344,16 +416,28 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). -source "arch/x86/cpu/coreboot/Kconfig" - -source "arch/x86/cpu/ivybridge/Kconfig" - -source "arch/x86/cpu/queensbay/Kconfig" - source "board/coreboot/coreboot/Kconfig" source "board/google/chromebook_link/Kconfig" source "board/intel/crownbay/Kconfig" +source "board/intel/minnowmax/Kconfig" + +source "board/intel/galileo/Kconfig" + +config PCIE_ECAM_BASE + hex + default 0xe0000000 + help + This is the memory-mapped address of PCI configuration space, which + is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. It can be set up almost + anywhere. Before it is set up, it is possible to access PCI + configuration space through I/O access, but memory access is more + convenient. Using this, PCI can be scanned and configured. This + should be set to a region that does not conflict with memory + assigned to PCI devices - i.e. the memory and prefetch regions, as + passed to pci_set_region(). + endmenu |