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-rw-r--r--arch/x86/cpu/i386/cpu.c27
-rw-r--r--arch/x86/cpu/i386/interrupt.c6
2 files changed, 31 insertions, 2 deletions
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index c8da7f10e9..0312a26bbb 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -447,10 +447,37 @@ int x86_cpu_init_f(void)
return 0;
}
+long detect_coreboot_table_at(ulong start, ulong size)
+{
+ u32 *ptr, *end;
+
+ size /= 4;
+ for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
+ if (*ptr == 0x4f49424c) /* "LBIO" */
+ return (long)ptr;
+ }
+
+ return -ENOENT;
+}
+
+long locate_coreboot_table(void)
+{
+ long addr;
+
+ /* We look for LBIO in the first 4K of RAM and again at 960KB */
+ addr = detect_coreboot_table_at(0x0, 0x1000);
+ if (addr < 0)
+ addr = detect_coreboot_table_at(0xf0000, 0x1000);
+
+ return addr;
+}
+
int x86_cpu_reinit_f(void)
{
setup_identity();
setup_pci_ram_top();
+ if (locate_coreboot_table() >= 0)
+ gd->flags |= GD_FLG_SKIP_LL_INIT;
return 0;
}
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index 4c7e9ea215..e67a116ac1 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -264,6 +264,9 @@ int interrupt_init(void)
struct udevice *dev;
int ret;
+ if (!ll_boot_init())
+ return 0;
+
/* Try to set up the interrupt router, but don't require one */
ret = irq_first_device_type(X86_IRQT_BASE, &dev);
if (ret && ret != -ENODEV)
@@ -295,8 +298,7 @@ int interrupt_init(void)
* TODO(sjg@chromium.org): But we don't handle these correctly when
* booted from EFI.
*/
- if (ll_boot_init())
- enable_interrupts();
+ enable_interrupts();
#endif
return 0;