diff options
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/irq.c | 80 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/bd82x6x.c | 43 | ||||
| -rw-r--r-- | arch/x86/cpu/pci.c | 59 | ||||
| -rw-r--r-- | arch/x86/cpu/qemu/qemu.c | 34 | ||||
| -rw-r--r-- | arch/x86/cpu/quark/mrc_util.c | 5 | ||||
| -rw-r--r-- | arch/x86/cpu/quark/quark.c | 17 | ||||
| -rw-r--r-- | arch/x86/cpu/queensbay/irq.c | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/queensbay/tnc.c | 80 |
8 files changed, 156 insertions, 164 deletions
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 0b36ace091..2950783055 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -16,19 +16,18 @@ DECLARE_GLOBAL_DATA_PTR; -static struct irq_router irq_router; static struct irq_routing_table *pirq_routing_table; -bool pirq_check_irq_routed(int link, u8 irq) +bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq) { + struct irq_router *priv = dev_get_priv(dev); u8 pirq; - int base = irq_router.link_base; + int base = priv->link_base; - if (irq_router.config == PIRQ_VIA_PCI) - pirq = x86_pci_read_config8(irq_router.bdf, - LINK_N2V(link, base)); + if (priv->config == PIRQ_VIA_PCI) + dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq); else - pirq = readb(irq_router.ibase + LINK_N2V(link, base)); + pirq = readb(priv->ibase + LINK_N2V(link, base)); pirq &= 0xf; @@ -39,24 +38,26 @@ bool pirq_check_irq_routed(int link, u8 irq) return pirq == irq ? true : false; } -int pirq_translate_link(int link) +int pirq_translate_link(struct udevice *dev, int link) { - return LINK_V2N(link, irq_router.link_base); + struct irq_router *priv = dev_get_priv(dev); + + return LINK_V2N(link, priv->link_base); } -void pirq_assign_irq(int link, u8 irq) +void pirq_assign_irq(struct udevice *dev, int link, u8 irq) { - int base = irq_router.link_base; + struct irq_router *priv = dev_get_priv(dev); + int base = priv->link_base; /* IRQ# 0/1/2/8/13 are reserved */ if (irq < 3 || irq == 8 || irq == 13) return; - if (irq_router.config == PIRQ_VIA_PCI) - x86_pci_write_config8(irq_router.bdf, - LINK_N2V(link, base), irq); + if (priv->config == PIRQ_VIA_PCI) + dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq); else - writeb(irq, irq_router.ibase + LINK_N2V(link, base)); + writeb(irq, priv->ibase + LINK_N2V(link, base)); } static struct irq_info *check_dup_entry(struct irq_info *slot_base, @@ -74,46 +75,40 @@ static struct irq_info *check_dup_entry(struct irq_info *slot_base, return (i == entry_num) ? NULL : slot; } -static inline void fill_irq_info(struct irq_info *slot, int bus, int device, - int pin, int pirq) +static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot, + int bus, int device, int pin, int pirq) { slot->bus = bus; slot->devfn = (device << 3) | 0; - slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base); - slot->irq[pin - 1].bitmap = irq_router.irq_mask; + slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base); + slot->irq[pin - 1].bitmap = priv->irq_mask; } static int create_pirq_routing_table(struct udevice *dev) { + struct irq_router *priv = dev_get_priv(dev); const void *blob = gd->fdt_blob; - struct fdt_pci_addr addr; int node; int len, count; const u32 *cell; struct irq_routing_table *rt; struct irq_info *slot, *slot_base; int irq_entries = 0; - int parent; int i; int ret; node = dev->of_offset; - parent = dev->parent->of_offset; - ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG, - "reg", &addr); - if (ret) - return ret; /* extract the bdf from fdt_pci_addr */ - irq_router.bdf = addr.phys_hi & 0xffff00; + priv->bdf = dm_pci_get_bdf(dev->parent); ret = fdt_find_string(blob, node, "intel,pirq-config", "pci"); if (!ret) { - irq_router.config = PIRQ_VIA_PCI; + priv->config = PIRQ_VIA_PCI; } else { ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase"); if (!ret) - irq_router.config = PIRQ_VIA_IBASE; + priv->config = PIRQ_VIA_IBASE; else return -EINVAL; } @@ -121,12 +116,12 @@ static int create_pirq_routing_table(struct udevice *dev) ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1); if (ret == -1) return ret; - irq_router.link_base = ret; + priv->link_base = ret; - irq_router.irq_mask = fdtdec_get_int(blob, node, - "intel,pirq-mask", PIRQ_BITMAP); + priv->irq_mask = fdtdec_get_int(blob, node, + "intel,pirq-mask", PIRQ_BITMAP); - if (irq_router.config == PIRQ_VIA_IBASE) { + if (priv->config == PIRQ_VIA_IBASE) { int ibase_off; ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0); @@ -143,9 +138,8 @@ static int create_pirq_routing_table(struct udevice *dev) * 2) memory range decoding is enabled. * Hence we don't do any santify test here. */ - irq_router.ibase = x86_pci_read_config32(irq_router.bdf, - ibase_off); - irq_router.ibase &= ~0xf; + dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase); + priv->ibase &= ~0xf; } cell = fdt_getprop(blob, node, "intel,pirq-routing", &len); @@ -160,9 +154,8 @@ static int create_pirq_routing_table(struct udevice *dev) /* Populate the PIRQ table fields */ rt->signature = PIRQ_SIGNATURE; rt->version = PIRQ_VERSION; - rt->rtr_bus = PCI_BUS(irq_router.bdf); - rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) | - PCI_FUNC(irq_router.bdf); + rt->rtr_bus = PCI_BUS(priv->bdf); + rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf); rt->rtr_vendor = PCI_VENDOR_ID_INTEL; rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31; @@ -199,7 +192,7 @@ static int create_pirq_routing_table(struct udevice *dev) * routing information in the device tree. */ if (slot->irq[pr.pin - 1].link != - LINK_N2V(pr.pirq, irq_router.link_base)) + LINK_N2V(pr.pirq, priv->link_base)) debug("WARNING: Inconsistent PIRQ routing information\n"); continue; } @@ -207,8 +200,8 @@ static int create_pirq_routing_table(struct udevice *dev) slot = slot_base + irq_entries++; } debug("writing INT%c\n", 'A' + pr.pin - 1); - fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin, - pr.pirq); + fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), + pr.pin, pr.pirq); } rt->size = irq_entries * sizeof(struct irq_info) + 32; @@ -228,7 +221,7 @@ int irq_router_common_init(struct udevice *dev) return ret; } /* Route PIRQ */ - pirq_route_irqs(pirq_routing_table->slots, + pirq_route_irqs(dev, pirq_routing_table->slots, get_irq_slot_count(pirq_routing_table)); return 0; @@ -257,6 +250,7 @@ U_BOOT_DRIVER(irq_router_drv) = { .id = UCLASS_IRQ, .of_match = irq_router_ids, .probe = irq_router_probe, + .priv_auto_alloc_size = sizeof(struct irq_router), }; UCLASS_DRIVER(irq) = { diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 2b172d49ba..996707b7fe 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -19,6 +19,7 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h> +#define GPIO_BASE 0x48 #define BIOS_CTRL 0xdc static int pch_revision_id = -1; @@ -170,7 +171,7 @@ static int bd82x6x_probe(struct udevice *dev) return 0; } -static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) +static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep) { u32 rcba; @@ -182,11 +183,6 @@ static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) return 0; } -static enum pch_version bd82x6x_pch_get_version(struct udevice *dev) -{ - return PCHV_9; -} - static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) { uint8_t bios_cntl; @@ -205,10 +201,41 @@ static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) return 0; } +static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep) +{ + u32 base; + + /* + * GPIO_BASE moved to its current offset with ICH6, but prior to + * that it was unused (or undocumented). Check that it looks + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. + */ + dm_pci_read_config32(dev, GPIO_BASE, &base); + if (base == 0x00000000 || base == 0xffffffff) { + debug("%s: unexpected BASE value\n", __func__); + return -ENODEV; + } + + /* + * Okay, I guess we're looking at the right device. The actual + * GPIO registers are in the PCI device's I/O space, starting + * at the offset that we just read. Bit 0 indicates that it's + * an I/O address, not a memory address, so mask that off. + */ + *gbasep = base & 1 ? base & ~3 : base & ~15; + + return 0; +} + static const struct pch_ops bd82x6x_pch_ops = { - .get_sbase = bd82x6x_pch_get_sbase, - .get_version = bd82x6x_pch_get_version, + .get_spi_base = bd82x6x_pch_get_spi_base, .set_spi_protect = bd82x6x_set_spi_protect, + .get_gpio_base = bd82x6x_get_gpio_base, }; static const struct udevice_id bd82x6x_ids[] = { diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index 7a312602a0..c9c7637fa7 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -19,59 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct pci_controller *get_hose(void) -{ - if (gd->hose) - return gd->hose; - - return pci_bus_to_hose(0); -} - -unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where) -{ - uint8_t value; - - if (pci_hose_read_config_byte(get_hose(), dev, where, &value)) - return -1U; - - return value; -} - -unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where) -{ - uint16_t value; - - if (pci_hose_read_config_word(get_hose(), dev, where, &value)) - return -1U; - - return value; -} - -unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where) -{ - uint32_t value; - - if (pci_hose_read_config_dword(get_hose(), dev, where, &value)) - return -1U; - - return value; -} - -void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value) -{ - pci_hose_write_config_byte(get_hose(), dev, where, value); -} - -void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value) -{ - pci_hose_write_config_word(get_hose(), dev, where, value); -} - -void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value) -{ - pci_hose_write_config_dword(get_hose(), dev, where, value); -} - int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { @@ -119,11 +66,11 @@ void pci_assign_irqs(int bus, int device, u8 irq[4]) for (func = 0; func < 8; func++) { bdf = PCI_BDF(bus, device, func); - vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID); + pci_read_config16(bdf, PCI_VENDOR_ID, &vendor); if (vendor == 0xffff || vendor == 0x0000) continue; - pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN); + pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin); /* PCI spec says all values except 1..4 are reserved */ if ((pin < 1) || (pin > 4)) @@ -136,6 +83,6 @@ void pci_assign_irqs(int bus, int device, u8 irq[4]) debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", line, bus, device, func, 'A' + pin - 1); - x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); + pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); } } diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index f8af566dea..7ad0ee49a1 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -5,8 +5,8 @@ */ #include <common.h> +#include <pci.h> #include <asm/irq.h> -#include <asm/pci.h> #include <asm/post.h> #include <asm/processor.h> #include <asm/arch/device.h> @@ -21,23 +21,23 @@ static void enable_pm_piix(void) u16 cmd; /* Set the PM I/O base */ - x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); + pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); /* Enable access to the PM I/O space */ - cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND); + pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_IO; - x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); + pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); /* PM I/O Space Enable (PMIOSE) */ - en = x86_pci_read_config8(PIIX_PM, PMREGMISC); + pci_read_config8(PIIX_PM, PMREGMISC, &en); en |= PMIOSE; - x86_pci_write_config8(PIIX_PM, PMREGMISC, en); + pci_write_config8(PIIX_PM, PMREGMISC, en); } static void enable_pm_ich9(void) { /* Set the PM I/O base */ - x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); + pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); } static void qemu_chipset_init(void) @@ -50,7 +50,7 @@ static void qemu_chipset_init(void) * the same bitfield layout. Here we determine the offset based on its * PCI device ID. */ - device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); + pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device); i440fx = (device == PCI_DEVICE_ID_INTEL_82441); pam = i440fx ? I440FX_PAM : Q35_PAM; @@ -60,7 +60,7 @@ static void qemu_chipset_init(void) * Configure legacy segments C/D/E/F to system RAM */ for (i = 0; i < PAM_NUM; i++) - x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); + pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); if (i440fx) { /* @@ -71,19 +71,19 @@ static void qemu_chipset_init(void) * registers to see whether legacy ports decode is turned on. * This is to make Linux ata_piix driver happy. */ - x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); - x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); + pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); + pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); /* Enable I/O APIC */ - xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); + pci_read_config16(PIIX_ISA, XBCS, &xbcs); xbcs |= APIC_EN; - x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + pci_write_config16(PIIX_ISA, XBCS, xbcs); enable_pm_piix(); } else { /* Configure PCIe ECAM base address */ - x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, - CONFIG_PCIE_ECAM_BASE | BAR_EN); + pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, + CONFIG_PCIE_ECAM_BASE | BAR_EN); enable_pm_ich9(); } @@ -136,8 +136,8 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) * connected to I/O APIC INTPIN#16-19. Instead they are routed * to an irq number controled by the PIRQ routing register. */ - irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), - PCI_INTERRUPT_LINE); + pci_read_config8(PCI_BDF(bus, dev, func), + PCI_INTERRUPT_LINE, &irq); } else { /* * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index 49d803d794..fac2d72e0d 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -12,6 +12,7 @@ #include <asm/arch/device.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> +#include <asm/arch/quark.h> #include "mrc_util.h" #include "hte.h" #include "smc.h" @@ -106,8 +107,8 @@ void select_hte(void) */ void dram_init_command(uint32_t data) { - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data); - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0); msg_port_setup(MSG_OP_DRAM_INIT, MEM_CTLR, 0); DPF(D_REGWR, "WR32 %03X %08X %08X\n", MEM_CTLR, 0, data); diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 6e20930a4d..afb3463797 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -20,21 +20,6 @@ static struct pci_device_id mmc_supported[] = { {}, }; -/* - * TODO: - * - * This whole routine should be removed until we fully convert the ICH SPI - * driver to DM and make use of DT to pass the bios control register offset - */ -static void unprotect_spi_flash(void) -{ - u32 bc; - - qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); - bc |= 0x1; /* unprotect the flash */ - qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); -} - static void quark_setup_mtrr(void) { u32 base, mask; @@ -259,8 +244,6 @@ int arch_cpu_init(void) /* Turn on legacy segments (A/B/E/F) decode to system RAM */ quark_enable_legacy_seg(); - unprotect_spi_flash(); - return 0; } diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c index 44369f7ec7..63d0f35a29 100644 --- a/arch/x86/cpu/queensbay/irq.c +++ b/arch/x86/cpu/queensbay/irq.c @@ -18,7 +18,7 @@ int queensbay_irq_router_probe(struct udevice *dev) struct tnc_rcba *rcba; u32 base; - base = x86_pci_read_config32(TNC_LPC, LPC_RCBA); + dm_pci_read_config32(dev->parent, LPC_RCBA, &base); base &= ~MEM_BAR_EN; rcba = (struct tnc_rcba *)base; diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 75f7adb74c..b226e4c5fd 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -5,26 +5,34 @@ */ #include <common.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <pci.h> #include <asm/io.h> #include <asm/irq.h> -#include <asm/pci.h> #include <asm/post.h> #include <asm/arch/device.h> #include <asm/arch/tnc.h> #include <asm/fsp/fsp_support.h> #include <asm/processor.h> -static void unprotect_spi_flash(void) +static int __maybe_unused disable_igd(void) { - u32 bc; + struct udevice *igd, *sdvo; + int ret; - bc = x86_pci_read_config32(TNC_LPC, 0xd8); - bc |= 0x1; /* unprotect the flash */ - x86_pci_write_config32(TNC_LPC, 0xd8, bc); -} + ret = dm_pci_bus_find_bdf(TNC_IGD, &igd); + if (ret) + return ret; + if (!igd) + return 0; + + ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo); + if (ret) + return ret; + if (!sdvo) + return 0; -static void __maybe_unused disable_igd(void) -{ /* * According to Atom E6xx datasheet, setting VGA Disable (bit17) * of Graphics Controller register (offset 0x50) prevents IGD @@ -43,8 +51,45 @@ static void __maybe_unused disable_igd(void) * two devices will be completely disabled (invisible in the PCI * configuration space) unless a system reset is performed. */ - x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE); - x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE); + dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE); + dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE); + + /* + * After setting the function disable bit, IGD and SDVO devices will + * disappear in the PCI configuration space. This however creates an + * inconsistent state from a driver model PCI controller point of view, + * as these two PCI devices are still attached to its parent's child + * device list as maintained by the driver model. Some driver model PCI + * APIs like dm_pci_find_class(), are referring to the list to speed up + * the finding process instead of re-enumerating the whole PCI bus, so + * it gets the stale cached data which is wrong. + * + * Note x86 PCI enueration normally happens twice, in pre-relocation + * phase and post-relocation. One option might be to call disable_igd() + * in one of the pre-relocation initialization hooks so that it gets + * disabled in the first round, and when it comes to the second round + * driver model PCI will construct a correct list. Unfortunately this + * does not work as Intel FSP is used on this platform to perform low + * level initialization, and fsp_init_phase_pci() is called only once + * in the post-relocation phase. If we disable IGD and SDVO devices, + * fsp_init_phase_pci() simply hangs and never returns. + * + * So the only option we have is to manually remove these two devices. + */ + ret = device_remove(igd); + if (ret) + return ret; + ret = device_unbind(igd); + if (ret) + return ret; + ret = device_remove(sdvo); + if (ret) + return ret; + ret = device_unbind(sdvo); + if (ret) + return ret; + + return 0; } int arch_cpu_init(void) @@ -62,16 +107,11 @@ int arch_cpu_init(void) int arch_early_init_r(void) { + int ret = 0; + #ifdef CONFIG_DISABLE_IGD - disable_igd(); + ret = disable_igd(); #endif - return 0; -} - -int arch_misc_init(void) -{ - unprotect_spi_flash(); - - return 0; + return ret; } |