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-rw-r--r--arch/x86/cpu/acpi_gpe.c26
-rw-r--r--arch/x86/cpu/apollolake/cpu_spl.c13
-rw-r--r--arch/x86/cpu/apollolake/fsp_m.c18
-rw-r--r--arch/x86/cpu/apollolake/fsp_s.c66
-rw-r--r--arch/x86/cpu/baytrail/acpi.c6
-rw-r--r--arch/x86/cpu/broadwell/power_state.c5
-rw-r--r--arch/x86/cpu/coreboot/coreboot.c4
-rw-r--r--arch/x86/cpu/coreboot/tables.c8
-rw-r--r--arch/x86/cpu/cpu.c64
-rw-r--r--arch/x86/cpu/efi/app.c2
-rw-r--r--arch/x86/cpu/i386/cpu.c7
-rw-r--r--arch/x86/cpu/intel_common/itss.c25
-rw-r--r--arch/x86/cpu/intel_common/p2sb.c44
-rw-r--r--arch/x86/cpu/quark/acpi.c4
-rw-r--r--arch/x86/cpu/quark/quark.c2
-rw-r--r--arch/x86/cpu/start.S1
-rw-r--r--arch/x86/cpu/tangier/acpi.c4
17 files changed, 207 insertions, 92 deletions
diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c
index 8aa2009bd6..70badb15a3 100644
--- a/arch/x86/cpu/acpi_gpe.c
+++ b/arch/x86/cpu/acpi_gpe.c
@@ -8,7 +8,10 @@
#include <dm.h>
#include <irq.h>
#include <log.h>
+#include <acpi/acpi_device.h>
#include <asm/io.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/x86-irq.h>
/**
* struct acpi_gpe_priv - private driver information
@@ -62,13 +65,36 @@ static int acpi_gpe_ofdata_to_platdata(struct udevice *dev)
static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
{
irq->id = args->args[0];
+ irq->flags = args->args[1];
return 0;
}
+#if CONFIG_IS_ENABLED(ACPIGEN)
+static int acpi_gpe_get_acpi(const struct irq *irq, struct acpi_irq *acpi_irq)
+{
+ memset(acpi_irq, '\0', sizeof(*acpi_irq));
+ acpi_irq->pin = irq->id;
+ acpi_irq->mode = irq->flags & IRQ_TYPE_EDGE_BOTH ?
+ ACPI_IRQ_EDGE_TRIGGERED : ACPI_IRQ_LEVEL_TRIGGERED;
+ acpi_irq->polarity = irq->flags &
+ (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW) ?
+ ACPI_IRQ_ACTIVE_LOW : ACPI_IRQ_ACTIVE_HIGH;
+ acpi_irq->shared = irq->flags & X86_IRQ_TYPE_SHARED ?
+ ACPI_IRQ_SHARED : ACPI_IRQ_EXCLUSIVE;
+ acpi_irq->wake = irq->flags & X86_IRQ_TYPE_WAKE ? ACPI_IRQ_WAKE :
+ ACPI_IRQ_NO_WAKE;
+
+ return 0;
+}
+#endif
+
static const struct irq_ops acpi_gpe_ops = {
.read_and_clear = acpi_gpe_read_and_clear,
.of_xlate = acpi_gpe_of_xlate,
+#if CONFIG_IS_ENABLED(ACPIGEN)
+ .get_acpi = acpi_gpe_get_acpi,
+#endif
};
static const struct udevice_id acpi_gpe_ids[] = {
diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c
index 707ceb3e64..9f32f2e27e 100644
--- a/arch/x86/cpu/apollolake/cpu_spl.c
+++ b/arch/x86/cpu/apollolake/cpu_spl.c
@@ -247,12 +247,13 @@ static int arch_cpu_init_spl(void)
ret = pmc_init(pmc);
if (ret < 0)
return log_msg_ret("Could not init PMC", ret);
-#ifdef CONFIG_HAVE_ACPI_RESUME
- ret = pmc_prev_sleep_state(pmc);
- if (ret < 0)
- return log_msg_ret("Could not get PMC sleep state", ret);
- gd->arch.prev_sleep_state = ret;
-#endif
+ if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
+ ret = pmc_prev_sleep_state(pmc);
+ if (ret < 0)
+ return log_msg_ret("Could not get PMC sleep state",
+ ret);
+ gd->arch.prev_sleep_state = ret;
+ }
return 0;
}
diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c
index 1301100cd5..cef937573b 100644
--- a/arch/x86/cpu/apollolake/fsp_m.c
+++ b/arch/x86/cpu/apollolake/fsp_m.c
@@ -16,19 +16,29 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
{
struct fsp_m_config *cfg = &upd->config;
struct fspm_arch_upd *arch = &upd->arch;
+ int cache_ret = 0;
ofnode node;
+ int ret;
arch->nvs_buffer_ptr = NULL;
- prepare_mrc_cache(upd);
- arch->stack_base = (void *)0xfef96000;
+ cache_ret = prepare_mrc_cache(upd);
+ if (cache_ret && cache_ret != -ENOENT)
+ return log_msg_ret("mrc", cache_ret);
+ arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE -
+ arch->stack_size);
arch->boot_loader_tolum_size = 0;
- arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION;
+ arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION :
+ FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
node = dev_ofnode(dev);
if (!ofnode_valid(node))
return log_msg_ret("fsp-m settings", -ENOENT);
- return fsp_m_update_config_from_dtb(node, cfg);
+ ret = fsp_m_update_config_from_dtb(node, cfg);
+ if (ret)
+ return log_msg_ret("dtb", cache_ret);
+
+ return cache_ret;
}
/*
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 767ddfe680..e54b0ac104 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -12,6 +12,7 @@
#include <irq.h>
#include <log.h>
#include <malloc.h>
+#include <p2sb.h>
#include <acpi/acpi_s3.h>
#include <asm/intel_pinctrl.h>
#include <asm/io.h>
@@ -21,10 +22,11 @@
#include <asm/pci.h>
#include <asm/arch/cpu.h>
#include <asm/arch/systemagent.h>
+#include <asm/arch/fsp_bindings.h>
#include <asm/arch/fsp/fsp_configs.h>
#include <asm/arch/fsp/fsp_s_upd.h>
+#include <dm/uclass-internal.h>
#include <linux/bitops.h>
-#include <asm/arch/fsp_bindings.h>
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
@@ -36,29 +38,20 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,
ofnode node;
if (IS_ENABLED(CONFIG_HAVE_VBT)) {
- struct binman_entry vbt;
- void *vbt_buf;
+ void *buf;
int ret;
- ret = binman_entry_find("intel-vbt", &vbt);
+ ret = binman_entry_map(ofnode_null(), "intel-vbt", &buf, NULL);
if (ret)
return log_msg_ret("Cannot find VBT", ret);
- vbt.image_pos += rom_offset;
- vbt_buf = malloc(vbt.size);
- if (!vbt_buf)
- return log_msg_ret("Alloc VBT", -ENOMEM);
+ if (*(u32 *)buf != VBT_SIGNATURE)
+ return log_msg_ret("VBT signature", -EINVAL);
/*
* Load VBT before devicetree-specific config. This only
* supports memory-mapped SPI at present.
*/
- bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
- memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
- if (*(u32 *)vbt_buf != VBT_SIGNATURE)
- return log_msg_ret("VBT signature", -EINVAL);
-
- cfg->graphics_config_ptr = (ulong)vbt_buf;
+ cfg->graphics_config_ptr = (ulong)buf;
}
node = dev_read_subnode(dev, "fsp-s");
@@ -68,12 +61,6 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,
return fsp_s_update_config_from_dtb(node, cfg);
}
-static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
-{
- pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
- hide ? HIDE_BIT : 0, PCI_SIZE_8);
-}
-
/* Configure package power limits */
static int set_power_limits(struct udevice *dev)
{
@@ -146,15 +133,15 @@ static int set_power_limits(struct udevice *dev)
int p2sb_unhide(void)
{
- pci_dev_t dev = PCI_BDF(0, 0xd, 0);
- ulong val;
-
- p2sb_set_hide_bit(dev, 0);
-
- pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
+ struct udevice *dev;
+ int ret;
- if (val != PCI_VENDOR_ID_INTEL)
- return log_msg_ret("p2sb unhide", -EIO);
+ ret = uclass_find_first_device(UCLASS_P2SB, &dev);
+ if (ret)
+ return log_msg_ret("p2sb", ret);
+ ret = p2sb_set_hide(dev, false);
+ if (ret)
+ return log_msg_ret("hide", ret);
return 0;
}
@@ -173,11 +160,6 @@ int arch_fsps_preinit(void)
ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
if (ret)
return log_msg_ret("no itss", ret);
- /*
- * Snapshot the current GPIO IRQ polarities. FSP is setting a default
- * policy that doesn't honour boards' requirements
- */
- irq_snapshot_polarities(itss);
/*
* Clear the GPI interrupt status and enable registers. These
@@ -192,16 +174,16 @@ int arch_fsps_preinit(void)
int arch_fsp_init_r(void)
{
-#ifdef CONFIG_HAVE_ACPI_RESUME
- bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
-#else
- bool s3wake = false;
-#endif
+ bool s3wake;
struct udevice *dev, *itss;
int ret;
if (!ll_boot_init())
return 0;
+
+ s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
+ gd->arch.prev_sleep_state == ACPI_S3;
+
/*
* This must be called before any devices are probed. Put any probing
* into arch_fsps_preinit() above.
@@ -216,7 +198,11 @@ int arch_fsp_init_r(void)
ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
if (ret)
return log_msg_ret("no itss", ret);
- /* Restore GPIO IRQ polarities back to previous settings */
+
+ /*
+ * Restore GPIO IRQ polarities back to previous settings. This was
+ * stored in reserve_arch() - see X86_IRQT_ITSS
+ */
irq_restore_polarities(itss);
/* soc_init() */
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index 65f2006a0a..07757b88a3 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -139,7 +139,7 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
header->checksum = table_compute_checksum(fadt, header->length);
}
-void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
struct udevice *dev;
int ret;
@@ -159,9 +159,10 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
gnvs->iuart_en = 1;
else
gnvs->iuart_en = 0;
+
+ return 0;
}
-#ifdef CONFIG_HAVE_ACPI_RESUME
/*
* The following two routines are called at a very early stage, even before
* FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS
@@ -204,4 +205,3 @@ void chipset_clear_sleep_state(void)
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
}
-#endif
diff --git a/arch/x86/cpu/broadwell/power_state.c b/arch/x86/cpu/broadwell/power_state.c
index 99d6f72cf6..62fd2e8d2c 100644
--- a/arch/x86/cpu/broadwell/power_state.c
+++ b/arch/x86/cpu/broadwell/power_state.c
@@ -23,11 +23,10 @@ static int prev_sleep_state(struct chipset_power_state *ps)
if (ps->pm1_sts & WAK_STS) {
switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
-#if CONFIG_HAVE_ACPI_RESUME
case SLP_TYP_S3:
- prev_sleep_state = SLEEP_STATE_S3;
+ if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+ prev_sleep_state = SLEEP_STATE_S3;
break;
-#endif
case SLP_TYP_S5:
prev_sleep_state = SLEEP_STATE_S5;
break;
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index d44db1347b..22a93254a9 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -42,7 +42,7 @@ int print_cpuinfo(void)
return default_print_cpuinfo();
}
-static void board_final_cleanup(void)
+static void board_final_init(void)
{
/*
* Un-cache the ROM so the kernel has one
@@ -80,7 +80,7 @@ int last_stage_init(void)
if (CONFIG_IS_ENABLED(USB_KEYBOARD))
usb_init();
- board_final_cleanup();
+ board_final_init();
return 0;
}
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index a5d31d1dea..1594b4a8b2 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -10,6 +10,8 @@
#include <net.h>
#include <asm/arch/sysinfo.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* This needs to be in the .data section so that it's copied over during
* relocation. By default it's put in the .bss section which is simply filled
@@ -243,6 +245,10 @@ int get_coreboot_info(struct sysinfo_t *info)
if (addr < 0)
return addr;
ret = cb_parse_header((void *)addr, 0x1000, info);
+ if (!ret)
+ return -ENOENT;
+ gd->arch.coreboot_table = addr;
+ gd->flags |= GD_FLG_SKIP_LL_INIT;
- return ret == 1 ? 0 : -ENOENT;
+ return 0;
}
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index a814e7d7a6..98ed66e67d 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -25,6 +25,7 @@
#include <dm.h>
#include <errno.h>
#include <init.h>
+#include <irq.h>
#include <log.h>
#include <malloc.h>
#include <syscon.h>
@@ -163,10 +164,10 @@ int default_print_cpuinfo(void)
cpu_has_64bit() ? "x86_64" : "x86",
cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
-#ifdef CONFIG_HAVE_ACPI_RESUME
- debug("ACPI previous sleep state: %s\n",
- acpi_ss_string(gd->arch.prev_sleep_state));
-#endif
+ if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
+ debug("ACPI previous sleep state: %s\n",
+ acpi_ss_string(gd->arch.prev_sleep_state));
+ }
return 0;
}
@@ -178,10 +179,10 @@ void show_boot_progress(int val)
#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
/*
- * Implement a weak default function for boards that optionally
- * need to clean up the system before jumping to the kernel.
+ * Implement a weak default function for boards that need to do some final init
+ * before the system is ready.
*/
-__weak void board_final_cleanup(void)
+__weak void board_final_init(void)
{
}
@@ -189,14 +190,14 @@ int last_stage_init(void)
{
struct acpi_fadt __maybe_unused *fadt;
- board_final_cleanup();
+ board_final_init();
-#ifdef CONFIG_HAVE_ACPI_RESUME
- fadt = acpi_find_fadt();
+ if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
+ fadt = acpi_find_fadt();
- if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
- acpi_resume(fadt);
-#endif
+ if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
+ acpi_resume(fadt);
+ }
write_tables();
@@ -269,25 +270,36 @@ int cpu_init_r(void)
#ifndef CONFIG_EFI_STUB
int reserve_arch(void)
{
-#ifdef CONFIG_ENABLE_MRC_CACHE
- mrccache_reserve();
-#endif
+ struct udevice *itss;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
+ mrccache_reserve();
#ifdef CONFIG_SEABIOS
high_table_reserve();
#endif
-#ifdef CONFIG_HAVE_ACPI_RESUME
- acpi_s3_reserve();
+ if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
+ acpi_s3_reserve();
-#ifdef CONFIG_HAVE_FSP
- /*
- * Save stack address to CMOS so that at next S3 boot,
- * we can use it as the stack address for fsp_contiue()
- */
- fsp_save_s3_stack();
-#endif /* CONFIG_HAVE_FSP */
-#endif /* CONFIG_HAVE_ACPI_RESUME */
+ if (IS_ENABLED(CONFIG_HAVE_FSP)) {
+ /*
+ * Save stack address to CMOS so that at next S3 boot,
+ * we can use it as the stack address for fsp_contiue()
+ */
+ fsp_save_s3_stack();
+ }
+ }
+ ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
+ if (!ret) {
+ /*
+ * Snapshot the current GPIO IRQ polarities. FSP-S is about to
+ * run and will set a default policy that doesn't honour boards'
+ * requirements
+ */
+ irq_snapshot_polarities(itss);
+ }
return 0;
}
diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c
index 10677ecbc2..f754489784 100644
--- a/arch/x86/cpu/efi/app.c
+++ b/arch/x86/cpu/efi/app.c
@@ -24,7 +24,7 @@ int print_cpuinfo(void)
return default_print_cpuinfo();
}
-void board_final_cleanup(void)
+void board_final_init(void)
{
}
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index d27324cb4e..a6a6afec8c 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -455,10 +455,15 @@ int x86_cpu_init_f(void)
int x86_cpu_reinit_f(void)
{
+ long addr;
+
setup_identity();
setup_pci_ram_top();
- if (locate_coreboot_table() >= 0)
+ addr = locate_coreboot_table();
+ if (addr >= 0) {
+ gd->arch.coreboot_table = addr;
gd->flags |= GD_FLG_SKIP_LL_INIT;
+ }
return 0;
}
diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c
index 963afa8f5b..fe84ebe29f 100644
--- a/arch/x86/cpu/intel_common/itss.c
+++ b/arch/x86/cpu/intel_common/itss.c
@@ -65,14 +65,23 @@ static int snapshot_polarities(struct udevice *dev)
int i;
reg_start = start / IRQS_PER_IPC;
- reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
+ reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
+ log_info("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot);
for (i = reg_start; i < reg_end; i++) {
uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
priv->irq_snapshot[i] = pcr_read32(dev, reg);
+ log_debug(" - %d, reg %x: irq_snapshot[i] %x\n", i, reg,
+ priv->irq_snapshot[i]);
}
+ /* Save the snapshot for use after relocation */
+ gd->start_addr_sp -= sizeof(*priv);
+ gd->start_addr_sp &= ~0xf;
+ gd->arch.itss_priv = (void *)gd->start_addr_sp;
+ memcpy(gd->arch.itss_priv, priv, sizeof(*priv));
+
return 0;
}
@@ -91,16 +100,26 @@ static void show_polarities(struct udevice *dev, const char *msg)
static int restore_polarities(struct udevice *dev)
{
struct itss_priv *priv = dev_get_priv(dev);
+ struct itss_priv *old_priv;
const int start = GPIO_IRQ_START;
const int end = GPIO_IRQ_END;
int reg_start;
int reg_end;
int i;
+ /* Get the snapshot which was stored by the pre-reloc device */
+ old_priv = gd->arch.itss_priv;
+ if (!old_priv)
+ return log_msg_ret("priv", -EFAULT);
+ memcpy(priv->irq_snapshot, old_priv->irq_snapshot,
+ sizeof(priv->irq_snapshot));
+
show_polarities(dev, "Before");
+ log_info("priv->irq_snapshot %p\n", priv->irq_snapshot);
reg_start = start / IRQS_PER_IPC;
- reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
+ reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
+
for (i = reg_start; i < reg_end; i++) {
u32 mask;
@@ -125,6 +144,8 @@ static int restore_polarities(struct udevice *dev)
mask &= ~((1U << irq_start) - 1);
reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
+ log_debug(" - %d, reg %x: mask %x, irq_snapshot[i] %x\n",
+ i, reg, mask, priv->irq_snapshot[i]);
pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
}
diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c
index ec35d04ae5..361d4c90cb 100644
--- a/arch/x86/cpu/intel_common/p2sb.c
+++ b/arch/x86/cpu/intel_common/p2sb.c
@@ -16,6 +16,9 @@
#include <asm/pci.h>
#include <linux/bitops.h>
+#define PCH_P2SB_E0 0xe0
+#define HIDE_BIT BIT(0)
+
struct p2sb_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_p2sb dtplat;
@@ -127,6 +130,40 @@ static int p2sb_probe(struct udevice *dev)
return 0;
}
+static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
+{
+ dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
+ hide ? HIDE_BIT : 0);
+}
+
+static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
+{
+ u16 vendor;
+
+ if (!CONFIG_IS_ENABLED(PCI))
+ return -EPERM;
+ p2sb_set_hide_bit(dev, hide);
+
+ dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
+ if (hide && vendor != 0xffff)
+ return log_msg_ret("hide", -EEXIST);
+ else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
+ return log_msg_ret("unhide", -ENOMEDIUM);
+
+ return 0;
+}
+
+static int p2sb_remove(struct udevice *dev)
+{
+ int ret;
+
+ ret = intel_p2sb_set_hide(dev, true);
+ if (ret)
+ return log_msg_ret("hide", ret);
+
+ return 0;
+}
+
static int p2sb_child_post_bind(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
@@ -143,6 +180,10 @@ static int p2sb_child_post_bind(struct udevice *dev)
return 0;
}
+struct p2sb_ops p2sb_ops = {
+ .set_hide = intel_p2sb_set_hide,
+};
+
static const struct udevice_id p2sb_ids[] = {
{ .compatible = "intel,p2sb" },
{ }
@@ -153,9 +194,12 @@ U_BOOT_DRIVER(p2sb_drv) = {
.id = UCLASS_P2SB,
.of_match = p2sb_ids,
.probe = p2sb_probe,
+ .remove = p2sb_remove,
+ .ops = &p2sb_ops,
.ofdata_to_platdata = p2sb_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
.per_child_platdata_auto_alloc_size =
sizeof(struct p2sb_child_platdata),
.child_post_bind = p2sb_child_post_bind,
+ .flags = DM_FLAG_OS_PREPARE,
};
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
index 26cda3b337..b0406a04e9 100644
--- a/arch/x86/cpu/quark/acpi.c
+++ b/arch/x86/cpu/quark/acpi.c
@@ -133,8 +133,10 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
header->checksum = table_compute_checksum(fadt, header->length);
}
-void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
/* quark is a uni-processor */
gnvs->pcnt = 1;
+
+ return 0;
}
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index ddad02e375..30b4711b9a 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -363,7 +363,7 @@ int arch_misc_init(void)
return 0;
}
-void board_final_cleanup(void)
+void board_final_init(void)
{
struct quark_rcba *rcba;
u32 base, val;
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 01524635e9..4ad515ce08 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -124,6 +124,7 @@ car_init_ret:
#endif
#else
/*
+ * Instructions for FSP1, but not FSP2:
* U-Boot enters here twice. For the first time it comes from
* car_init_done() with esp points to a temporary stack and esi
* set to zero. For the second time it comes from fsp_init_done()
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
index 4ec8fdd6f8..41bd177e09 100644
--- a/arch/x86/cpu/tangier/acpi.c
+++ b/arch/x86/cpu/tangier/acpi.c
@@ -107,7 +107,7 @@ u32 acpi_fill_csrt(u32 current)
return current;
}
-void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
struct udevice *dev;
int ret;
@@ -122,4 +122,6 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
if (ret > 0)
gnvs->pcnt = ret;
}
+
+ return 0;
}
generated by cgit (git 2.34.1) at 2025-01-08 11:03:01 +0000