diff options
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/baytrail/Kconfig | 11 | ||||
| -rw-r--r-- | arch/x86/cpu/baytrail/acpi.c | 26 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/lpc.c | 6 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/sdram.c | 5 | ||||
| -rw-r--r-- | arch/x86/cpu/quark/acpi.c | 7 |
5 files changed, 49 insertions, 6 deletions
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index 407feb214b..1c8ac370b3 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -7,3 +7,14 @@ config INTEL_BAYTRAIL bool select HAVE_FSP if !EFI + +if INTEL_BAYTRAIL +config INTERNAL_UART + bool "Enable the SoC integrated legacy UART" + help + There is a legacy UART integrated into the Bay Trail SoC. + A maximum baud rate of 115200 bps is supported. For this + reason, it is recommended that the UART port be used for + debug purposes only, eg: U-Boot console. + +endif diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 5ee4868cf8..fa92d8852e 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -5,10 +5,14 @@ */ #include <common.h> +#include <cpu.h> +#include <dm.h> +#include <dm/uclass-internal.h> #include <asm/acpi_table.h> #include <asm/ioapic.h> #include <asm/mpspec.h> #include <asm/tables.h> +#include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, @@ -161,3 +165,25 @@ u32 acpi_fill_madt(u32 current) return current; } + +void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + struct udevice *dev; + int ret; + + /* at least we have one processor */ + gnvs->pcnt = 1; + /* override the processor count with actual number */ + ret = uclass_find_first_device(UCLASS_CPU, &dev); + if (ret == 0 && dev != NULL) { + ret = cpu_get_count(dev); + if (ret > 0) + gnvs->pcnt = ret; + } + + /* determine whether internal uart is on */ + if (IS_ENABLED(CONFIG_INTERNAL_UART)) + gnvs->iuart_en = 1; + else + gnvs->iuart_en = 0; +} diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index ff1faa5014..4e0be2a88b 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -424,8 +424,6 @@ static void set_spi_speed(void) static int lpc_init_extra(struct udevice *dev) { struct udevice *pch = dev->parent; - const void *blob = gd->fdt_blob; - int node; debug("pch: lpc_init\n"); dm_pci_write_bar32(pch, 0, 0); @@ -434,10 +432,6 @@ static int lpc_init_extra(struct udevice *dev) dm_pci_write_bar32(pch, 3, 0x800); dm_pci_write_bar32(pch, 4, 0x900); - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); - if (node < 0) - return -ENOENT; - /* Set the value for PCI command register. */ dm_pci_write_config16(pch, PCI_COMMAND, 0x000f); diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 9d9f63d70c..e0b06b5ada 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -458,6 +458,11 @@ int dram_init(void) struct udevice *dev, *me_dev; int ret; + /* We need the pinctrl set up early */ + ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); + if (ret) + return ret; + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); if (ret) return ret; diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 8f69829608..3968f7a8bf 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -9,6 +9,7 @@ #include <asm/ioapic.h> #include <asm/mpspec.h> #include <asm/tables.h> +#include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, @@ -161,3 +162,9 @@ u32 acpi_fill_madt(u32 current) return current; } + +void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + /* quark is a uni-processor */ + gnvs->pcnt = 1; +} |