diff options
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/broadwell/Makefile | 1 | ||||
| -rw-r--r-- | arch/x86/cpu/broadwell/adsp.c | 156 | ||||
| -rw-r--r-- | arch/x86/cpu/broadwell/pch.c | 110 | ||||
| -rw-r--r-- | arch/x86/cpu/broadwell/pinctrl_broadwell.c | 3 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/Kconfig | 1 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/bd82x6x.c | 27 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/northbridge.c | 32 |
7 files changed, 327 insertions, 3 deletions
diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile index a032861e57..d3785aabdf 100644 --- a/arch/x86/cpu/broadwell/Makefile +++ b/arch/x86/cpu/broadwell/Makefile @@ -2,6 +2,7 @@ # # Copyright (c) 2016 Google, Inc +obj-y += adsp.o obj-y += cpu.o obj-y += iobp.o obj-y += lpc.o diff --git a/arch/x86/cpu/broadwell/adsp.c b/arch/x86/cpu/broadwell/adsp.c new file mode 100644 index 0000000000..2ac8cea7c3 --- /dev/null +++ b/arch/x86/cpu/broadwell/adsp.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Application Digital Signal Processor + * + * Copyright 2019 Google LLC + * + * Modified from coreboot file of the same name + */ + +#define LOG_CATEGORY UCLASS_SYSCON + +#include <common.h> +#include <dm.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/cpu.h> +#include <asm/intel_regs.h> +#include <asm/arch/adsp.h> +#include <asm/arch/pch.h> +#include <asm/arch/rcb.h> + +enum pci_type_t { + LYNX_POINT, + WILDCAT_POINT, +}; + +struct broadwell_adsp_priv { + bool adsp_d3_pg_enable; + bool adsp_sram_pg_enable; + bool sio_acpi_mode; +}; + +static int broadwell_adsp_probe(struct udevice *dev) +{ + struct broadwell_adsp_priv *priv = dev_get_priv(dev); + enum pci_type_t type; + u32 bar0, bar1; + u32 tmp32; + + /* Find BAR0 and BAR1 */ + bar0 = dm_pci_read_bar32(dev, 0); + if (!bar0) + return -EINVAL; + bar1 = dm_pci_read_bar32(dev, 1); + if (!bar1) + return -EINVAL; + + /* + * Set LTR value in DSP shim LTR control register to 3ms + * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h + */ + type = dev_get_driver_data(dev); + tmp32 = type == WILDCAT_POINT ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT; + writel(ADSP_SHIM_LTRC_VALUE, bar0 + tmp32); + + /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */ + dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE); + + /* Program ADSP IOBP VDLDAT1 to 0x040100 */ + pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE); + + /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */ + dm_pci_read_config32(dev, ADSP_PCI_VDRTCTL0, &tmp32); + if (type == WILDCAT_POINT) { + if (priv->adsp_d3_pg_enable) { + tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; + if (priv->adsp_sram_pg_enable) + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; + else + tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT; + } else { + tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT; + } + } else { + if (priv->adsp_d3_pg_enable) { + tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT; + if (priv->adsp_sram_pg_enable) + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; + else + tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT; + } else { + tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT; + } + } + dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); + + /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */ + setbits_le32(RCB_REG(0x3350), 1 << 10); + + /* Set DSP IOBP PMCTL 0x1e0=0x3f */ + pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE); + + if (priv->sio_acpi_mode) { + /* Configure for ACPI mode */ + log_info("ADSP: Enable ACPI Mode IRQ3\n"); + + /* Set interrupt de-assert/assert opcode override to IRQ3 */ + pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3); + + /* Enable IRQ3 in RCBA */ + setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN); + + /* Set ACPI Interrupt Enable Bit */ + pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD, + ADSP_PCICFGCTL_ACPIIE); + + /* Put ADSP in D3hot */ + clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT); + } else { + log_info("ADSP: Enable PCI Mode IRQ23\n"); + + /* Configure for PCI mode */ + dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); + + /* Clear ACPI Interrupt Enable Bit */ + pch_iobp_update(ADSP_IOBP_PCICFGCTL, + ~(ADSP_PCICFGCTL_SPCBAD | + ADSP_PCICFGCTL_ACPIIE), 0); + } + + return 0; +} + +static int broadwell_adsp_ofdata_to_platdata(struct udevice *dev) +{ + struct broadwell_adsp_priv *priv = dev_get_priv(dev); + + priv->adsp_d3_pg_enable = dev_read_bool(dev, "intel,adsp-d3-pg-enable"); + priv->adsp_sram_pg_enable = dev_read_bool(dev, + "intel,adsp-sram-pg-enable"); + priv->sio_acpi_mode = dev_read_bool(dev, "intel,sio-acpi-mode"); + + return 0; +} + +static const struct udevice_id broadwell_adsp_ids[] = { + { .compatible = "intel,wildcatpoint-adsp", .data = WILDCAT_POINT }, + { } +}; + +U_BOOT_DRIVER(broadwell_adsp_drv) = { + .name = "adsp", + .id = UCLASS_SYSCON, + .ofdata_to_platdata = broadwell_adsp_ofdata_to_platdata, + .of_match = broadwell_adsp_ids, + .bind = dm_scan_fdt_dev, + .probe = broadwell_adsp_probe, +}; + +static struct pci_device_id broadwell_adsp_supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP) }, + { }, +}; + +U_BOOT_PCI_DEVICE(broadwell_adsp_drv, broadwell_adsp_supported); diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c index 82506ba35e..73d3d3b515 100644 --- a/arch/x86/cpu/broadwell/pch.c +++ b/arch/x86/cpu/broadwell/pch.c @@ -20,7 +20,9 @@ #include <asm/arch/pch.h> #include <asm/arch/pm.h> #include <asm/arch/rcb.h> +#include <asm/arch/serialio.h> #include <asm/arch/spi.h> +#include <dm/uclass-internal.h> #define BIOS_CTRL 0xdc @@ -456,6 +458,111 @@ static void systemagent_init(void) cpu_set_power_limits(28); } +/* Enable LTR Auto Mode for D21:F1-F6 */ +static void serialio_d21_ltr(u32 bar0) +{ + /* 1. Program BAR0 + 808h[2] = 0b */ + clrbits_le32(bar0 + SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_LTR_MODE_MASK); + + /* 2. Program BAR0 + 804h[1:0] = 00b */ + clrbits_le32(bar0 + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT); + + /* 3. Program BAR0 + 804h[1:0] = 11b */ + setbits_le32(bar0 + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT); + + /* 4. Program BAR0 + 814h[31:0] = 00000000h */ + writel(0, bar0 + SIO_REG_AUTO_LTR); +} + +/* Select I2C voltage of 1.8V or 3.3V */ +static void serialio_i2c_voltage_sel(u32 bar0, uint voltage) +{ + clrsetbits_le32(bar0 + SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_VOLTAGE_MASK, + SIO_REG_PPR_GEN_VOLTAGE(voltage)); +} + +/* Put Serial IO D21:F0-F6 device into desired mode */ +static void serialio_d21_mode(int sio_index, int int_pin, bool acpi_mode) +{ + u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT; + + /* Snoop select 1 */ + portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1); + + /* Set interrupt pin */ + portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin); + + if (acpi_mode) { + /* Enable ACPI interrupt mode */ + portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN; + } + + pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl); +} + +/* Init sequence to be run once, done as part of D21:F0 (SDMA) init */ +static void serialio_init_once(bool acpi_mode) +{ + if (acpi_mode) { + /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA */ + setbits_le32(RCB_REG(ACPIIRQEN), + 1 << 13 | 1 << 7 | 1 << 6 | 1 << 5); + } + + /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ + pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f); + + /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ + pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); +} + +/** + * pch_serialio_init() - set up serial I/O devices + * + * @return 0 if OK, -ve on error + */ +static int pch_serialio_init(void) +{ + struct udevice *dev, *hda; + bool acpi_mode = true; + u32 bar0, bar1; + int ret; + + ret = uclass_find_first_device(UCLASS_I2C, &dev); + if (ret) + return ret; + bar0 = dm_pci_read_bar32(dev, 0); + if (!bar0) + return -EINVAL; + bar1 = dm_pci_read_bar32(dev, 1); + if (!bar1) + return -EINVAL; + + serialio_init_once(acpi_mode); + serialio_d21_mode(SIO_ID_SDMA, SIO_PIN_INTB, acpi_mode); + + serialio_d21_ltr(bar0); + serialio_i2c_voltage_sel(bar0, 1); /* Select 1.8V always */ + serialio_d21_mode(SIO_ID_I2C0, SIO_PIN_INTC, acpi_mode); + setbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT); + + clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT); + + setbits_le32(bar0 + SIO_REG_PPR_CLOCK, SIO_REG_PPR_CLOCK_EN); + + /* Manually find the High-definition audio, to turn it off */ + ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1b, 0), &hda); + if (ret) + return -ENOENT; + dm_pci_clrset_config8(hda, 0x43, 0, 0x6f); + + /* Route I/O buffers to ADSP function */ + dm_pci_clrset_config8(hda, 0x42, 0, 1 << 7 | 1 << 6); + log_debug("HDA disabled, I/O buffers routed to ADSP\n"); + + return 0; +} + static int broadwell_pch_init(struct udevice *dev) { int ret; @@ -482,6 +589,9 @@ static int broadwell_pch_init(struct udevice *dev) return ret; pch_pm_init(dev); pch_cg_init(dev); + ret = pch_serialio_init(); + if (ret) + return ret; systemagent_init(); return 0; diff --git a/arch/x86/cpu/broadwell/pinctrl_broadwell.c b/arch/x86/cpu/broadwell/pinctrl_broadwell.c index 914ecfb314..aa83abbf85 100644 --- a/arch/x86/cpu/broadwell/pinctrl_broadwell.c +++ b/arch/x86/cpu/broadwell/pinctrl_broadwell.c @@ -16,6 +16,7 @@ #include <asm/arch/gpio.h> #include <dt-bindings/gpio/x86-gpio.h> #include <dm/pinctrl.h> +#include <dm/uclass-internal.h> DECLARE_GLOBAL_DATA_PTR; @@ -214,7 +215,7 @@ static int broadwell_pinctrl_probe(struct udevice *dev) u32 gpiobase; int ret; - ret = uclass_first_device(UCLASS_PCH, &pch); + ret = uclass_find_first_device(UCLASS_PCH, &pch); if (ret) return ret; if (!pch) diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 5f0e60837c..2f42393786 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE imply USB_EHCI_HCD imply USB_XHCI_HCD imply VIDEO_VESA + imply SOUND_IVYBRIDGE if NORTHBRIDGE_INTEL_IVYBRIDGE diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index a78bb02544..ed9bce6416 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -20,8 +20,12 @@ DECLARE_GLOBAL_DATA_PTR; -#define GPIO_BASE 0x48 -#define BIOS_CTRL 0xdc +#define GPIO_BASE 0x48 +#define BIOS_CTRL 0xdc + +#define RCBA_AUDIO_CONFIG 0x2030 +#define RCBA_AUDIO_CONFIG_HDA BIT(31) +#define RCBA_AUDIO_CONFIG_MASK 0xfe #ifndef CONFIG_HAVE_FSP static int pch_revision_id = -1; @@ -212,10 +216,29 @@ static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep) return 0; } +static int bd82x6x_ioctl(struct udevice *dev, enum pch_req_t req, void *data, + int size) +{ + u32 rcba, val; + + switch (req) { + case PCH_REQ_HDA_CONFIG: + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + val = readl(rcba + RCBA_AUDIO_CONFIG); + if (!(val & RCBA_AUDIO_CONFIG_HDA)) + return -ENOENT; + + return val & RCBA_AUDIO_CONFIG_MASK; + default: + return -ENOSYS; + } +} + static const struct pch_ops bd82x6x_pch_ops = { .get_spi_base = bd82x6x_pch_get_spi_base, .set_spi_protect = bd82x6x_set_spi_protect, .get_gpio_base = bd82x6x_get_gpio_base, + .ioctl = bd82x6x_ioctl, }; static const struct udevice_id bd82x6x_ids[] = { diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 39bab7bdf3..a809b823b3 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -177,6 +177,35 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev) dm_pci_write_config8(dev, PAM6, 0x33); } +/** + * sandybridge_init_iommu() - Set up IOMMU so that azalia can be used + * + * It is not obvious where these values come from. They may be undocumented. + */ +static void sandybridge_init_iommu(struct udevice *dev) +{ + u32 capid0_a; + + dm_pci_read_config32(dev, 0xe4, &capid0_a); + if (capid0_a & (1 << 23)) { + log_debug("capid0_a not needed\n"); + return; + } + + /* setup BARs */ + writel(IOMMU_BASE1 >> 32, MCHBAR_REG(0x5404)); + writel(IOMMU_BASE1 | 1, MCHBAR_REG(0x5400)); + writel(IOMMU_BASE2 >> 32, MCHBAR_REG(0x5414)); + writel(IOMMU_BASE2 | 1, MCHBAR_REG(0x5410)); + + /* lock policies */ + writel(0x80000000, IOMMU_BASE1 + 0xff0); + + /* Enable azalia sound */ + writel(0x20000000, IOMMU_BASE2 + 0xff0); + writel(0xa0000000, IOMMU_BASE2 + 0xff0); +} + static int bd82x6x_northbridge_early_init(struct udevice *dev) { const int chipset_type = SANDYBRIDGE_MOBILE; @@ -197,6 +226,9 @@ static int bd82x6x_northbridge_early_init(struct udevice *dev) sandybridge_setup_northbridge_bars(dev); + /* Setup IOMMU BARs */ + sandybridge_init_iommu(dev); + /* Device Enable */ dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); |