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-rw-r--r--arch/x86/dts/bayleybay.dts160
-rw-r--r--arch/x86/dts/broadwell_som-6896.dts24
-rw-r--r--arch/x86/dts/chromebook_link.dts91
-rw-r--r--arch/x86/dts/chromebox_panther.dts34
-rw-r--r--arch/x86/dts/crownbay.dts150
-rw-r--r--arch/x86/dts/galileo.dts99
-rw-r--r--arch/x86/dts/minnowmax.dts158
-rw-r--r--arch/x86/dts/qemu-x86_i440fx.dts26
-rw-r--r--arch/x86/dts/qemu-x86_q35.dts38
9 files changed, 448 insertions, 332 deletions
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index d3380dee6c..9bf707bf0e 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,23 +65,6 @@
};
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64dw", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x006e0000 0x00010000>;
- };
- };
- };
-
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
@@ -133,66 +116,91 @@
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "ibase";
- intel,ibase-offset = <0x50>;
- intel,pirq-link = <8 8>;
- intel,pirq-mask = <0xdee0>;
- intel,pirq-routing = <
- /* BayTrail PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQA
- PCI_BDF(0, 3, 0) INTA PIRQA
- PCI_BDF(0, 16, 0) INTA PIRQA
- PCI_BDF(0, 17, 0) INTA PIRQA
- PCI_BDF(0, 18, 0) INTA PIRQA
- PCI_BDF(0, 19, 0) INTA PIRQA
- PCI_BDF(0, 20, 0) INTA PIRQA
- PCI_BDF(0, 21, 0) INTA PIRQA
- PCI_BDF(0, 22, 0) INTA PIRQA
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 24, 0) INTA PIRQA
- PCI_BDF(0, 24, 1) INTC PIRQC
- PCI_BDF(0, 24, 2) INTD PIRQD
- PCI_BDF(0, 24, 3) INTB PIRQB
- PCI_BDF(0, 24, 4) INTA PIRQA
- PCI_BDF(0, 24, 5) INTC PIRQC
- PCI_BDF(0, 24, 6) INTD PIRQD
- PCI_BDF(0, 24, 7) INTB PIRQB
- PCI_BDF(0, 26, 0) INTA PIRQA
- PCI_BDF(0, 27, 0) INTA PIRQA
- PCI_BDF(0, 28, 0) INTA PIRQA
- PCI_BDF(0, 28, 1) INTB PIRQB
- PCI_BDF(0, 28, 2) INTC PIRQC
- PCI_BDF(0, 28, 3) INTD PIRQD
- PCI_BDF(0, 29, 0) INTA PIRQA
- PCI_BDF(0, 30, 0) INTA PIRQA
- PCI_BDF(0, 30, 1) INTD PIRQD
- PCI_BDF(0, 30, 2) INTB PIRQB
- PCI_BDF(0, 30, 3) INTC PIRQC
- PCI_BDF(0, 30, 4) INTD PIRQD
- PCI_BDF(0, 30, 5) INTB PIRQB
- PCI_BDF(0, 31, 3) INTB PIRQB
-
- /* PCIe root ports downstream interrupts */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(1, 0, 0) INTB PIRQB
- PCI_BDF(1, 0, 0) INTC PIRQC
- PCI_BDF(1, 0, 0) INTD PIRQD
- PCI_BDF(2, 0, 0) INTA PIRQB
- PCI_BDF(2, 0, 0) INTB PIRQC
- PCI_BDF(2, 0, 0) INTC PIRQD
- PCI_BDF(2, 0, 0) INTD PIRQA
- PCI_BDF(3, 0, 0) INTA PIRQC
- PCI_BDF(3, 0, 0) INTB PIRQD
- PCI_BDF(3, 0, 0) INTC PIRQA
- PCI_BDF(3, 0, 0) INTD PIRQB
- PCI_BDF(4, 0, 0) INTA PIRQD
- PCI_BDF(4, 0, 0) INTB PIRQA
- PCI_BDF(4, 0, 0) INTC PIRQB
- PCI_BDF(4, 0, 0) INTD PIRQC
- >;
+ compatible = "intel,pch9";
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /* BayTrail PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ PCI_BDF(0, 3, 0) INTA PIRQA
+ PCI_BDF(0, 16, 0) INTA PIRQA
+ PCI_BDF(0, 17, 0) INTA PIRQA
+ PCI_BDF(0, 18, 0) INTA PIRQA
+ PCI_BDF(0, 19, 0) INTA PIRQA
+ PCI_BDF(0, 20, 0) INTA PIRQA
+ PCI_BDF(0, 21, 0) INTA PIRQA
+ PCI_BDF(0, 22, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 24, 0) INTA PIRQA
+ PCI_BDF(0, 24, 1) INTC PIRQC
+ PCI_BDF(0, 24, 2) INTD PIRQD
+ PCI_BDF(0, 24, 3) INTB PIRQB
+ PCI_BDF(0, 24, 4) INTA PIRQA
+ PCI_BDF(0, 24, 5) INTC PIRQC
+ PCI_BDF(0, 24, 6) INTD PIRQD
+ PCI_BDF(0, 24, 7) INTB PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQA
+ PCI_BDF(0, 27, 0) INTA PIRQA
+ PCI_BDF(0, 28, 0) INTA PIRQA
+ PCI_BDF(0, 28, 1) INTB PIRQB
+ PCI_BDF(0, 28, 2) INTC PIRQC
+ PCI_BDF(0, 28, 3) INTD PIRQD
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 30, 0) INTA PIRQA
+ PCI_BDF(0, 30, 1) INTD PIRQD
+ PCI_BDF(0, 30, 2) INTB PIRQB
+ PCI_BDF(0, 30, 3) INTC PIRQC
+ PCI_BDF(0, 30, 4) INTD PIRQD
+ PCI_BDF(0, 30, 5) INTB PIRQB
+ PCI_BDF(0, 31, 3) INTB PIRQB
+
+ /*
+ * PCIe root ports downstream
+ * interrupts
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ PCI_BDF(3, 0, 0) INTA PIRQC
+ PCI_BDF(3, 0, 0) INTB PIRQD
+ PCI_BDF(3, 0, 0) INTC PIRQA
+ PCI_BDF(3, 0, 0) INTD PIRQB
+ PCI_BDF(4, 0, 0) INTA PIRQD
+ PCI_BDF(4, 0, 0) INTB PIRQA
+ PCI_BDF(4, 0, 0) INTC PIRQB
+ PCI_BDF(4, 0, 0) INTD PIRQC
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64dw",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x006e0000 0x00010000>;
+ };
+ };
+ };
};
};
diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
index 194f0ebcda..4e9e410b70 100644
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ b/arch/x86/dts/broadwell_som-6896.dts
@@ -29,16 +29,22 @@
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- };
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- reg = <0>;
- compatible = "winbond,w25q128", "spi-flash";
- memory-map = <0xff000000 0x01000000>;
+ pch@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,pch9";
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "winbond,w25q128", "spi-flash";
+ memory-map = <0xff000000 0x01000000>;
+ };
+ };
};
};
+
};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index c4469a9768..d148d6e349 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -12,12 +12,48 @@
aliases {
spi0 = "/pci/pch/spi";
+ usb0 = &usb_0;
+ usb1 = &usb_1;
};
config {
silent_console = <0>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,core-gen3";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "intel,core-gen3";
+ reg = <1>;
+ intel,apic-id = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "intel,core-gen3";
+ reg = <2>;
+ intel,apic-id = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "intel,core-gen3";
+ reg = <3>;
+ intel,apic-id = <3>;
+ };
+
+ };
+
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
@@ -159,21 +195,22 @@
};
pci {
- compatible = "intel,pci-ivybridge", "pci-x86";
+ compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
- sata {
- compatible = "intel,pantherpoint-ahci";
- intel,sata-mode = "ahci";
- intel,sata-port-map = <1>;
- intel,sata-port0-gen3-tx = <0x00880a7f>;
+
+ northbridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ compatible = "intel,bd82x6x-northbridge";
+ u-boot,dm-pre-reloc;
};
- gma {
+ gma@2,0 {
+ reg = <0x00001000 0 0 0 0>;
compatible = "intel,gma";
intel,dp_hotplug = <0 0 0x06>;
intel,panel-port-select = <1>;
@@ -186,20 +223,35 @@
intel,pch-backlight = <0x04000000>;
};
- pch {
+ me@16,0 {
+ reg = <0x0000b000 0 0 0 0>;
+ compatible = "intel,me";
+ u-boot,dm-pre-reloc;
+ };
+
+ usb_1: usb@1a,0 {
+ reg = <0x0000d000 0 0 0 0>;
+ compatible = "ehci-pci";
+ };
+
+ usb_0: usb@1d,0 {
+ reg = <0x0000e800 0 0 0 0>;
+ compatible = "ehci-pci";
+ };
+
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,bd82x6x", "intel,pch";
+ compatible = "intel,bd82x6x", "intel,pch9";
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
- intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
0x80 0x80 0x80 0x80>;
intel,gpi-routing = <0 0 0 0 0 0 0 2
1 0 0 0 0 0 0 0>;
/* Enable EC SMI source */
intel,alt-gp-smi-enable = <0x0100>;
+
spi {
#address-cells = <1>;
#size-cells = <0>;
@@ -222,6 +274,8 @@
compatible = "intel,bd82x6x-lpc";
#address-cells = <1>;
#size-cells = <0>;
+ u-boot,dm-pre-reloc;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
@@ -239,6 +293,21 @@
};
};
};
+
+ sata@1f,2 {
+ compatible = "intel,pantherpoint-ahci";
+ reg = <0x0000fa00 0 0 0 0>;
+ u-boot,dm-pre-reloc;
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+ };
+
+ smbus: smbus@1f,3 {
+ compatible = "intel,ich-i2c";
+ reg = <0x0000fb00 0 0 0 0>;
+ u-boot,dm-pre-reloc;
+ };
};
tpm {
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 4e2b51708b..23027016e5 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -51,21 +51,27 @@
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xf000>;
- };
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #size-cells = <1>;
- #address-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x003e0000 0x00010000>;
+ pch@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,pch9";
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x003e0000 0x00010000>;
+ };
+ };
};
};
};
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 84231b3778..d6dd0b49f0 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -72,17 +72,6 @@
stdout-path = "/serial";
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- reg = <0>;
- compatible = "sst,25vf016b", "spi-flash";
- memory-map = <0xffe00000 0x00200000>;
- };
- };
-
microcode {
update@0 {
#include "microcode/m0220661105_cv.dtsi"
@@ -170,68 +159,85 @@
};
};
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 8>;
- intel,pirq-mask = <0xcee0>;
- intel,pirq-routing = <
- /* TunnelCreek PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQE
- PCI_BDF(0, 3, 0) INTA PIRQF
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 23, 0) INTB PIRQB
- PCI_BDF(0, 23, 0) INTC PIRQC
- PCI_BDF(0, 23, 0) INTD PIRQD
- PCI_BDF(0, 24, 0) INTA PIRQB
- PCI_BDF(0, 24, 0) INTB PIRQC
- PCI_BDF(0, 24, 0) INTC PIRQD
- PCI_BDF(0, 24, 0) INTD PIRQA
- PCI_BDF(0, 25, 0) INTA PIRQC
- PCI_BDF(0, 25, 0) INTB PIRQD
- PCI_BDF(0, 25, 0) INTC PIRQA
- PCI_BDF(0, 25, 0) INTD PIRQB
- PCI_BDF(0, 26, 0) INTA PIRQD
- PCI_BDF(0, 26, 0) INTB PIRQA
- PCI_BDF(0, 26, 0) INTC PIRQB
- PCI_BDF(0, 26, 0) INTD PIRQC
- PCI_BDF(0, 27, 0) INTA PIRQG
- /*
- * Topcliff PCI devices
- *
- * Note on the Crown Bay board, Topcliff chipset
- * is connected to TunnelCreek PCIe port 0, so
- * its bus number is 1 for its PCIe port and 2
- * for its PCI devices per U-Boot current PCI
- * bus enumeration algorithm.
- */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(2, 0, 1) INTA PIRQA
- PCI_BDF(2, 0, 2) INTA PIRQA
- PCI_BDF(2, 2, 0) INTB PIRQD
- PCI_BDF(2, 2, 1) INTB PIRQD
- PCI_BDF(2, 2, 2) INTB PIRQD
- PCI_BDF(2, 2, 3) INTB PIRQD
- PCI_BDF(2, 2, 4) INTB PIRQD
- PCI_BDF(2, 4, 0) INTC PIRQC
- PCI_BDF(2, 4, 1) INTC PIRQC
- PCI_BDF(2, 6, 0) INTD PIRQB
- PCI_BDF(2, 8, 0) INTA PIRQA
- PCI_BDF(2, 8, 1) INTA PIRQA
- PCI_BDF(2, 8, 2) INTA PIRQA
- PCI_BDF(2, 8, 3) INTA PIRQA
- PCI_BDF(2, 10, 0) INTB PIRQD
- PCI_BDF(2, 10, 1) INTB PIRQD
- PCI_BDF(2, 10, 2) INTB PIRQD
- PCI_BDF(2, 10, 3) INTB PIRQD
- PCI_BDF(2, 10, 4) INTB PIRQD
- PCI_BDF(2, 12, 0) INTC PIRQC
- PCI_BDF(2, 12, 1) INTC PIRQC
- PCI_BDF(2, 12, 2) INTC PIRQC
- PCI_BDF(2, 12, 3) INTC PIRQC
- PCI_BDF(2, 12, 4) INTC PIRQC
- >;
+ compatible = "intel,pch7";
+
+ irq-router {
+ compatible = "intel,queensbay-irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0xcee0>;
+ intel,pirq-routing = <
+ /* TunnelCreek PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQE
+ PCI_BDF(0, 3, 0) INTA PIRQF
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTB PIRQB
+ PCI_BDF(0, 23, 0) INTC PIRQC
+ PCI_BDF(0, 23, 0) INTD PIRQD
+ PCI_BDF(0, 24, 0) INTA PIRQB
+ PCI_BDF(0, 24, 0) INTB PIRQC
+ PCI_BDF(0, 24, 0) INTC PIRQD
+ PCI_BDF(0, 24, 0) INTD PIRQA
+ PCI_BDF(0, 25, 0) INTA PIRQC
+ PCI_BDF(0, 25, 0) INTB PIRQD
+ PCI_BDF(0, 25, 0) INTC PIRQA
+ PCI_BDF(0, 25, 0) INTD PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQD
+ PCI_BDF(0, 26, 0) INTB PIRQA
+ PCI_BDF(0, 26, 0) INTC PIRQB
+ PCI_BDF(0, 26, 0) INTD PIRQC
+ PCI_BDF(0, 27, 0) INTA PIRQG
+ /*
+ * Topcliff PCI devices
+ *
+ * Note on the Crown Bay board, Topcliff
+ * chipset is connected to TunnelCreek
+ * PCIe port 0, so its bus number is 1
+ * for its PCIe port and 2 for its PCI
+ * devices per U-Boot current PCI bus
+ * enumeration algorithm.
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(2, 0, 1) INTA PIRQA
+ PCI_BDF(2, 0, 2) INTA PIRQA
+ PCI_BDF(2, 2, 0) INTB PIRQD
+ PCI_BDF(2, 2, 1) INTB PIRQD
+ PCI_BDF(2, 2, 2) INTB PIRQD
+ PCI_BDF(2, 2, 3) INTB PIRQD
+ PCI_BDF(2, 2, 4) INTB PIRQD
+ PCI_BDF(2, 4, 0) INTC PIRQC
+ PCI_BDF(2, 4, 1) INTC PIRQC
+ PCI_BDF(2, 6, 0) INTD PIRQB
+ PCI_BDF(2, 8, 0) INTA PIRQA
+ PCI_BDF(2, 8, 1) INTA PIRQA
+ PCI_BDF(2, 8, 2) INTA PIRQA
+ PCI_BDF(2, 8, 3) INTA PIRQA
+ PCI_BDF(2, 10, 0) INTB PIRQD
+ PCI_BDF(2, 10, 1) INTB PIRQD
+ PCI_BDF(2, 10, 2) INTB PIRQD
+ PCI_BDF(2, 10, 3) INTB PIRQD
+ PCI_BDF(2, 10, 4) INTB PIRQD
+ PCI_BDF(2, 12, 0) INTC PIRQC
+ PCI_BDF(2, 12, 1) INTC PIRQC
+ PCI_BDF(2, 12, 2) INTC PIRQC
+ PCI_BDF(2, 12, 3) INTC PIRQC
+ PCI_BDF(2, 12, 4) INTC PIRQC
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "sst,25vf016b",
+ "spi-flash";
+ memory-map = <0xffe00000 0x00200000>;
+ };
+ };
};
};
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 55165e1464..a2f5a1f223 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -79,37 +79,59 @@
current-speed = <115200>;
};
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 8>;
- intel,pirq-mask = <0xdef8>;
- intel,pirq-routing = <
- PCI_BDF(0, 20, 0) INTA PIRQE
- PCI_BDF(0, 20, 1) INTB PIRQF
- PCI_BDF(0, 20, 2) INTC PIRQG
- PCI_BDF(0, 20, 3) INTD PIRQH
- PCI_BDF(0, 20, 4) INTA PIRQE
- PCI_BDF(0, 20, 5) INTB PIRQF
- PCI_BDF(0, 20, 6) INTC PIRQG
- PCI_BDF(0, 20, 7) INTD PIRQH
- PCI_BDF(0, 21, 0) INTA PIRQE
- PCI_BDF(0, 21, 1) INTB PIRQF
- PCI_BDF(0, 21, 2) INTC PIRQG
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 23, 1) INTB PIRQB
-
- /* PCIe root ports downstream interrupts */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(1, 0, 0) INTB PIRQB
- PCI_BDF(1, 0, 0) INTC PIRQC
- PCI_BDF(1, 0, 0) INTD PIRQD
- PCI_BDF(2, 0, 0) INTA PIRQB
- PCI_BDF(2, 0, 0) INTB PIRQC
- PCI_BDF(2, 0, 0) INTC PIRQD
- PCI_BDF(2, 0, 0) INTD PIRQA
- >;
+ compatible = "intel,pch7";
+
+ irq-router {
+ compatible = "intel,quark-irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0xdef8>;
+ intel,pirq-routing = <
+ PCI_BDF(0, 20, 0) INTA PIRQE
+ PCI_BDF(0, 20, 1) INTB PIRQF
+ PCI_BDF(0, 20, 2) INTC PIRQG
+ PCI_BDF(0, 20, 3) INTD PIRQH
+ PCI_BDF(0, 20, 4) INTA PIRQE
+ PCI_BDF(0, 20, 5) INTB PIRQF
+ PCI_BDF(0, 20, 6) INTC PIRQG
+ PCI_BDF(0, 20, 7) INTD PIRQH
+ PCI_BDF(0, 21, 0) INTA PIRQE
+ PCI_BDF(0, 21, 1) INTB PIRQF
+ PCI_BDF(0, 21, 2) INTC PIRQG
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 23, 1) INTB PIRQB
+
+ /* PCIe root ports downstream interrupts */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x00010000 0x00010000>;
+ };
+ };
+ };
};
};
@@ -127,21 +149,4 @@
bank-name = "B";
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #size-cells = <1>;
- #address-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x00010000 0x00010000>;
- };
- };
- };
-
};
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index bbfd6d4028..e7ef7c987b 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -150,66 +150,91 @@
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "ibase";
- intel,ibase-offset = <0x50>;
- intel,pirq-link = <8 8>;
- intel,pirq-mask = <0xdee0>;
- intel,pirq-routing = <
- /* BayTrail PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQA
- PCI_BDF(0, 3, 0) INTA PIRQA
- PCI_BDF(0, 16, 0) INTA PIRQA
- PCI_BDF(0, 17, 0) INTA PIRQA
- PCI_BDF(0, 18, 0) INTA PIRQA
- PCI_BDF(0, 19, 0) INTA PIRQA
- PCI_BDF(0, 20, 0) INTA PIRQA
- PCI_BDF(0, 21, 0) INTA PIRQA
- PCI_BDF(0, 22, 0) INTA PIRQA
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 24, 0) INTA PIRQA
- PCI_BDF(0, 24, 1) INTC PIRQC
- PCI_BDF(0, 24, 2) INTD PIRQD
- PCI_BDF(0, 24, 3) INTB PIRQB
- PCI_BDF(0, 24, 4) INTA PIRQA
- PCI_BDF(0, 24, 5) INTC PIRQC
- PCI_BDF(0, 24, 6) INTD PIRQD
- PCI_BDF(0, 24, 7) INTB PIRQB
- PCI_BDF(0, 26, 0) INTA PIRQA
- PCI_BDF(0, 27, 0) INTA PIRQA
- PCI_BDF(0, 28, 0) INTA PIRQA
- PCI_BDF(0, 28, 1) INTB PIRQB
- PCI_BDF(0, 28, 2) INTC PIRQC
- PCI_BDF(0, 28, 3) INTD PIRQD
- PCI_BDF(0, 29, 0) INTA PIRQA
- PCI_BDF(0, 30, 0) INTA PIRQA
- PCI_BDF(0, 30, 1) INTD PIRQD
- PCI_BDF(0, 30, 2) INTB PIRQB
- PCI_BDF(0, 30, 3) INTC PIRQC
- PCI_BDF(0, 30, 4) INTD PIRQD
- PCI_BDF(0, 30, 5) INTB PIRQB
- PCI_BDF(0, 31, 3) INTB PIRQB
+ compatible = "pci8086,0f1c", "intel,pch9";
- /* PCIe root ports downstream interrupts */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(1, 0, 0) INTB PIRQB
- PCI_BDF(1, 0, 0) INTC PIRQC
- PCI_BDF(1, 0, 0) INTD PIRQD
- PCI_BDF(2, 0, 0) INTA PIRQB
- PCI_BDF(2, 0, 0) INTB PIRQC
- PCI_BDF(2, 0, 0) INTC PIRQD
- PCI_BDF(2, 0, 0) INTD PIRQA
- PCI_BDF(3, 0, 0) INTA PIRQC
- PCI_BDF(3, 0, 0) INTB PIRQD
- PCI_BDF(3, 0, 0) INTC PIRQA
- PCI_BDF(3, 0, 0) INTD PIRQB
- PCI_BDF(4, 0, 0) INTA PIRQD
- PCI_BDF(4, 0, 0) INTB PIRQA
- PCI_BDF(4, 0, 0) INTC PIRQB
- PCI_BDF(4, 0, 0) INTD PIRQC
- >;
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /* BayTrail PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ PCI_BDF(0, 3, 0) INTA PIRQA
+ PCI_BDF(0, 16, 0) INTA PIRQA
+ PCI_BDF(0, 17, 0) INTA PIRQA
+ PCI_BDF(0, 18, 0) INTA PIRQA
+ PCI_BDF(0, 19, 0) INTA PIRQA
+ PCI_BDF(0, 20, 0) INTA PIRQA
+ PCI_BDF(0, 21, 0) INTA PIRQA
+ PCI_BDF(0, 22, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 24, 0) INTA PIRQA
+ PCI_BDF(0, 24, 1) INTC PIRQC
+ PCI_BDF(0, 24, 2) INTD PIRQD
+ PCI_BDF(0, 24, 3) INTB PIRQB
+ PCI_BDF(0, 24, 4) INTA PIRQA
+ PCI_BDF(0, 24, 5) INTC PIRQC
+ PCI_BDF(0, 24, 6) INTD PIRQD
+ PCI_BDF(0, 24, 7) INTB PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQA
+ PCI_BDF(0, 27, 0) INTA PIRQA
+ PCI_BDF(0, 28, 0) INTA PIRQA
+ PCI_BDF(0, 28, 1) INTB PIRQB
+ PCI_BDF(0, 28, 2) INTC PIRQC
+ PCI_BDF(0, 28, 3) INTD PIRQD
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 30, 0) INTA PIRQA
+ PCI_BDF(0, 30, 1) INTD PIRQD
+ PCI_BDF(0, 30, 2) INTB PIRQB
+ PCI_BDF(0, 30, 3) INTC PIRQC
+ PCI_BDF(0, 30, 4) INTD PIRQD
+ PCI_BDF(0, 30, 5) INTB PIRQB
+ PCI_BDF(0, 31, 3) INTB PIRQB
+
+ /*
+ * PCIe root ports downstream
+ * interrupts
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ PCI_BDF(3, 0, 0) INTA PIRQC
+ PCI_BDF(3, 0, 0) INTB PIRQD
+ PCI_BDF(3, 0, 0) INTC PIRQA
+ PCI_BDF(3, 0, 0) INTD PIRQB
+ PCI_BDF(4, 0, 0) INTA PIRQD
+ PCI_BDF(4, 0, 0) INTB PIRQA
+ PCI_BDF(4, 0, 0) INTC PIRQB
+ PCI_BDF(4, 0, 0) INTD PIRQC
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "stmicro,n25q064a",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x006f0000 0x00010000>;
+ };
+ };
+ };
};
};
@@ -269,23 +294,6 @@
};
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "stmicro,n25q064a", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x006f0000 0x00010000>;
- };
- };
- };
-
microcode {
update@0 {
#include "microcode/m0130673322.dtsi"
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 9086b461b9..9c3f2a08e6 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -51,18 +51,22 @@
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1,0 {
+ pch@1,0 {
reg = <0x00000800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 4>;
- intel,pirq-mask = <0x0e40>;
- intel,pirq-routing = <
- /* PIIX UHCI */
- PCI_BDF(0, 1, 2) INTD PIRQD
- /* e1000 NIC */
- PCI_BDF(0, 3, 0) INTA PIRQC
- >;
+ compatible = "intel,pch7";
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 4>;
+ intel,pirq-mask = <0x0e40>;
+ intel,pirq-routing = <
+ /* PIIX UHCI */
+ PCI_BDF(0, 1, 2) INTD PIRQD
+ /* e1000 NIC */
+ PCI_BDF(0, 3, 0) INTA PIRQC
+ >;
+ };
};
};
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 145e8115ce..5d601b3444 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -62,24 +62,28 @@
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 8>;
- intel,pirq-mask = <0x0e40>;
- intel,pirq-routing = <
- /* e1000 NIC */
- PCI_BDF(0, 2, 0) INTA PIRQG
- /* ICH9 UHCI */
- PCI_BDF(0, 29, 0) INTA PIRQA
- PCI_BDF(0, 29, 1) INTB PIRQB
- PCI_BDF(0, 29, 2) INTC PIRQC
- /* ICH9 EHCI */
- PCI_BDF(0, 29, 7) INTD PIRQD
- /* ICH9 SATA */
- PCI_BDF(0, 31, 2) INTA PIRQA
- >;
+ compatible = "intel,pch9";
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0x0e40>;
+ intel,pirq-routing = <
+ /* e1000 NIC */
+ PCI_BDF(0, 2, 0) INTA PIRQG
+ /* ICH9 UHCI */
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 29, 1) INTB PIRQB
+ PCI_BDF(0, 29, 2) INTC PIRQC
+ /* ICH9 EHCI */
+ PCI_BDF(0, 29, 7) INTD PIRQD
+ /* ICH9 SATA */
+ PCI_BDF(0, 31, 2) INTA PIRQA
+ >;
+ };
};
};
generated by cgit (git 2.34.1) at 2025-01-05 02:36:26 +0000