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-rw-r--r--arch/x86/dts/Makefile4
-rw-r--r--arch/x86/dts/crownbay.dts54
-rw-r--r--arch/x86/dts/galileo.dts22
-rw-r--r--arch/x86/dts/minnowmax.dts23
-rw-r--r--arch/x86/dts/qemu-x86_i440fx.dts50
-rw-r--r--arch/x86/dts/qemu-x86_q35.dts67
6 files changed, 219 insertions, 1 deletions
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 431bbd8a0d..f86514ce83 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -2,7 +2,9 @@ dtb-y += chromebook_link.dtb \
chromebox_panther.dtb \
crownbay.dtb \
galileo.dtb \
- minnowmax.dtb
+ minnowmax.dtb \
+ qemu-x86_i440fx.dtb \
+ qemu-x86_q35.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index fbdeade047..d68efda8df 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
@@ -135,6 +137,58 @@
};
};
};
+
+ irq-router@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /* TunnelCreek PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQE
+ PCI_BDF(0, 3, 0) INTA PIRQF
+ PCI_BDF(0, 23, 0) INTA PIRQE
+ PCI_BDF(0, 24, 0) INTA PIRQF
+ PCI_BDF(0, 25, 0) INTA PIRQG
+ PCI_BDF(0, 26, 0) INTA PIRQH
+ PCI_BDF(0, 27, 0) INTA PIRQG
+ /*
+ * Topcliff PCI devices
+ *
+ * Note on the Crown Bay board, Topcliff chipset
+ * is connected to TunnelCreek PCIe port 0, so
+ * its bus number is 1 for its PCIe port and 2
+ * for its PCI devices per U-Boot currnet PCI
+ * bus enumeration algorithm.
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(2, 0, 1) INTA PIRQA
+ PCI_BDF(2, 0, 2) INTA PIRQA
+ PCI_BDF(2, 2, 0) INTB PIRQB
+ PCI_BDF(2, 2, 1) INTB PIRQB
+ PCI_BDF(2, 2, 2) INTB PIRQB
+ PCI_BDF(2, 2, 3) INTB PIRQB
+ PCI_BDF(2, 2, 4) INTB PIRQB
+ PCI_BDF(2, 4, 0) INTC PIRQC
+ PCI_BDF(2, 4, 1) INTC PIRQC
+ PCI_BDF(2, 6, 0) INTD PIRQD
+ PCI_BDF(2, 8, 0) INTA PIRQA
+ PCI_BDF(2, 8, 1) INTA PIRQA
+ PCI_BDF(2, 8, 2) INTA PIRQA
+ PCI_BDF(2, 8, 3) INTA PIRQA
+ PCI_BDF(2, 10, 0) INTB PIRQB
+ PCI_BDF(2, 10, 1) INTB PIRQB
+ PCI_BDF(2, 10, 2) INTB PIRQB
+ PCI_BDF(2, 10, 3) INTB PIRQB
+ PCI_BDF(2, 10, 4) INTB PIRQB
+ PCI_BDF(2, 12, 0) INTC PIRQC
+ PCI_BDF(2, 12, 1) INTC PIRQC
+ PCI_BDF(2, 12, 2) INTC PIRQC
+ PCI_BDF(2, 12, 3) INTC PIRQC
+ PCI_BDF(2, 12, 4) INTC PIRQC
+ >;
+ };
};
};
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 60dbc5f8a3..2ba081e9dc 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/mrc/quark.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
/include/ "skeleton.dtsi"
@@ -67,6 +68,27 @@
clock-frequency = <44236800>;
current-speed = <115200>;
};
+
+ irq-router@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0xdef8>;
+ intel,pirq-routing = <
+ PCI_BDF(0, 20, 0) INTA PIRQE
+ PCI_BDF(0, 20, 1) INTB PIRQF
+ PCI_BDF(0, 20, 2) INTC PIRQG
+ PCI_BDF(0, 20, 3) INTD PIRQH
+ PCI_BDF(0, 20, 4) INTA PIRQE
+ PCI_BDF(0, 20, 5) INTB PIRQF
+ PCI_BDF(0, 20, 6) INTC PIRQG
+ PCI_BDF(0, 20, 7) INTD PIRQH
+ PCI_BDF(0, 21, 0) INTA PIRQE
+ PCI_BDF(0, 21, 1) INTB PIRQF
+ PCI_BDF(0, 21, 2) INTC PIRQG
+ >;
+ };
};
gpioa {
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 7103bc5077..bd21bfb0b4 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include <dt-bindings/gpio/x86-gpio.h>
+
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
@@ -22,6 +24,27 @@
silent_console = <0>;
};
+ pch_pinctrl {
+ compatible = "intel,x86-pinctrl";
+ io-base = <0x4c>;
+
+ pin_usb_host_en0@0 {
+ gpio-offset = <0x80 8>;
+ pad-offset = <0x260>;
+ mode-gpio;
+ output-value = <1>;
+ direction = <PIN_OUTPUT>;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = <0x80 9>;
+ pad-offset = <0x258>;
+ mode-gpio;
+ output-value = <1>;
+ direction = <PIN_OUTPUT>;
+ };
+ };
+
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
new file mode 100644
index 0000000000..557428a459
--- /dev/null
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+ model = "QEMU x86 (I440FX)";
+ compatible = "qemu,x86";
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ pci {
+ compatible = "pci-x86";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
+ 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+ irq-router@1,0 {
+ reg = <0x00000800 0 0 0 0>;
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 4>;
+ intel,pirq-mask = <0x0e40>;
+ intel,pirq-routing = <
+ /* PIIX UHCI */
+ PCI_BDF(0, 1, 2) INTD PIRQD
+ /* e1000 NIC */
+ PCI_BDF(0, 3, 0) INTA PIRQC
+ >;
+ };
+ };
+
+};
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
new file mode 100644
index 0000000000..c259f2a3d2
--- /dev/null
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/* ICH9 IRQ router has discrete PIRQ control registers */
+#undef PIRQE
+#undef PIRQF
+#undef PIRQG
+#undef PIRQH
+#define PIRQE 8
+#define PIRQF 9
+#define PIRQG 10
+#define PIRQH 11
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+ model = "QEMU x86 (Q35)";
+ compatible = "qemu,x86";
+
+ config {
+ silent_console = <0>;
+ u-boot,no-apm-finalize;
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ pci {
+ compatible = "pci-x86";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
+ 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+ irq-router@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0x0e40>;
+ intel,pirq-routing = <
+ /* e1000 NIC */
+ PCI_BDF(0, 2, 0) INTA PIRQG
+ /* ICH9 UHCI */
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 29, 1) INTB PIRQB
+ PCI_BDF(0, 29, 2) INTC PIRQC
+ /* ICH9 EHCI */
+ PCI_BDF(0, 29, 7) INTD PIRQD
+ /* ICH9 SATA */
+ PCI_BDF(0, 31, 2) INTA PIRQA
+ >;
+ };
+ };
+
+};
generated by cgit (git 2.34.1) at 2025-01-04 01:20:30 +0000