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-rw-r--r--arch/x86/dts/chromebook_samus.dts53
-rw-r--r--arch/x86/dts/reset.dtsi2
-rw-r--r--arch/x86/dts/rtc.dtsi2
-rw-r--r--arch/x86/dts/u-boot.dtsi162
4 files changed, 153 insertions, 66 deletions
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 35211ed81b..772ea5c91b 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -9,6 +9,12 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#ifdef CONFIG_CHROMEOS
+#include "chromeos-x86.dtsi"
+#include "flashmap-x86-ro.dtsi"
+#include "flashmap-8mb-rw.dtsi"
+#endif
+
/ {
model = "Google Samus";
compatible = "google,samus", "intel,broadwell";
@@ -17,6 +23,7 @@
spi0 = &spi;
usb0 = &usb_0;
usb1 = &usb_1;
+ cros-ec0 = &cros_ec;
};
config {
@@ -73,6 +80,7 @@
/* Put this first: it is the default */
gpio_unused: gpio-unused {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
@@ -80,6 +88,7 @@
};
gpio_acpi_sci: acpi-sci {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
invert;
@@ -87,6 +96,7 @@
};
gpio_acpi_smi: acpi-smi {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
invert;
@@ -94,12 +104,14 @@
};
gpio_input: gpio-input {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
};
gpio_input_invert: gpio-input-invert {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
@@ -107,9 +119,11 @@
};
gpio_native: gpio-native {
+ u-boot,dm-pre-reloc;
};
gpio_out_high: gpio-out-high {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <1>;
@@ -118,6 +132,7 @@
};
gpio_out_low: gpio-out-low {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <0>;
@@ -126,6 +141,7 @@
};
gpio_pirq: gpio-pirq {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
@@ -133,6 +149,7 @@
};
soc_gpio@0 {
+ u-boot,dm-pre-reloc;
config =
<0 &gpio_unused 0>, /* unused */
<1 &gpio_unused 0>, /* unused */
@@ -250,8 +267,10 @@
spd {
#address-cells = <1>;
#size-cells = <0>;
+ u-boot,dm-pre-reloc;
samsung_4 {
reg = <6>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -291,6 +310,7 @@
* columns 10, density 4096 mb, x32
*/
reg = <8>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -326,6 +346,7 @@
};
samsung_8 {
reg = <10>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -365,6 +386,7 @@
* columns 11, density 4096 mb, x16
*/
reg = <12>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -404,6 +426,7 @@
* columns 11, density 8192 mb, x16
*/
reg = <13>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 05 1a 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -443,6 +466,7 @@
* columns 11, density 8192 mb, x16
*/
reg = <15>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 05 1a 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -540,7 +564,7 @@
compatible = "ehci-pci";
};
- pch@1f,0 {
+ pch: pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,broadwell-pch";
u-boot,dm-pre-reloc;
@@ -559,10 +583,12 @@
power-enable-gpio = <&gpio_a 23 0>;
spi: spi {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
- spi-flash@0 {
+ fwstore_spi: spi-flash@0 {
+ u-boot,dm-pre-reloc;
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
@@ -570,6 +596,7 @@
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
+ u-boot,dm-pre-reloc;
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
};
@@ -609,7 +636,8 @@
#size-cells = <0>;
u-boot,dm-pre-reloc;
intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
- cros-ec@200 {
+ cros_ec: cros-ec {
+ u-boot,dm-pre-reloc;
compatible = "google,cros-ec-lpc";
reg = <0x204 1 0x200 1 0x880 0x80>;
@@ -630,7 +658,7 @@
sata@1f,2 {
compatible = "intel,wildcatpoint-ahci";
reg = <0x0000fa00 0 0 0 0>;
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-proper;
intel,sata-mode = "ahci";
intel,sata-port-map = <1>;
intel,sata-port0-gen3-tx = <0x72>;
@@ -645,12 +673,19 @@
};
tpm {
+ u-boot,dm-pre-reloc;
reg = <0xfed40000 0x5000>;
compatible = "infineon,slb9635lpc";
+ secdata {
+ u-boot,dm-pre-reloc;
+ compatible = "google,tpm-secdata";
+ };
};
microcode {
+ u-boot,dm-pre-reloc;
update@0 {
+ u-boot,dm-pre-reloc;
#include "microcode/mc0306d4_00000018.dtsi"
};
};
@@ -668,3 +703,13 @@
};
};
+
+&rtc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nvdata {
+ u-boot,dm-pre-reloc;
+ compatible = "google,cmos-nvdata";
+ reg = <0x26>;
+ };
+};
diff --git a/arch/x86/dts/reset.dtsi b/arch/x86/dts/reset.dtsi
index f979d83757..555d0dd960 100644
--- a/arch/x86/dts/reset.dtsi
+++ b/arch/x86/dts/reset.dtsi
@@ -1,5 +1,5 @@
/ {
- reset {
+ reset: reset {
compatible = "x86,reset";
u-boot,dm-pre-reloc;
};
diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi
index 1797e042da..d0bbd84e50 100644
--- a/arch/x86/dts/rtc.dtsi
+++ b/arch/x86/dts/rtc.dtsi
@@ -1,5 +1,5 @@
/ {
- rtc {
+ rtc: rtc {
compatible = "motorola,mc146818";
u-boot,dm-pre-reloc;
reg = <0x70 2>;
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 1050236330..daeb168b65 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -6,86 +6,128 @@
#include <config.h>
-#ifdef CONFIG_ROM_SIZE
+#ifdef CONFIG_CHROMEOS
/ {
binman {
- filename = "u-boot.rom";
- end-at-4gb;
- sort-by-offset;
- pad-byte = <0xff>;
- size = <CONFIG_ROM_SIZE>;
-#ifdef CONFIG_HAVE_INTEL_ME
- intel-descriptor {
- filename = CONFIG_FLASH_DESCRIPTOR_FILE;
- };
- intel-me {
- filename = CONFIG_INTEL_ME_FILE;
+ multiple-images;
+ rom: rom {
};
+ };
+};
+#else
+/ {
+ rom: binman {
+ };
+};
#endif
-#ifdef CONFIG_SPL
- u-boot-spl-with-ucode-ptr {
- offset = <CONFIG_SPL_TEXT_BASE>;
- };
- u-boot-dtb-with-ucode2 {
- type = "u-boot-dtb-with-ucode";
- };
- u-boot {
- offset = <0xfff00000>;
- };
+#ifdef CONFIG_ROM_SIZE
+&rom {
+ filename = "u-boot.rom";
+ end-at-4gb;
+ sort-by-offset;
+ pad-byte = <0xff>;
+ size = <CONFIG_ROM_SIZE>;
+#ifdef CONFIG_HAVE_INTEL_ME
+ intel-descriptor {
+ filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+ };
+ intel-me {
+ filename = CONFIG_INTEL_ME_FILE;
+ };
+#endif
+#ifdef CONFIG_TPL
+ u-boot-tpl-with-ucode-ptr {
+ offset = <CONFIG_TPL_TEXT_BASE>;
+ };
+ u-boot-tpl-dtb {
+ };
+ u-boot-spl {
+ offset = <CONFIG_SPL_TEXT_BASE>;
+ };
+ u-boot-spl-dtb {
+ };
+ u-boot {
+ offset = <CONFIG_SYS_TEXT_BASE>;
+ };
+#elif defined(CONFIG_SPL)
+ u-boot-spl-with-ucode-ptr {
+ offset = <CONFIG_SPL_TEXT_BASE>;
+ };
+ u-boot-dtb-with-ucode2 {
+ type = "u-boot-dtb-with-ucode";
+ };
+ u-boot {
+ /*
+ * TODO(sjg@chromium.org):
+ * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
+ * for boards with textbase in SDRAM we cannot do this. Just use
+ * an assumed-valid value (1MB before the end of flash) here so
+ * that we can actually build an image for coreboot, etc.
+ * We need a better solution, perhaps a separate Kconfig.
+ */
+#if CONFIG_SYS_TEXT_BASE == 0x1110000
+ offset = <0xfff00000>;
#else
- u-boot-with-ucode-ptr {
- offset = <CONFIG_SYS_TEXT_BASE>;
- };
+ offset = <CONFIG_SYS_TEXT_BASE>;
#endif
- u-boot-dtb-with-ucode {
- };
- u-boot-ucode {
- align = <16>;
- };
+ };
+#else
+ u-boot-with-ucode-ptr {
+ offset = <CONFIG_SYS_TEXT_BASE>;
+ };
+#endif
+ u-boot-dtb-with-ucode {
+ };
+ u-boot-ucode {
+ align = <16>;
+ };
#ifdef CONFIG_HAVE_MRC
- intel-mrc {
- offset = <CONFIG_X86_MRC_ADDR>;
- };
+ intel-mrc {
+ offset = <CONFIG_X86_MRC_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_FSP
- intel-fsp {
- filename = CONFIG_FSP_FILE;
- offset = <CONFIG_FSP_ADDR>;
- };
+ intel-fsp {
+ filename = CONFIG_FSP_FILE;
+ offset = <CONFIG_FSP_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_CMC
- intel-cmc {
- filename = CONFIG_CMC_FILE;
- offset = <CONFIG_CMC_ADDR>;
- };
+ intel-cmc {
+ filename = CONFIG_CMC_FILE;
+ offset = <CONFIG_CMC_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_VGA_BIOS
- intel-vga {
- filename = CONFIG_VGA_BIOS_FILE;
- offset = <CONFIG_VGA_BIOS_ADDR>;
- };
+ intel-vga {
+ filename = CONFIG_VGA_BIOS_FILE;
+ offset = <CONFIG_VGA_BIOS_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_VBT
- intel-vbt {
- filename = CONFIG_VBT_FILE;
- offset = <CONFIG_VBT_ADDR>;
- };
+ intel-vbt {
+ filename = CONFIG_VBT_FILE;
+ offset = <CONFIG_VBT_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_REFCODE
- intel-refcode {
- offset = <CONFIG_X86_REFCODE_ADDR>;
- };
+ intel-refcode {
+ offset = <CONFIG_X86_REFCODE_ADDR>;
+ };
#endif
-#ifdef CONFIG_SPL
- x86-start16-spl {
- offset = <CONFIG_SYS_X86_START16>;
- };
+#ifdef CONFIG_TPL
+ x86-start16-tpl {
+ offset = <CONFIG_SYS_X86_START16>;
+ };
+#elif defined(CONFIG_SPL)
+ x86-start16-spl {
+ offset = <CONFIG_SYS_X86_START16>;
+ };
#else
- x86-start16 {
- offset = <CONFIG_SYS_X86_START16>;
- };
-#endif
+ x86-start16 {
+ offset = <CONFIG_SYS_X86_START16>;
};
+#endif
};
#endif
generated by cgit (git 2.34.1) at 2024-12-28 07:20:18 +0000