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-rw-r--r--arch/x86/dts/chromebook_coral.dts15
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index dea35b73a0..965d9f387d 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -516,6 +516,11 @@
20 23 22 21 18 19 16 17
/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
25 28 30 31 26 27 24 29>;
+
+ fspm,dimm0-spd-address = <0>;
+ fspm,dimm1-spd-address = <0>;
+ fspm,skip-cse-rbp = <1>;
+ fspm,enable-s3-heci2 = <0>;
};
&fsp_s {
@@ -594,13 +599,9 @@
fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>;
fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
- /* Enable Audio Clock and Power gating */
- fsps,hd-audio-clk-gate = <1>;
- fsps,hd-audio-pwr-gate = <1>;
- fsps,bios-cfg-lock-down = <1>;
-
- /* Enable lpss s0ix */
- fsps,lpss-s0ix-enable = <1>;
+ /* Enable WiFi */
+ fsps,pcie-root-port-en = [01 00 00 00 00 00];
+ fsps,pcie-rp-hot-plug = [00 00 00 00 00 00];
fsps,skip-mp-init = <1>;
fsps,spi-eiss = <0>;