4 files changed, 73 insertions, 45 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index fcdf6e26cb..e866580046 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -7,27 +7,6 @@
 #ifndef _ASM_ARCH_BD82X6X_H
 #define _ASM_ARCH_BD82X6X_H
 
-void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
-void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
-void bd82x6x_pci_init(pci_dev_t dev);
-void bd82x6x_usb_ehci_init(pci_dev_t dev);
-void bd82x6x_usb_xhci_init(pci_dev_t dev);
-int gma_func0_init(struct udevice *dev, const void *blob, int node);
-int bd82x6x_init(void);
-
-/**
- * struct x86_cpu_priv - Information about a single CPU
- *
- * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
- * just a number representing the CPU core
- *
- * TODO: Move this to driver model once lifecycle is understood
- */
-struct x86_cpu_priv {
-	int apic_id;
-	int start_err;
-};
-
-int model_206ax_init(struct x86_cpu_priv *cpu);
+int gma_func0_init(struct udevice *dev);
 
 #endif
diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h
index 3a0809d6ec..eb1b73f92e 100644
--- a/arch/x86/include/asm/arch-ivybridge/me.h
+++ b/arch/x86/include/asm/arch-ivybridge/me.h
@@ -345,12 +345,47 @@ struct __packed me_fwcaps {
 	u8 reserved[3];
 };
 
-/* Defined in me_status.c for both romstage and ramstage */
+/**
+ * intel_me_status() - Check Intel Management Engine status
+ *
+ * struct hfs:	Firmware status
+ * struct gmes:	Management engine status
+ */
 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
 
-void intel_early_me_status(void);
-int intel_early_me_init(void);
-int intel_early_me_uma_size(void);
-int intel_early_me_init_done(u8 status);
+/**
+ * intel_early_me_status() - Check early Management Engine Status
+ *
+ * @me_dev:	Management engine PCI device
+ */
+void intel_early_me_status(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init() - Early Intel Management Engine init
+ *
+ * @me_dev:	Management engine PCI device
+ * @return 0 if OK, -ve on error
+ */
+int intel_early_me_init(struct udevice *me_dev);
+
+/**
+ * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
+ *
+ * @me_dev:	Management engine PCI device
+ * @return UMA size if OK, -EINVAL on error
+ */
+int intel_early_me_uma_size(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init_done() - Complete Intel Management Engine init
+ *
+ * @dev:	Northbridge device
+ * @me_dev:	Management engine PCI device
+ * @status:	Status result (ME_INIT_...)
+ * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
+ * if ME did not respond
+ */
+int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
+			     uint status);
 
 #endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index 21df083842..af3e8e747c 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -30,11 +30,6 @@
 
 #define SMBUS_IO_BASE		0x0400
 
-int pch_silicon_revision(void);
-int pch_silicon_type(void);
-int pch_silicon_supported(int type, int rev);
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-
 #define MAINBOARD_POWER_OFF	0
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
@@ -105,6 +100,8 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 #define GPIO_ROUT		0xb8
 
 #define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define  COMB_DEC_RANGE		(1 << 4)  /* 0x2f8-0x2ff (COM2) */
+#define  COMA_DEC_RANGE		(0 << 0)  /* 0x3f8-0x3ff (COM1) */
 #define LPC_EN			0x82 /* LPC IF Enables Register */
 #define  CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
 #define  CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
@@ -121,6 +118,14 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 #define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
 #define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
 #define LPC_GENX_DEC(x)		(0x84 + 4 * (x))
+#define  GEN_DEC_RANGE_256B	0xfc0000  /* 256 Bytes */
+#define  GEN_DEC_RANGE_128B	0x7c0000  /* 128 Bytes */
+#define  GEN_DEC_RANGE_64B	0x3c0000  /* 64 Bytes */
+#define  GEN_DEC_RANGE_32B	0x1c0000  /* 32 Bytes */
+#define  GEN_DEC_RANGE_16B	0x0c0000  /* 16 Bytes */
+#define  GEN_DEC_RANGE_8B	0x040000  /* 8 Bytes */
+#define  GEN_DEC_RANGE_4B	0x000000  /* 4 Bytes */
+#define  GEN_DEC_RANGE_EN	(1 << 0)  /* Range Enable */
 
 /* PCI Configuration Space (D31:F1): IDE */
 #define PCH_IDE_DEV		PCI_BDF(0, 0x1f, 1)
@@ -460,17 +465,23 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 #define   DMISCI_STS	(1 << 9)
 #define TCO2_STS	0x66
 
-int lpc_init(struct pci_controller *hose, pci_dev_t dev);
-void lpc_enable(pci_dev_t dev);
+/**
+ * pch_silicon_revision() - Read silicon device ID from the PCH
+ *
+ * @dev:	PCH device
+ * @return silicon device ID
+ */
+int pch_silicon_type(struct udevice *dev);
 
 /**
- * lpc_early_init() - set up LPC serial ports and other early things
+ * pch_pch_iobp_update() - Update a pch register
  *
- * @blob:	Device tree blob
- * @node:	Offset of LPC node
- * @dev:	PCH PCI device containing the LPC
- * @return 0 if OK, -ve on error
+ * @dev:	PCH device
+ * @address:	Address to update
+ * @andvalue:	Value to AND with existing value
+ * @orvalue:	Value to OR with existing value
  */
-int lpc_early_init(const void *blob, int node, pci_dev_t dev);
+void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
+			     u32 orvalue);
 
 #endif
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index c9605258b5..d137d6786a 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -108,12 +108,15 @@
 
 #define DMIBAR_REG(x)	(DEFAULT_DMIBAR + x)
 
-int bridge_silicon_revision(void);
-
-void northbridge_enable(pci_dev_t dev);
-void northbridge_init(pci_dev_t dev);
+/**
+ * bridge_silicon_revision() - Get the Northbridge revision
+ *
+ * @dev:	Northbridge device
+ * @return revision ID (bits 3:0) and bridge ID (bits 7:4)
+ */
+int bridge_silicon_revision(struct udevice *dev);
 
-void report_platform_info(void);
+void report_platform_info(struct udevice *dev);
 
 void sandybridge_early_init(int chipset_type);