9 files changed, 107 insertions, 11 deletions
diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h
new file mode 100644
index 0000000000..7f2ffd49ec
--- /dev/null
+++ b/arch/x86/include/asm/acpi/global_nvs.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ACPI_GNVS_H_
+#define _ACPI_GNVS_H_
+
+/*
+ * This file provides two ACPI global NVS macros: ACPI_GNVS_ADDR and
+ * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file
+ * to declare the GNVS OperationRegion, as well as write_acpi_tables()
+ * for the GNVS address runtime fix up.
+ */
+#define ACPI_GNVS_ADDR	0xdeadbeef
+#define ACPI_GNVS_SIZE	0x100
+
+#endif /* _ACPI_GNVS_H_ */
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 56aa282127..caff4d8a1e 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -299,6 +299,9 @@ struct acpi_mcfg_mmconfig {
 /* PM1_CNT bit defines */
 #define PM1_CNT_SCI_EN		(1 << 0)
 
+/* ACPI global NVS structure */
+struct acpi_global_nvs;
+
 /* These can be used by the target port */
 
 void acpi_fill_header(struct acpi_table_header *header, char *signature);
@@ -312,4 +315,5 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 			       u8 cpu, u16 flags, u8 lint);
 u32 acpi_fill_madt(u32 current);
+void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
 u32 write_acpi_tables(u32 start);
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl
new file mode 100644
index 0000000000..a28d4dfade
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/global_nvs.h>
+
+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
+Field(GNVS, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x00),
+	PCNT, 8,	/* processor count */
+	IURE, 8,	/* internal UART enabled */
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
index 22f0d68f4d..fe34d3271c 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -119,17 +119,14 @@ Device (LPCB)
 
 		Method(_STA, 0, Serialized)
 		{
-			/*
-			 * TODO:
-			 *
-			 * Need to hide the internal UART depending on whether
-			 * internal UART is enabled or not so that external
-			 * SuperIO UART can be exposed to system.
-			 */
-			Store(1, UI3E)
-			Store(1, UI4E)
-			Store(1, C1EN)
-			Return (STA_VISIBLE)
+			If (LEqual(IURE, 1)) {
+				Store(1, UI3E)
+				Store(1, UI4E)
+				Store(1, C1EN)
+				Return (STA_VISIBLE)
+			} Else {
+				Return (STA_MISSING)
+			}
 
 		}
 
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
index 6bc82ecfe1..a80d2c0e51 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -22,6 +22,9 @@ Method(_WAK, 1)
 	Return (Package() {0, 0})
 }
 
+/* ACPI global NVS */
+#include "global_nvs.asl"
+
 /* TODO: add CPU ASL support */
 
 Scope (\_SB)
diff --git a/arch/x86/include/asm/arch-baytrail/global_nvs.h b/arch/x86/include/asm/arch-baytrail/global_nvs.h
new file mode 100644
index 0000000000..56e362633f
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/global_nvs.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _GLOBAL_NVS_H_
+#define _GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+	u8	pcnt;		/* processor count */
+	u8	iuart_en;	/* internal UART enabled */
+
+	/*
+	 * Add padding so sizeof(struct acpi_global_nvs) == 0x100.
+	 * This must match the size defined in the global_nvs.asl.
+	 */
+	u8	rsvd[254];
+};
+
+#endif /* _GLOBAL_NVS_H_ */
diff --git a/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl
new file mode 100644
index 0000000000..6f0435e1de
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/global_nvs.h>
+
+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
+Field(GNVS, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x00),
+	PCNT, 8,	/* processor count */
+}
diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl
index bd72842dd6..1ecf153c0f 100644
--- a/arch/x86/include/asm/arch-quark/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl
@@ -22,6 +22,9 @@ Method(_WAK, 1)
 	Return (Package() {0, 0})
 }
 
+/* ACPI global NVS */
+#include "global_nvs.asl"
+
 /* TODO: add CPU ASL support */
 
 Scope (\_SB)
diff --git a/arch/x86/include/asm/arch-quark/global_nvs.h b/arch/x86/include/asm/arch-quark/global_nvs.h
new file mode 100644
index 0000000000..0231da0bcd
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/global_nvs.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _GLOBAL_NVS_H_
+#define _GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+	u8	pcnt;		/* processor count */
+
+	/*
+	 * Add padding so sizeof(struct acpi_global_nvs) == 0x100.
+	 * This must match the size defined in the global_nvs.asl.
+	 */
+	u8	rsvd[255];
+};
+
+#endif /* _GLOBAL_NVS_H_ */