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-rw-r--r--arch/x86/include/asm/arch-baytrail/gpio.h13
-rw-r--r--arch/x86/include/asm/arch-coreboot/gpio.h13
-rw-r--r--arch/x86/include/asm/arch-efi/gpio.h10
-rw-r--r--arch/x86/include/asm/arch-ivybridge/gpio.h13
-rw-r--r--arch/x86/include/asm/arch-qemu/gpio.h13
-rw-r--r--arch/x86/include/asm/arch-quark/gpio.h13
-rw-r--r--arch/x86/include/asm/arch-queensbay/gpio.h13
-rw-r--r--arch/x86/include/asm/gpio.h1
-rw-r--r--arch/x86/include/asm/pci.h19
-rw-r--r--arch/x86/include/asm/pirq_routing.h12
10 files changed, 8 insertions, 112 deletions
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h
deleted file mode 100644
index 4e8987ce5c..0000000000
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h
deleted file mode 100644
index 31edef9623..0000000000
--- a/arch/x86/include/asm/arch-coreboot/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2014, Google Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-efi/gpio.h b/arch/x86/include/asm/arch-efi/gpio.h
deleted file mode 100644
index f044f07537..0000000000
--- a/arch/x86/include/asm/arch-efi/gpio.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h
deleted file mode 100644
index 31edef9623..0000000000
--- a/arch/x86/include/asm/arch-ivybridge/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2014, Google Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-qemu/gpio.h b/arch/x86/include/asm/arch-qemu/gpio.h
deleted file mode 100644
index ca8cba4f97..0000000000
--- a/arch/x86/include/asm/arch-qemu/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-quark/gpio.h b/arch/x86/include/asm/arch-quark/gpio.h
deleted file mode 100644
index ca8cba4f97..0000000000
--- a/arch/x86/include/asm/arch-quark/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h b/arch/x86/include/asm/arch-queensbay/gpio.h
deleted file mode 100644
index ab4e059131..0000000000
--- a/arch/x86/include/asm/arch-queensbay/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index ed85b08ce7..403851b792 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -7,7 +7,6 @@
#define _X86_GPIO_H_
#include <linux/compiler.h>
-#include <asm/arch/gpio.h>
#include <asm-generic/gpio.h>
struct ich6_bank_platdata {
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index a2945f1aff..f93c840244 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -18,25 +18,6 @@
#ifndef __ASSEMBLY__
-#define DEFINE_PCI_DEVICE_TABLE(_table) \
- const struct pci_device_id _table[]
-
-struct pci_controller;
-
-void pci_setup_type1(struct pci_controller *hose);
-
-/*
- * Simple PCI access routines - these work from either the early PCI hose
- * or the 'real' one, created after U-Boot has memory available
- */
-unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where);
-unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where);
-unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where);
-
-void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
-void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
-void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
-
int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size);
diff --git a/arch/x86/include/asm/pirq_routing.h b/arch/x86/include/asm/pirq_routing.h
index ddc08e11d5..0afcb4615e 100644
--- a/arch/x86/include/asm/pirq_routing.h
+++ b/arch/x86/include/asm/pirq_routing.h
@@ -72,12 +72,13 @@ static inline int get_irq_slot_count(struct irq_routing_table *rt)
* Note: this function should be provided by the platform codes, as the
* implementation of interrupt router may be different.
*
+ * @dev: irq router's udevice
* @link: link number which represents a PIRQ
* @irq: the 8259 IRQ number
* @return: true if the irq is already routed to 8259 for a given link,
* false elsewise
*/
-bool pirq_check_irq_routed(int link, u8 irq);
+bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq);
/**
* pirq_translate_link() - Translate a link value
@@ -89,10 +90,11 @@ bool pirq_check_irq_routed(int link, u8 irq);
* Note: this function should be provided by the platform codes, as the
* implementation of interrupt router may be different.
*
+ * @dev: irq router's udevice
* @link: platform-specific link value
* @return: link number which represents a PIRQ
*/
-int pirq_translate_link(int link);
+int pirq_translate_link(struct udevice *dev, int link);
/**
* pirq_assign_irq() - Assign an IRQ to a PIRQ link
@@ -103,10 +105,11 @@ int pirq_translate_link(int link);
* Note: this function should be provided by the platform codes, as the
* implementation of interrupt router may be different.
*
+ * @dev: irq router's udevice
* @link: link number which represents a PIRQ
* @irq: IRQ to which the PIRQ is routed
*/
-void pirq_assign_irq(int link, u8 irq);
+void pirq_assign_irq(struct udevice *dev, int link, u8 irq);
/**
* pirq_route_irqs() - Route PIRQs to 8259 PIC
@@ -117,10 +120,11 @@ void pirq_assign_irq(int link, u8 irq);
* The configuration source is taken from a struct irq_info table, the format
* of which is defined in PIRQ routing table spec and PCI BIOS spec.
*
+ * @dev: irq router's udevice
* @irq: pointer to the base address of the struct irq_info
* @num: number of entries in the struct irq_info
*/
-void pirq_route_irqs(struct irq_info *irq, int num);
+void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num);
/**
* copy_pirq_routing_table() - Copy a PIRQ routing table
generated by cgit (git 2.34.1) at 2025-01-04 06:47:29 +0000