diff options
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/pch.h | 121 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/sandybridge.h | 107 | ||||
| -rw-r--r-- | arch/x86/include/asm/global_data.h | 8 | ||||
| -rw-r--r-- | arch/x86/include/asm/post.h | 2 |
4 files changed, 237 insertions, 1 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index c572f76037..290a737b02 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -14,9 +14,30 @@ #include <pci.h> +#define DEFAULT_GPIOBASE 0x0480 +#define DEFAULT_PMBASE 0x0500 + +#define SMBUS_IO_BASE 0x0400 + +#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) +#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) +#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0) +#define PCH_ME_DEV PCI_BDF(0, 0x16, 0) +#define PCH_PCIE_DEV_SLOT 28 + +#define PCH_DEV PCI_BDF(0, 0, 0) +#define PCH_VIDEO_DEV PCI_BDF(0, 2, 0) + /* PCI Configuration Space (D31:F0): LPC */ #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0xDC +#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ +#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_ROUT 0xb8 + #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ @@ -35,9 +56,35 @@ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) -#define DEFAULT_RCBA 0xfed1c000 +/* PCI Configuration Space (D31:F3): SMBus */ +#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3) +#define SMB_BASE 0x20 +#define HOSTC 0x40 +#define SMB_RCV_SLVA 0x09 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + /* Root Complex Register Block */ +#define DEFAULT_RCBA 0xfed1c000 #define RCB_REG(reg) (DEFAULT_RCBA + (reg)) #define PCH_RCBA_BASE 0xf0 @@ -95,6 +142,78 @@ #define FD2 0x3428 /* 32bit */ #define CG 0x341c /* 32bit */ +/* ICH7 PMBASE */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define PROC_CNT 0x10 +#define LV2 0x14 +#define LV3 0x15 +#define LV4 0x16 +#define PM2_CNT 0x50 /* mobile only */ +#define GPE0_STS 0x20 +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN 0x28 +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) +#define SMI_EN 0x30 +#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ +#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */ +#define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a +#define GPE_CNTL 0x42 +#define DEVACT_STS 0x44 +#define SS_CNT 0x50 +#define C3_RES 0x54 +#define TCO1_STS 0x64 +#define DMISCI_STS (1 << 9) +#define TCO2_STS 0x66 + /** * lpc_early_init() - set up LPC serial ports and other early things * diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h new file mode 100644 index 0000000000..a1072f21e8 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot file of the same name + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ACH_ASM_SANDYBRIDGE_H +#define _ACH_ASM_SANDYBRIDGE_H + +/* Chipset types */ +#define SANDYBRIDGE_MOBILE 0 +#define SANDYBRIDGE_DESKTOP 1 +#define SANDYBRIDGE_SERVER 2 + +/* Device ID for SandyBridge and IvyBridge */ +#define BASE_REV_SNB 0x00 +#define BASE_REV_IVB 0x50 +#define BASE_REV_MASK 0x50 + +/* SandyBridge CPU stepping */ +#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ +#define SNB_STEP_D1 (BASE_REV_SNB + 6) +#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ + +/* IvyBridge CPU stepping */ +#define IVB_STEP_A0 (BASE_REV_IVB + 0) +#define IVB_STEP_B0 (BASE_REV_IVB + 2) +#define IVB_STEP_C0 (BASE_REV_IVB + 4) +#define IVB_STEP_K0 (BASE_REV_IVB + 5) +#define IVB_STEP_D0 (BASE_REV_IVB + 6) + +/* Intel Enhanced Debug region must be 4MB */ +#define IED_SIZE 0x400000 + +/* Northbridge BARs */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_RCBABASE 0xfed1c000 +/* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define X60BAR 0x60 + +#define GGC 0x50 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_PEG60 (1 << 13) +#define DEVEN_IGD (1 << 4) +#define DEVEN_PEG10 (1 << 3) +#define DEVEN_PEG11 (1 << 2) +#define DEVEN_PEG12 (1 << 1) +#define DEVEN_HOST (1 << 0) + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define LAC 0x87 /* Legacy Access Control */ +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define TOM 0xa0 +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +/* Device 0:1.0 PCI configuration space (PCI Express) */ +#define BCTRL1 0x3e /* 16bit */ + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define MSAC 0x62 /* Multi Size Aperture Control */ +#define SWSCI 0xe8 /* SWSCI enable */ +#define ASLS 0xfc /* OpRegion Base */ + +/* + * MCHBAR + */ +#define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg)) + +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ + +void sandybridge_early_init(int chipset_type); + +#endif diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index d32987b7ec..ff9574c4cd 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -10,6 +10,13 @@ #ifndef __ASSEMBLY__ +enum pei_boot_mode_t { + PEI_BOOT_NONE = 0, + PEI_BOOT_SOFT_RESET, + PEI_BOOT_RESUME, + +}; + /* Architecture-specific global data */ struct arch_global_data { struct global_data *gd_addr; /* Location of Global Data */ @@ -25,6 +32,7 @@ struct arch_global_data { void *new_fdt; /* Relocated FDT */ uint32_t bist; /* Built-in self test value */ struct pci_controller *hose; /* PCI hose for early use */ + enum pei_boot_mode_t pei_boot_mode; }; #endif diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h index b203dc99b0..61dcda190a 100644 --- a/arch/x86/include/asm/post.h +++ b/arch/x86/include/asm/post.h @@ -25,6 +25,8 @@ #define POST_START_STACK 0x29 #define POST_START_DONE 0x2a #define POST_CPU_INIT 0x2b +#define POST_EARLY_INIT 0x2c +#define POST_CPU_INFO 0x2d /* Output a post code using al - value must be 0 to 0xff */ #ifdef __ASSEMBLY__ |