diff options
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 23 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/me.h | 45 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/pch.h | 27 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/sandybridge.h | 13 | ||||
| -rw-r--r-- | arch/x86/include/asm/cpu.h | 11 | ||||
| -rw-r--r-- | arch/x86/include/asm/irq.h | 19 | ||||
| -rw-r--r-- | arch/x86/include/asm/u-boot-x86.h | 2 |
7 files changed, 77 insertions, 63 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index fcdf6e26cb..e866580046 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -7,27 +7,6 @@ #ifndef _ASM_ARCH_BD82X6X_H #define _ASM_ARCH_BD82X6X_H -void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); -void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); -void bd82x6x_pci_init(pci_dev_t dev); -void bd82x6x_usb_ehci_init(pci_dev_t dev); -void bd82x6x_usb_xhci_init(pci_dev_t dev); -int gma_func0_init(struct udevice *dev, const void *blob, int node); -int bd82x6x_init(void); - -/** - * struct x86_cpu_priv - Information about a single CPU - * - * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is - * just a number representing the CPU core - * - * TODO: Move this to driver model once lifecycle is understood - */ -struct x86_cpu_priv { - int apic_id; - int start_err; -}; - -int model_206ax_init(struct x86_cpu_priv *cpu); +int gma_func0_init(struct udevice *dev); #endif diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h index 3a0809d6ec..eb1b73f92e 100644 --- a/arch/x86/include/asm/arch-ivybridge/me.h +++ b/arch/x86/include/asm/arch-ivybridge/me.h @@ -345,12 +345,47 @@ struct __packed me_fwcaps { u8 reserved[3]; }; -/* Defined in me_status.c for both romstage and ramstage */ +/** + * intel_me_status() - Check Intel Management Engine status + * + * struct hfs: Firmware status + * struct gmes: Management engine status + */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); -void intel_early_me_status(void); -int intel_early_me_init(void); -int intel_early_me_uma_size(void); -int intel_early_me_init_done(u8 status); +/** + * intel_early_me_status() - Check early Management Engine Status + * + * @me_dev: Management engine PCI device + */ +void intel_early_me_status(struct udevice *me_dev); + +/** + * intel_early_me_init() - Early Intel Management Engine init + * + * @me_dev: Management engine PCI device + * @return 0 if OK, -ve on error + */ +int intel_early_me_init(struct udevice *me_dev); + +/** + * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine + * + * @me_dev: Management engine PCI device + * @return UMA size if OK, -EINVAL on error + */ +int intel_early_me_uma_size(struct udevice *me_dev); + +/** + * intel_early_me_init_done() - Complete Intel Management Engine init + * + * @dev: Northbridge device + * @me_dev: Management engine PCI device + * @status: Status result (ME_INIT_...) + * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT + * if ME did not respond + */ +int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, + uint status); #endif diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 31437c8618..af3e8e747c 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -30,11 +30,6 @@ #define SMBUS_IO_BASE 0x0400 -int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); - #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 @@ -470,17 +465,23 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -int lpc_init(struct pci_controller *hose, pci_dev_t dev); -void lpc_enable(pci_dev_t dev); +/** + * pch_silicon_revision() - Read silicon device ID from the PCH + * + * @dev: PCH device + * @return silicon device ID + */ +int pch_silicon_type(struct udevice *dev); /** - * lpc_early_init() - set up LPC serial ports and other early things + * pch_pch_iobp_update() - Update a pch register * - * @blob: Device tree blob - * @node: Offset of LPC node - * @dev: PCH PCI device containing the LPC - * @return 0 if OK, -ve on error + * @dev: PCH device + * @address: Address to update + * @andvalue: Value to AND with existing value + * @orvalue: Value to OR with existing value */ -int lpc_early_init(const void *blob, int node, pci_dev_t dev); +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue); #endif diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index c9605258b5..d137d6786a 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -108,12 +108,15 @@ #define DMIBAR_REG(x) (DEFAULT_DMIBAR + x) -int bridge_silicon_revision(void); - -void northbridge_enable(pci_dev_t dev); -void northbridge_init(pci_dev_t dev); +/** + * bridge_silicon_revision() - Get the Northbridge revision + * + * @dev: Northbridge device + * @return revision ID (bits 3:0) and bridge ID (bits 7:4) + */ +int bridge_silicon_revision(struct udevice *dev); -void report_platform_info(void); +void report_platform_info(struct udevice *dev); void sandybridge_early_init(int chipset_type); diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index c70183ccef..18b0345986 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -45,6 +45,17 @@ enum { GDT_BASE_HIGH_MASK = 0xf, }; +/* + * System controllers in an x86 system. We mostly need to just find these and + * use them on PCI. At some point these might have their own uclass (e.g. + * UCLASS_VIDEO for the GMA device). + */ +enum { + X86_NONE, + X86_SYSCON_ME, /* Intel Management Engine */ + X86_SYSCON_GMA, /* Intel Graphics Media Accelerator */ +}; + struct cpuid_result { uint32_t eax; uint32_t ebx; diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 6697da3b85..5b9e673763 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -56,23 +56,10 @@ struct pirq_routing { #define PIRQ_BITMAP 0xdef8 /** - * cpu_irq_init() - Initialize CPU IRQ routing + * irq_router_common_init() - Perform common x86 interrupt init * - * This initializes some platform-specific registers related to IRQ routing, - * like configuring internal PCI devices to use which PCI interrupt pin, - * and which PCI interrupt pin is mapped to which PIRQ line. Note on some - * platforms, such IRQ routing might be hard-coded thus cannot configure. + * This creates the PIRQ routing table and routes the IRQs */ -void cpu_irq_init(void); - -/** - * pirq_init() - Initialize platform PIRQ routing - * - * This initializes the PIRQ routing on the platform and configures all PCI - * devices' interrupt line register to a working IRQ number on the 8259 PIC. - * - * @return 0 if OK, -ve on error - */ -int pirq_init(void); +int irq_router_common_init(struct udevice *dev); #endif /* _ARCH_IRQ_H_ */ diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index dbf8e95c1b..9c143caf67 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -77,8 +77,6 @@ uint64_t timer_get_tsc(void); void quick_ram_check(void); -int x86_init_cpus(void); - #define PCI_VGA_RAM_IMAGE_START 0xc0000 #endif /* _U_BOOT_I386_H_ */ |