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-rw-r--r--arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h10
-rw-r--r--arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h6
2 files changed, 13 insertions, 3 deletions
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
index 382cb79700..1c6c2479f0 100644
--- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
@@ -93,4 +93,14 @@ struct fspinit_rtbuf {
#define DIMM_SIDES_1RANKS 0
#define DIMM_SIDES_2RANKS 1
+#define LPE_MODE_DISABLED 0
+#define LPE_MODE_PCI 1
+#define LPE_MODE_ACPI 2
+
+#define LPSS_SIO_MODE_ACPI 0
+#define LPSS_SIO_MODE_PCI 1
+
+#define SCC_MODE_ACPI 0
+#define SCC_MODE_PCI 1
+
#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
index b083b6e5ec..8c07b3747f 100644
--- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -47,8 +47,8 @@ struct __packed upd_region {
uint8_t enable_azalia; /* Offset 0x002f */
uint32_t azalia_config_ptr; /* Offset 0x0030 */
uint8_t enable_xhci; /* Offset 0x0034 */
- uint8_t enable_lpe; /* Offset 0x0035 */
- uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */
+ uint8_t lpe_mode; /* Offset 0x0035 */
+ uint8_t lpss_sio_mode; /* Offset 0x0036 */
uint8_t enable_dma0; /* Offset 0x0037 */
uint8_t enable_dma1; /* Offset 0x0038 */
uint8_t enable_i2_c0; /* Offset 0x0039 */
@@ -67,7 +67,7 @@ struct __packed upd_region {
uint8_t reserved2[5]; /* Offset 0x0046 */
uint8_t mrc_debug_msg; /* Offset 0x004b */
uint8_t isp_enable; /* Offset 0x004c */
- uint8_t scc_enable_pci_mode; /* Offset 0x004d */
+ uint8_t scc_mode; /* Offset 0x004d */
uint8_t igd_render_standby; /* Offset 0x004e */
uint8_t txe_uma_enable; /* Offset 0x004f */
uint8_t os_selection; /* Offset 0x0050 */