diff options
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/apollolake/Makefile | 1 | ||||
| -rw-r--r-- | arch/x86/cpu/apollolake/fsp_bindings.c | 1805 | ||||
| -rw-r--r-- | arch/x86/cpu/apollolake/fsp_m.c | 169 | ||||
| -rw-r--r-- | arch/x86/cpu/apollolake/fsp_s.c | 430 | ||||
| -rw-r--r-- | arch/x86/cpu/coreboot/tables.c | 14 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 73 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h | 168 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h | 202 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/fsp_bindings.h | 110 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-coreboot/sysinfo.h | 2 | ||||
| -rw-r--r-- | arch/x86/include/asm/coreboot_tables.h | 11 | ||||
| -rw-r--r-- | arch/x86/lib/fsp2/fsp_init.c | 3 |
12 files changed, 2415 insertions, 573 deletions
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 578e15c4bf..3aa2a55676 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -10,6 +10,7 @@ obj-y += cpu_common.o ifndef CONFIG_TPL_BUILD obj-y += cpu.o obj-y += punit.o +obj-y += fsp_bindings.o ifdef CONFIG_SPL_BUILD obj-y += fsp_m.o endif diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c new file mode 100644 index 0000000000..9130af9ce0 --- /dev/null +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -0,0 +1,1805 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 B&R Industrial Automation GmbH - http://www.br-automation.com + */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <asm/arch/fsp_bindings.h> + +/** + * read_u8_prop() - Read an u8 property from devicetree (scalar or array) + * @node: Valid node reference to read property from + * @name: Name of the property to read from + * @count: If the property is expected to be an array, this is the + * number of expected elements + * Set to 0 if the property is expected to be a scalar + * @dst: Pointer to destination of where to save the value(s) read + * from devicetree + */ +static void read_u8_prop(ofnode node, char *name, size_t count, u8 *dst) +{ + u32 tmp; + const u8 *buf; + int ret; + + if (count == 0) { + ret = ofnode_read_u32(node, name, &tmp); + if (ret == 0) + *dst = tmp; + } else { + buf = ofnode_read_u8_array_ptr(node, name, count); + if (buf) + memcpy(dst, buf, count); + } +} + +/** + * read_u16_prop() - Read an u16 property from devicetree (scalar or array) + * @node: Valid node reference to read property from + * @name: Name of the property to read from + * @count: If the property is expected to be an array, this is the + * number of expected elements + * Set to 0 if the property is expected to be a scalar + * @dst: Pointer to destination of where to save the value(s) read + * from devicetree + * @return 0 on success, -ve on error + */ +static int read_u16_prop(ofnode node, char *name, size_t count, u16 *dst) +{ + u32 tmp; + u32 buf[32]; + int ret; + + if (ARRAY_SIZE(buf) < count) { + debug("ERROR: %s buffer to small!\n", __func__); + return -ENOSPC; + } + + if (count == 0) { + ret = ofnode_read_u32(node, name, &tmp); + if (ret == 0) + *dst = tmp; + } else { + ret = ofnode_read_u32_array(node, name, buf, count); + if (ret == 0) + for (int i = 0; i < count; i++) + dst[i] = buf[i]; + } + + return 0; +} + +/** + * read_u32_prop() - Read an u32 property from devicetree (scalar or array) + * @node: Valid node reference to read property from + * @name: Name of the property to read from + * @count: If the property is expected to be an array, this is the + * number of expected elements + * set to 0 if the property is expected to be a scalar + * @dst: Pointer to destination of where to save the value(s) read + * from devicetree + */ +static void read_u32_prop(ofnode node, char *name, size_t count, u32 *dst) +{ + if (count == 0) + ofnode_read_u32(node, name, dst); + else + ofnode_read_u32_array(node, name, dst, count); +} + +/** + * read_string_prop() - Read a string property from devicetree + * @node: Valid node reference to read property from + * @name: Name of the property to read from + * @count: Size of the destination buffer + * @dst: Pointer to destination of where to save the values read + * from devicetree + */ +static void read_string_prop(ofnode node, char *name, size_t count, char *dst) +{ + const char *string_buf; + + if (count > 0) { + string_buf = ofnode_read_string(node, name); + if (string_buf) + strlcpy(dst, string_buf, count); + } +} + +/** + * read_swizzle_prop() - Read a swizzle property from devicetree + * @node: Valid node reference to read property from + * @name: Name of the property to read from + * @count: Number of elements in the swizzle configuration + * @dst: pointer to destination of where to save the values read + * from devicetree + */ +static void read_swizzle_prop(ofnode node, char *name, size_t count, u8 *dst) +{ + const struct lpddr4_chan_swizzle_cfg *sch; + /* Number of bytes to copy per DQS */ + const size_t sz = DQ_BITS_PER_DQS; + const struct lpddr4_swizzle_cfg *swizzle_cfg; + + swizzle_cfg = (const struct lpddr4_swizzle_cfg *) + ofnode_read_u8_array_ptr(node, name, count); + + if (!swizzle_cfg) + return; + /* + * CH0_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH0B]; + memcpy(&dst[0 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS1], sz); + memcpy(&dst[1 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS0], sz); + memcpy(&dst[2 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS3], sz); + memcpy(&dst[3 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS2], sz); + + /* + * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH0A]; + memcpy(&dst[4 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS0], sz); + memcpy(&dst[5 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS1], sz); + memcpy(&dst[6 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS2], sz); + memcpy(&dst[7 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS3], sz); + + sch = &swizzle_cfg->phys[LP4_PHYS_CH1B]; + memcpy(&dst[8 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS1], sz); + memcpy(&dst[9 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS0], sz); + memcpy(&dst[10 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS3], sz); + memcpy(&dst[11 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS2], sz); + + /* + * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH1A]; + memcpy(&dst[12 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS0], sz); + memcpy(&dst[13 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS1], sz); + memcpy(&dst[14 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS2], sz); + memcpy(&dst[15 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS3], sz); +} + +/** + * fsp_update_config_from_dtb() - Read FSP config from devicetree node + * @node: Valid node reference to read property from + * @cfg: Pointer to FSP config structure + * @fsp_bindings: Binding describing which devicetree properties should + * be stored where in the FSP configuration structure + * The end of the list is declared by a NULL pointer in propname + * @return 0 on success, -ve on error + * + * This function reads the configuration for FSP from the provided + * devicetree node and saves it in the FSP configuration structure. + * Configuration options that are not present in the devicetree are + * left at their current value. + */ +__maybe_unused +static int fsp_update_config_from_dtb(ofnode node, u8 *cfg, + const struct fsp_binding *fsp_bindings) +{ + const struct fsp_binding *fspb; + int ret; + + for (int i = 0; fsp_bindings[i].propname; i++) { + fspb = &fsp_bindings[i]; + + switch (fspb->type) { + case FSP_UINT8: + read_u8_prop(node, fspb->propname, fspb->count, + &cfg[fspb->offset]); + break; + case FSP_UINT16: + ret = read_u16_prop(node, fspb->propname, fspb->count, + (u16 *)&cfg[fspb->offset]); + if (ret) + return ret; + break; + case FSP_UINT32: + read_u32_prop(node, fspb->propname, fspb->count, + (u32 *)&cfg[fspb->offset]); + break; + case FSP_STRING: + read_string_prop(node, fspb->propname, fspb->count, + (char *)&cfg[fspb->offset]); + break; + case FSP_LPDDR4_SWIZZLE: + read_swizzle_prop(node, fspb->propname, fspb->count, + &cfg[fspb->offset]); + break; + } + } + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) +const struct fsp_binding fsp_m_bindings[] = { + { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_m_config, serial_debug_port_address), + .propname = "fspm,serial-debug-port-address", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, serial_debug_port_type), + .propname = "fspm,serial-debug-port-type", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, serial_debug_port_device), + .propname = "fspm,serial-debug-port-device", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, serial_debug_port_stride_size), + .propname = "fspm,serial-debug-port-stride-size", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, mrc_fast_boot), + .propname = "fspm,mrc-fast-boot", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, igd), + .propname = "fspm,igd", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, igd_dvmt50_pre_alloc), + .propname = "fspm,igd-dvmt50-pre-alloc", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, igd_aperture_size), + .propname = "fspm,igd-aperture-size", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, gtt_size), + .propname = "fspm,gtt-size", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, primary_video_adaptor), + .propname = "fspm,primary-video-adaptor", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, package), + .propname = "fspm,package", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, profile), + .propname = "fspm,profile", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, memory_down), + .propname = "fspm,memory-down", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, ddr3_l_page_size), + .propname = "fspm,ddr3-l-page-size", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, ddr3_lasr), + .propname = "fspm,ddr3-lasr", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, scrambler_support), + .propname = "fspm,scrambler-support", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, interleaved_mode), + .propname = "fspm,interleaved-mode", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_m_config, channel_hash_mask), + .propname = "fspm,channel-hash-mask", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_m_config, slice_hash_mask), + .propname = "fspm,slice-hash-mask", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, channels_slices_enable), + .propname = "fspm,channels-slices-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, min_ref_rate2x_enable), + .propname = "fspm,min-ref-rate2x-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, dual_rank_support_enable), + .propname = "fspm,dual-rank-support-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, rmt_mode), + .propname = "fspm,rmt-mode", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_m_config, memory_size_limit), + .propname = "fspm,memory-size-limit", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_m_config, low_memory_max_value), + .propname = "fspm,low-memory-max-value", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_m_config, high_memory_max_value), + .propname = "fspm,high-memory-max-value", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, disable_fast_boot), + .propname = "fspm,disable-fast-boot", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, dimm0_spd_address), + .propname = "fspm,dimm0-spd-address", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, dimm1_spd_address), + .propname = "fspm,dimm1-spd-address", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[0].rank_enable), + .propname = "fspm,ch0-rank-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[0].device_width), + .propname = "fspm,ch0-device-width", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[0].dram_density), + .propname = "fspm,ch0-dram-density", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[0].option), + .propname = "fspm,ch0-option", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[0].odt_config), + .propname = "fspm,ch0-odt-config", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[0].tristate_clk1), + .propname = "fspm,ch0-tristate-clk1", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[0].mode2_n), + .propname = "fspm,ch0-mode2-n", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[0].odt_levels), + .propname = "fspm,ch0-odt-levels", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[1].rank_enable), + .propname = "fspm,ch1-rank-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[1].device_width), + .propname = "fspm,ch1-device-width", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[1].dram_density), + .propname = "fspm,ch1-dram-density", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[1].option), + .propname = "fspm,ch1-option", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[1].odt_config), + .propname = "fspm,ch1-odt-config", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[1].tristate_clk1), + .propname = "fspm,ch1-tristate-clk1", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[1].mode2_n), + .propname = "fspm,ch1-mode2-n", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[1].odt_levels), + .propname = "fspm,ch1-odt-levels", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[2].rank_enable), + .propname = "fspm,ch2-rank-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[2].device_width), + .propname = "fspm,ch2-device-width", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[2].dram_density), + .propname = "fspm,ch2-dram-density", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[2].option), + .propname = "fspm,ch2-option", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[2].odt_config), + .propname = "fspm,ch2-odt-config", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[2].tristate_clk1), + .propname = "fspm,ch2-tristate-clk1", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[2].mode2_n), + .propname = "fspm,ch2-mode2-n", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[2].odt_levels), + .propname = "fspm,ch2-odt-levels", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[3].rank_enable), + .propname = "fspm,ch3-rank-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[3].device_width), + .propname = "fspm,ch3-device-width", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[3].dram_density), + .propname = "fspm,ch3-dram-density", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[3].option), + .propname = "fspm,ch3-option", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[3].odt_config), + .propname = "fspm,ch3-odt-config", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[3].tristate_clk1), + .propname = "fspm,ch3-tristate-clk1", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[3].mode2_n), + .propname = "fspm,ch3-mode2-n", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, chan[3].odt_levels), + .propname = "fspm,ch3-odt-levels", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, rmt_check_run), + .propname = "fspm,rmt-check-run", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_m_config, + rmt_margin_check_scale_high_threshold), + .propname = "fspm,rmt-margin-check-scale-high-threshold", + }, { + .type = FSP_LPDDR4_SWIZZLE, + .offset = offsetof(struct fsp_m_config, ch_bit_swizzling), + .propname = "fspm,ch-bit-swizzling", + .count = SIZE_OF_MEMBER(struct fsp_m_config, ch_bit_swizzling) / + SIZE_OF_MEMBER(struct fsp_m_config, ch_bit_swizzling[0][0]) + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_m_config, msg_level_mask), + .propname = "fspm,msg-level-mask", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, pre_mem_gpio_table_pin_num), + .propname = "fspm,pre-mem-gpio-table-pin-num", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_m_config, + pre_mem_gpio_table_pin_num), + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_m_config, pre_mem_gpio_table_ptr), + .propname = "fspm,pre-mem-gpio-table-ptr", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, pre_mem_gpio_table_entry_num), + .propname = "fspm,pre-mem-gpio-table-entry-num", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, enhance_port8xh_decoding), + .propname = "fspm,enhance-port8xh-decoding", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, spd_write_enable), + .propname = "fspm,spd-write-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, mrc_data_saving), + .propname = "fspm,mrc-data-saving", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_m_config, oem_loading_base), + .propname = "fspm,oem-loading-base", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, oem_file_name), + .propname = "fspm,oem-file-name", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_m_config, oem_file_name), + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_m_config, mrc_boot_data_ptr), + .propname = "fspm,mrc-boot-data-ptr", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, e_mmc_trace_len), + .propname = "fspm,e-mmc-trace-len", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, skip_cse_rbp), + .propname = "fspm,skip-cse-rbp", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, npk_en), + .propname = "fspm,npk-en", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, fw_trace_en), + .propname = "fspm,fw-trace-en", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, fw_trace_destination), + .propname = "fspm,fw-trace-destination", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, recover_dump), + .propname = "fspm,recover-dump", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, msc0_wrap), + .propname = "fspm,msc0-wrap", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, msc1_wrap), + .propname = "fspm,msc1-wrap", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_m_config, msc0_size), + .propname = "fspm,msc0-size", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_m_config, msc1_size), + .propname = "fspm,msc1-size", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, pti_mode), + .propname = "fspm,pti-mode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, pti_training), + .propname = "fspm,pti-training", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, pti_speed), + .propname = "fspm,pti-speed", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, punit_mlvl), + .propname = "fspm,punit-mlvl", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, pmc_mlvl), + .propname = "fspm,pmc-mlvl", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, sw_trace_en), + .propname = "fspm,sw-trace-en", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, periodic_retraining_disable), + .propname = "fspm,periodic-retraining-disable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, enable_reset_system), + .propname = "fspm,enable-reset-system", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, enable_s3_heci2), + .propname = "fspm,enable-s3-heci2", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_m_config, variable_nvs_buffer_ptr), + .propname = "fspm,variable-nvs-buffer-ptr", + }, { + .propname = NULL + } +}; + +int fsp_m_update_config_from_dtb(ofnode node, struct fsp_m_config *cfg) +{ + return fsp_update_config_from_dtb(node, (u8 *)cfg, fsp_m_bindings); +} +#endif + +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +const struct fsp_binding fsp_s_bindings[] = { + { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, active_processor_cores), + .propname = "fsps,active-processor-cores", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, disable_core1), + .propname = "fsps,disable-core1", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, disable_core2), + .propname = "fsps,disable-core2", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, disable_core3), + .propname = "fsps,disable-core3", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, vmx_enable), + .propname = "fsps,vmx-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, proc_trace_mem_size), + .propname = "fsps,proc-trace-mem-size", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, proc_trace_enable), + .propname = "fsps,proc-trace-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, eist), + .propname = "fsps,eist", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, boot_p_state), + .propname = "fsps,boot-p-state", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, enable_cx), + .propname = "fsps,enable-cx", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, c1e), + .propname = "fsps,c1e", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, bi_proc_hot), + .propname = "fsps,bi-proc-hot", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pkg_c_state_limit), + .propname = "fsps,pkg-c-state-limit", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, c_state_auto_demotion), + .propname = "fsps,c-state-auto-demotion", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, c_state_un_demotion), + .propname = "fsps,c-state-un-demotion", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, max_core_c_state), + .propname = "fsps,max-core-c-state", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pkg_c_state_demotion), + .propname = "fsps,pkg-c-state-demotion", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pkg_c_state_un_demotion), + .propname = "fsps,pkg-c-state-un-demotion", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, turbo_mode), + .propname = "fsps,turbo-mode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hda_verb_table_entry_num), + .propname = "fsps,hda-verb-table-entry-num", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, hda_verb_table_ptr), + .propname = "fsps,hda-verb-table-ptr", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, p2sb_unhide), + .propname = "fsps,p2sb-unhide", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, ipu_en), + .propname = "fsps,ipu-en", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, ipu_acpi_mode), + .propname = "fsps,ipu-acpi-mode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, force_wake), + .propname = "fsps,force-wake", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, gtt_mm_adr), + .propname = "fsps,gtt-mm-adr", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, gm_adr), + .propname = "fsps,gm-adr", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pavp_lock), + .propname = "fsps,pavp-lock", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, graphics_freq_modify), + .propname = "fsps,graphics-freq-modify", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, graphics_freq_req), + .propname = "fsps,graphics-freq-req", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, graphics_video_freq), + .propname = "fsps,graphics-video-freq", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pm_lock), + .propname = "fsps,pm-lock", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dop_clock_gating), + .propname = "fsps,dop-clock-gating", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, unsolicited_attack_override), + .propname = "fsps,unsolicited-attack-override", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, wopcm_support), + .propname = "fsps,wopcm-support", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, wopcm_size), + .propname = "fsps,wopcm-size", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, power_gating), + .propname = "fsps,power-gating", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, unit_level_clock_gating), + .propname = "fsps,unit-level-clock-gating", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, fast_boot), + .propname = "fsps,fast-boot", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dyn_sr), + .propname = "fsps,dyn-sr", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sa_ipu_enable), + .propname = "fsps,sa-ipu-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pm_support), + .propname = "fsps,pm-support", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, enable_render_standby), + .propname = "fsps,enable-render-standby", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, logo_size), + .propname = "fsps,logo-size", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, logo_ptr), + .propname = "fsps,logo-ptr", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, graphics_config_ptr), + .propname = "fsps,graphics-config-ptr", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pavp_enable), + .propname = "fsps,pavp-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pavp_pr3), + .propname = "fsps,pavp-pr3", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, cd_clock), + .propname = "fsps,cd-clock", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pei_graphics_peim_init), + .propname = "fsps,pei-graphics-peim-init", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, write_protection_enable), + .propname = "fsps,write-protection-enable", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + write_protection_enable), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, read_protection_enable), + .propname = "fsps,read-protection-enable", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + read_protection_enable), + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, protected_range_limit), + .propname = "fsps,protected-range-limit", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + protected_range_limit), + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, protected_range_base), + .propname = "fsps,protected-range-base", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + protected_range_base), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, gmm), + .propname = "fsps,gmm", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_pgcb_clk_trunk), + .propname = "fsps,clk-gating-pgcb-clk-trunk", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_sb), + .propname = "fsps,clk-gating-sb", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_sb_clk_trunk), + .propname = "fsps,clk-gating-sb-clk-trunk", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_sb_clk_partition), + .propname = "fsps,clk-gating-sb-clk-partition", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_core), + .propname = "fsps,clk-gating-core", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_dma), + .propname = "fsps,clk-gating-dma", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_reg_access), + .propname = "fsps,clk-gating-reg-access", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_host), + .propname = "fsps,clk-gating-host", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_partition), + .propname = "fsps,clk-gating-partition", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, clk_gating_trunk), + .propname = "fsps,clk-gating-trunk", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hda_enable), + .propname = "fsps,hda-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dsp_enable), + .propname = "fsps,dsp-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pme), + .propname = "fsps,pme", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hd_audio_io_buffer_ownership), + .propname = "fsps,hd-audio-io-buffer-ownership", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hd_audio_io_buffer_voltage), + .propname = "fsps,hd-audio-io-buffer-voltage", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hd_audio_vc_type), + .propname = "fsps,hd-audio-vc-type", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hd_audio_link_frequency), + .propname = "fsps,hd-audio-link-frequency", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hd_audio_i_disp_link_frequency), + .propname = "fsps,hd-audio-i-disp-link-frequency", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hd_audio_i_disp_link_tmode), + .propname = "fsps,hd-audio-i-disp-link-tmode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dsp_endpoint_dmic), + .propname = "fsps,dsp-endpoint-dmic", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dsp_endpoint_bluetooth), + .propname = "fsps,dsp-endpoint-bluetooth", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dsp_endpoint_i2s_skp), + .propname = "fsps,dsp-endpoint-i2s-skp", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dsp_endpoint_i2s_hp), + .propname = "fsps,dsp-endpoint-i2s-hp", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, audio_ctl_pwr_gate), + .propname = "fsps,audio-ctl-pwr-gate", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, audio_dsp_pwr_gate), + .propname = "fsps,audio-dsp-pwr-gate", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, mmt), + .propname = "fsps,mmt", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hmt), + .propname = "fsps,hmt", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hd_audio_pwr_gate), + .propname = "fsps,hd-audio-pwr-gate", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hd_audio_clk_gate), + .propname = "fsps,hd-audio-clk-gate", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, dsp_feature_mask), + .propname = "fsps,dsp-feature-mask", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, dsp_pp_module_mask), + .propname = "fsps,dsp-pp-module-mask", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, bios_cfg_lock_down), + .propname = "fsps,bios-cfg-lock-down", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hpet), + .propname = "fsps,hpet", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hpet_bdf_valid), + .propname = "fsps,hpet-bdf-valid", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hpet_bus_number), + .propname = "fsps,hpet-bus-number", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hpet_device_number), + .propname = "fsps,hpet-device-number", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hpet_function_number), + .propname = "fsps,hpet-function-number", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, io_apic_bdf_valid), + .propname = "fsps,io-apic-bdf-valid", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, io_apic_bus_number), + .propname = "fsps,io-apic-bus-number", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, io_apic_device_number), + .propname = "fsps,io-apic-device-number", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, io_apic_function_number), + .propname = "fsps,io-apic-function-number", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, io_apic_entry24_119), + .propname = "fsps,io-apic-entry24-119", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, io_apic_id), + .propname = "fsps,io-apic-id", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, io_apic_range_select), + .propname = "fsps,io-apic-range-select", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, ish_enable), + .propname = "fsps,ish-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, bios_interface), + .propname = "fsps,bios-interface", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, bios_lock), + .propname = "fsps,bios-lock", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, spi_eiss), + .propname = "fsps,spi-eiss", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, bios_lock_sw_smi_number), + .propname = "fsps,bios-lock-sw-smi-number", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, lpss_s0ix_enable), + .propname = "fsps,lpss-s0ix-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, i2c_clk_gate_cfg), + .propname = "fsps,i2c-clk-gate-cfg", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, i2c_clk_gate_cfg), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hsuart_clk_gate_cfg), + .propname = "fsps,hsuart-clk-gate-cfg", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, hsuart_clk_gate_cfg), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, spi_clk_gate_cfg), + .propname = "fsps,spi-clk-gate-cfg", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, spi_clk_gate_cfg), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, i2c0_enable), + .propname = "fsps,i2c0-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, i2c1_enable), + .propname = "fsps,i2c1-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, i2c2_enable), + .propname = "fsps,i2c2-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, i2c3_enable), + .propname = "fsps,i2c3-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, i2c4_enable), + .propname = "fsps,i2c4-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, i2c5_enable), + .propname = "fsps,i2c5-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, i2c6_enable), + .propname = "fsps,i2c6-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, i2c7_enable), + .propname = "fsps,i2c7-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hsuart0_enable), + .propname = "fsps,hsuart0-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hsuart1_enable), + .propname = "fsps,hsuart1-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hsuart2_enable), + .propname = "fsps,hsuart2-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hsuart3_enable), + .propname = "fsps,hsuart3-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, spi0_enable), + .propname = "fsps,spi0-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, spi1_enable), + .propname = "fsps,spi1-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, spi2_enable), + .propname = "fsps,spi2-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, os_dbg_enable), + .propname = "fsps,os-dbg-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dci_en), + .propname = "fsps,dci-en", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, + uart2_kernel_debug_base_address), + .propname = "fsps,uart2-kernel-debug-base-address", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_clock_gating_disabled), + .propname = "fsps,pcie-clock-gating-disabled", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_root_port8xh_decode), + .propname = "fsps,pcie-root-port8xh-decode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie8xh_decode_port_index), + .propname = "fsps,pcie8xh-decode-port-index", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + pcie_root_port_peer_memory_write_enable), + .propname = "fsps,pcie-root-port-peer-memory-write-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_aspm_sw_smi_number), + .propname = "fsps,pcie-aspm-sw-smi-number", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_root_port_en), + .propname = "fsps,pcie-root-port-en", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_root_port_en), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_hide), + .propname = "fsps,pcie-rp-hide", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_hide), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_slot_implemented), + .propname = "fsps,pcie-rp-slot-implemented", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_slot_implemented), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_hot_plug), + .propname = "fsps,pcie-rp-hot-plug", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_hot_plug), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_pm_sci), + .propname = "fsps,pcie-rp-pm-sci", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_pm_sci), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_ext_sync), + .propname = "fsps,pcie-rp-ext-sync", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_ext_sync), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + pcie_rp_transmitter_half_swing), + .propname = "fsps,pcie-rp-transmitter-half-swing", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_transmitter_half_swing), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_acs_enabled), + .propname = "fsps,pcie-rp-acs-enabled", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_acs_enabled), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_clk_req_supported), + .propname = "fsps,pcie-rp-clk-req-supported", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_clk_req_supported), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_clk_req_number), + .propname = "fsps,pcie-rp-clk-req-number", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_clk_req_number), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_clk_req_detect), + .propname = "fsps,pcie-rp-clk-req-detect", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_clk_req_detect), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, advanced_error_reporting), + .propname = "fsps,advanced-error-reporting", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + advanced_error_reporting), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pme_interrupt), + .propname = "fsps,pme-interrupt", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pme_interrupt), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, unsupported_request_report), + .propname = "fsps,unsupported-request-report", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + unsupported_request_report), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, fatal_error_report), + .propname = "fsps,fatal-error-report", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, fatal_error_report), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, no_fatal_error_report), + .propname = "fsps,no-fatal-error-report", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + no_fatal_error_report), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, correctable_error_report), + .propname = "fsps,correctable-error-report", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + correctable_error_report), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + system_error_on_fatal_error), + .propname = "fsps,system-error-on-fatal-error", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + system_error_on_fatal_error), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + system_error_on_non_fatal_error), + .propname = "fsps,system-error-on-non-fatal-error", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + system_error_on_non_fatal_error), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + system_error_on_correctable_error), + .propname = "fsps,system-error-on-correctable-error", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + system_error_on_correctable_error), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_speed), + .propname = "fsps,pcie-rp-speed", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_speed), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, physical_slot_number), + .propname = "fsps,physical-slot-number", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + physical_slot_number), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_completion_timeout), + .propname = "fsps,pcie-rp-completion-timeout", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_completion_timeout), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, ptm_enable), + .propname = "fsps,ptm-enable", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, ptm_enable), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_aspm), + .propname = "fsps,pcie-rp-aspm", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_aspm), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_l1_substates), + .propname = "fsps,pcie-rp-l1-substates", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_l1_substates), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_ltr_enable), + .propname = "fsps,pcie-rp-ltr-enable", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_ltr_enable), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_ltr_config_lock), + .propname = "fsps,pcie-rp-ltr-config-lock", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_ltr_config_lock), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pme_b0_s5_dis), + .propname = "fsps,pme-b0-s5-dis", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pci_clock_run), + .propname = "fsps,pci-clock-run", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, timer8254_clk_setting), + .propname = "fsps,timer8254-clk-setting", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, enable_sata), + .propname = "fsps,enable-sata", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_mode), + .propname = "fsps,sata-mode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_salp_support), + .propname = "fsps,sata-salp-support", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_pwr_opt_enable), + .propname = "fsps,sata-pwr-opt-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, e_sata_speed_limit), + .propname = "fsps,e-sata-speed-limit", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, speed_limit), + .propname = "fsps,speed-limit", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_enable), + .propname = "fsps,sata-ports-enable", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_enable), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_dev_slp), + .propname = "fsps,sata-ports-dev-slp", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_dev_slp), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_hot_plug), + .propname = "fsps,sata-ports-hot-plug", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_hot_plug), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_interlock_sw), + .propname = "fsps,sata-ports-interlock-sw", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + sata_ports_interlock_sw), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_external), + .propname = "fsps,sata-ports-external", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_external), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_spin_up), + .propname = "fsps,sata-ports-spin-up", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_spin_up), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_solid_state_drive), + .propname = "fsps,sata-ports-solid-state-drive", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + sata_ports_solid_state_drive), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_enable_dito_config), + .propname = "fsps,sata-ports-enable-dito-config", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + sata_ports_enable_dito_config), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_dm_val), + .propname = "fsps,sata-ports-dm-val", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_dm_val), + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, sata_ports_dito_val), + .propname = "fsps,sata-ports-dito-val", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_dito_val), + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, sub_system_vendor_id), + .propname = "fsps,sub-system-vendor-id", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, sub_system_id), + .propname = "fsps,sub-system-id", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, crid_settings), + .propname = "fsps,crid-settings", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, reset_select), + .propname = "fsps,reset-select", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sdcard_enabled), + .propname = "fsps,sdcard-enabled", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, e_mmc_enabled), + .propname = "fsps,e-mmc-enabled", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, e_mmc_host_max_speed), + .propname = "fsps,e-mmc-host-max-speed", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, ufs_enabled), + .propname = "fsps,ufs-enabled", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sdio_enabled), + .propname = "fsps,sdio-enabled", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, gpp_lock), + .propname = "fsps,gpp-lock", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sirq_enable), + .propname = "fsps,sirq-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sirq_mode), + .propname = "fsps,sirq-mode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, start_frame_pulse), + .propname = "fsps,start-frame-pulse", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, smbus_enable), + .propname = "fsps,smbus-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, arp_enable), + .propname = "fsps,arp-enable", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, num_rsvd_smbus_addresses), + .propname = "fsps,num-rsvd-smbus-addresses", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, rsvd_smbus_address_table), + .propname = "fsps,rsvd-smbus-address-table", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + rsvd_smbus_address_table), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, disable_compliance_mode), + .propname = "fsps,disable-compliance-mode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, usb_per_port_ctl), + .propname = "fsps,usb-per-port-ctl", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, usb30_mode), + .propname = "fsps,usb30-mode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, port_usb20_enable), + .propname = "fsps,port-usb20-enable", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, port_usb20_enable), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, port_us20b_over_current_pin), + .propname = "fsps,port-us20b-over-current-pin", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + port_us20b_over_current_pin), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, usb_otg), + .propname = "fsps,usb-otg", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hsic_support_enable), + .propname = "fsps,hsic-support-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, port_usb30_enable), + .propname = "fsps,port-usb30-enable", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, port_usb30_enable), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, port_us30b_over_current_pin), + .propname = "fsps,port-us30b-over-current-pin", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + port_us30b_over_current_pin), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, ssic_port_enable), + .propname = "fsps,ssic-port-enable", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, ssic_port_enable), + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, dlane_pwr_gating), + .propname = "fsps,dlane-pwr-gating", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, vtd_enable), + .propname = "fsps,vtd-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, lock_down_global_smi), + .propname = "fsps,lock-down-global-smi", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, reset_wait_timer), + .propname = "fsps,reset-wait-timer", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, rtc_lock), + .propname = "fsps,rtc-lock", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_test_mode), + .propname = "fsps,sata-test-mode", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, ssic_rate), + .propname = "fsps,ssic-rate", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, ssic_rate), + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, dynamic_power_gating), + .propname = "fsps,dynamic-power-gating", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, pcie_rp_ltr_max_snoop_latency), + .propname = "fsps,pcie-rp-ltr-max-snoop-latency", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_ltr_max_snoop_latency), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + pcie_rp_snoop_latency_override_mode), + .propname = "fsps,pcie-rp-snoop-latency-override-mode", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_snoop_latency_override_mode), + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, + pcie_rp_snoop_latency_override_value), + .propname = "fsps,pcie-rp-snoop-latency-override-value", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_snoop_latency_override_value), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + pcie_rp_snoop_latency_override_multiplier), + .propname = "fsps,pcie-rp-snoop-latency-override-multiplier", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_snoop_latency_override_multiplier), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, skip_mp_init), + .propname = "fsps,skip-mp-init", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dci_auto_detect), + .propname = "fsps,dci-auto-detect", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, + pcie_rp_ltr_max_non_snoop_latency), + .propname = "fsps,pcie-rp-ltr-max-non-snoop-latency", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_ltr_max_non_snoop_latency), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + pcie_rp_non_snoop_latency_override_mode), + .propname = "fsps,pcie-rp-non-snoop-latency-override-mode", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_non_snoop_latency_override_mode), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, tco_timer_halt_lock), + .propname = "fsps,tco-timer-halt-lock", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pwr_btn_override_period), + .propname = "fsps,pwr-btn-override-period", + }, { + .type = FSP_UINT16, + .offset = offsetof(struct fsp_s_config, + pcie_rp_non_snoop_latency_override_value), + .propname = "fsps,pcie-rp-non-snoop-latency-override-value", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_non_snoop_latency_override_value), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + pcie_rp_non_snoop_latency_override_multiplier), + .propname = "fsps,pcie-rp-non-snoop-latency-override-multiplier", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_non_snoop_latency_override_multiplier), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_slot_power_limit_scale), + .propname = "fsps,pcie-rp-slot-power-limit-scale", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_slot_power_limit_scale), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_slot_power_limit_value), + .propname = "fsps,pcie-rp-slot-power-limit-value", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_slot_power_limit_value), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, disable_native_power_button), + .propname = "fsps,disable-native-power-button", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, power_butter_debounce_mode), + .propname = "fsps,power-butter-debounce-mode", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdio_tx_cmd_cntl), + .propname = "fsps,sdio-tx-cmd-cntl", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdio_tx_data_cntl1), + .propname = "fsps,sdio-tx-data-cntl1", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdio_tx_data_cntl2), + .propname = "fsps,sdio-tx-data-cntl2", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdio_rx_cmd_data_cntl1), + .propname = "fsps,sdio-rx-cmd-data-cntl1", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdio_rx_cmd_data_cntl2), + .propname = "fsps,sdio-rx-cmd-data-cntl2", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdcard_tx_cmd_cntl), + .propname = "fsps,sdcard-tx-cmd-cntl", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdcard_tx_data_cntl1), + .propname = "fsps,sdcard-tx-data-cntl1", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdcard_tx_data_cntl2), + .propname = "fsps,sdcard-tx-data-cntl2", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdcard_rx_cmd_data_cntl1), + .propname = "fsps,sdcard-rx-cmd-data-cntl1", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdcard_rx_strobe_cntl), + .propname = "fsps,sdcard-rx-strobe-cntl", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, sdcard_rx_cmd_data_cntl2), + .propname = "fsps,sdcard-rx-cmd-data-cntl2", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, emmc_tx_cmd_cntl), + .propname = "fsps,emmc-tx-cmd-cntl", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, emmc_tx_data_cntl1), + .propname = "fsps,emmc-tx-data-cntl1", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, emmc_tx_data_cntl2), + .propname = "fsps,emmc-tx-data-cntl2", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, emmc_rx_cmd_data_cntl1), + .propname = "fsps,emmc-rx-cmd-data-cntl1", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, emmc_rx_strobe_cntl), + .propname = "fsps,emmc-rx-strobe-cntl", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, emmc_rx_cmd_data_cntl2), + .propname = "fsps,emmc-rx-cmd-data-cntl2", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, emmc_master_sw_cntl), + .propname = "fsps,emmc-master-sw-cntl", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pcie_rp_selectable_deemphasis), + .propname = "fsps,pcie-rp-selectable-deemphasis", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + pcie_rp_selectable_deemphasis), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, monitor_mwait_enable), + .propname = "fsps,monitor-mwait-enable", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, hd_audio_dsp_uaa_compliance), + .propname = "fsps,hd-audio-dsp-uaa-compliance", + }, { + .type = FSP_UINT32, + .offset = offsetof(struct fsp_s_config, ipc), + .propname = "fsps,ipc", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, ipc), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, sata_ports_disable_dynamic_pg), + .propname = "fsps,sata-ports-disable-dynamic-pg", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + sata_ports_disable_dynamic_pg), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, init_s3_cpu), + .propname = "fsps,init-s3-cpu", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, skip_punit_init), + .propname = "fsps,skip-punit-init", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, port_usb20_per_port_tx_pe_half), + .propname = "fsps,port-usb20-per-port-tx-pe-half", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + port_usb20_per_port_tx_pe_half), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, port_usb20_per_port_pe_txi_set), + .propname = "fsps,port-usb20-per-port-pe-txi-set", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + port_usb20_per_port_pe_txi_set), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, port_usb20_per_port_txi_set), + .propname = "fsps,port-usb20-per-port-txi-set", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + port_usb20_per_port_txi_set), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, port_usb20_hs_skew_sel), + .propname = "fsps,port-usb20-hs-skew-sel", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + port_usb20_hs_skew_sel), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + port_usb20_i_usb_tx_emphasis_en), + .propname = "fsps,port-usb20-i-usb-tx-emphasis-en", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + port_usb20_i_usb_tx_emphasis_en), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, + port_usb20_per_port_rxi_set), + .propname = "fsps,port-usb20-per-port-rxi-set", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + port_usb20_per_port_rxi_set), + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, port_usb20_hs_npre_drv_sel), + .propname = "fsps,port-usb20-hs-npre-drv-sel", + .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, + port_usb20_hs_npre_drv_sel), + }, { + .propname = NULL + } +}; + +int fsp_s_update_config_from_dtb(ofnode node, struct fsp_s_config *cfg) +{ + return fsp_update_config_from_dtb(node, (u8 *)cfg, fsp_s_bindings); +} +#endif diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index 56ce59dc70..1301100cd5 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -8,184 +8,27 @@ #include <dm.h> #include <log.h> #include <asm/arch/iomap.h> -#include <asm/arch/fsp/fsp_configs.h> -#include <asm/arch/fsp/fsp_m_upd.h> +#include <asm/arch/fsp_bindings.h> #include <asm/fsp2/fsp_internal.h> #include <dm/uclass-internal.h> -/* - * ODT settings: - * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B, - * choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A - * and LOW for ODT_B, choose ODT_A_B_HIGH_LOW. - * - * Note that the enum values correspond to the interpreted UPD fields - * within Ch[3:0]_OdtConfig parameters. - */ -enum { - ODT_A_B_HIGH_LOW = 0 << 1, - ODT_A_B_HIGH_HIGH = 1 << 1, - N_WR_24 = 1 << 5, -}; - -/* - * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. - * There are four physical LPDDR4 channels, each 32-bits wide. There are two - * logical channels using two physical channels together to form a 64-bit - * interface to memory for each logical channel. - */ - -enum { - LP4_PHYS_CH0A, - LP4_PHYS_CH0B, - LP4_PHYS_CH1A, - LP4_PHYS_CH1B, - - LP4_NUM_PHYS_CHANNELS, -}; - -/* - * The DQs within a physical channel can be bit-swizzled within each byte. - * Within a channel the bytes can be swapped, but the DQs need to be routed - * with the corresponding DQS (strobe). - */ -enum { - LP4_DQS0, - LP4_DQS1, - LP4_DQS2, - LP4_DQS3, - - LP4_NUM_BYTE_LANES, - DQ_BITS_PER_DQS = 8, -}; - -/* Provide bit swizzling per DQS and byte swapping within a channel */ -struct lpddr4_chan_swizzle_cfg { - u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS]; -}; - -struct lpddr4_swizzle_cfg { - struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS]; -}; - -static void setup_sdram(struct fsp_m_config *cfg, - const struct lpddr4_swizzle_cfg *swizzle_cfg) -{ - const struct lpddr4_chan_swizzle_cfg *sch; - /* Number of bytes to copy per DQS */ - const size_t sz = DQ_BITS_PER_DQS; - int chan; - - cfg->memory_down = 1; - cfg->scrambler_support = 1; - cfg->channel_hash_mask = 0x36; - cfg->slice_hash_mask = 9; - cfg->interleaved_mode = 2; - cfg->channels_slices_enable = 0; - cfg->min_ref_rate2x_enable = 0; - cfg->dual_rank_support_enable = 1; - - /* LPDDR4 is memory down so no SPD addresses */ - cfg->dimm0_spd_address = 0; - cfg->dimm1_spd_address = 0; - - for (chan = 0; chan < 4; chan++) { - struct fsp_ram_channel *ch = &cfg->chan[chan]; - - ch->rank_enable = 1; - ch->device_width = 1; - ch->dram_density = 2; - ch->option = 3; - ch->odt_config = ODT_A_B_HIGH_HIGH; - } - - /* - * CH0_DQB byte lanes in the bit swizzle configuration field are - * not 1:1. The mapping within the swizzling field is: - * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] - * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] - * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] - * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] - */ - sch = &swizzle_cfg->phys[LP4_PHYS_CH0B]; - memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz); - memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz); - - /* - * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. - */ - sch = &swizzle_cfg->phys[LP4_PHYS_CH0A]; - memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz); - memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz); - - sch = &swizzle_cfg->phys[LP4_PHYS_CH1B]; - memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz); - memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz); - - /* - * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. - */ - sch = &swizzle_cfg->phys[LP4_PHYS_CH1A]; - memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz); - memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz); -} - int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) { struct fsp_m_config *cfg = &upd->config; struct fspm_arch_upd *arch = &upd->arch; + ofnode node; arch->nvs_buffer_ptr = NULL; prepare_mrc_cache(upd); arch->stack_base = (void *)0xfef96000; arch->boot_loader_tolum_size = 0; - arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION; - cfg->serial_debug_port_type = 2; - cfg->serial_debug_port_device = 2; - cfg->serial_debug_port_stride_size = 2; - cfg->serial_debug_port_address = 0; - cfg->package = 1; - /* Don't enforce a memory size limit */ - cfg->memory_size_limit = 0; - cfg->low_memory_max_value = 2048; /* 2 GB */ - /* No restrictions on memory above 4GiB */ - cfg->high_memory_max_value = 0; + node = dev_ofnode(dev); + if (!ofnode_valid(node)) + return log_msg_ret("fsp-m settings", -ENOENT); - /* Always default to attempt to use saved training data */ - cfg->disable_fast_boot = 0; - - const u8 *swizzle_data; - - swizzle_data = dev_read_u8_array_ptr(dev, "lpddr4-swizzle", - LP4_NUM_BYTE_LANES * - DQ_BITS_PER_DQS * - LP4_NUM_PHYS_CHANNELS); - if (!swizzle_data) - return log_msg_ret("Cannot read swizzel data", -EINVAL); - - setup_sdram(cfg, (struct lpddr4_swizzle_cfg *)swizzle_data); - - cfg->pre_mem_gpio_table_ptr = 0; - - cfg->profile = 0xb; - cfg->msg_level_mask = 0; - - /* other */ - cfg->skip_cse_rbp = 1; - cfg->periodic_retraining_disable = 0; - cfg->enable_s3_heci2 = 0; - - return 0; + return fsp_m_update_config_from_dtb(node, cfg); } /* diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 3e303f8f32..767ddfe680 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -24,418 +24,48 @@ #include <asm/arch/fsp/fsp_configs.h> #include <asm/arch/fsp/fsp_s_upd.h> #include <linux/bitops.h> +#include <asm/arch/fsp_bindings.h> #define PCH_P2SB_E0 0xe0 #define HIDE_BIT BIT(0) -#define INTEL_GSPI_MAX 3 -#define MAX_USB2_PORTS 8 - -enum { - CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ - CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ -}; - -/* Serial IRQ control. SERIRQ_QUIET is the default (0) */ -enum serirq_mode { - SERIRQ_QUIET, - SERIRQ_CONTINUOUS, - SERIRQ_OFF, -}; - -struct gspi_cfg { - /* Bus speed in MHz */ - u32 speed_mhz; - /* Bus should be enabled prior to ramstage with temporary base */ - u8 early_init; -}; - -/* - * This structure will hold data required by common blocks. - * These are soc specific configurations which will be filled by soc. - * We'll fill this structure once during init and use the data in common block. - */ -struct soc_intel_common_config { - int chipset_lockdown; - struct gspi_cfg gspi[INTEL_GSPI_MAX]; -}; - -enum pnp_settings { - PNP_PERF, - PNP_POWER, - PNP_PERF_POWER, -}; - -struct usb2_eye_per_port { - u8 per_port_tx_pe_half; - u8 per_port_pe_txi_set; - u8 per_port_txi_set; - u8 hs_skew_sel; - u8 usb_tx_emphasis_en; - u8 per_port_rxi_set; - u8 hs_npre_drv_sel; - u8 override_en; -}; - -struct apl_config { - /* Common structure containing soc config data required by common code*/ - struct soc_intel_common_config common_soc_config; - - /* - * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has - * four CLKREQ inputs, but six root ports. Root ports without an - * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" - */ - u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS]; - - /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */ - u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS]; - - /* De-emphasis enable configuration for each PCIe root port */ - u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS]; - - /* - * [14:8] DDR mode Number of dealy elements.Each = 125pSec. - * [6:0] SDR mode Number of dealy elements.Each = 125pSec. - */ - u32 emmc_tx_cmd_cntl; - - /* - * [14:8] HS400 mode Number of dealy elements.Each = 125pSec. - * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec. - */ - u32 emmc_tx_data_cntl1; - - /* - * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. - * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. - * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. - * [6:0] SDR12/Compatibility mode Number of dealy elements. - * Each = 125pSec. - */ - u32 emmc_tx_data_cntl2; - - /* - * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. - * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. - * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. - * [6:0] SDR12/Compatibility mode Number of dealy elements. - * Each = 125pSec. - */ - u32 emmc_rx_cmd_data_cntl1; - - /* - * [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec. - * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec. - */ - u32 emmc_rx_strobe_cntl; - - /* - * [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec. - * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec. - */ - u32 emmc_rx_cmd_data_cntl2; - - /* Select the eMMC max speed allowed */ - u32 emmc_host_max_speed; - - /* Specifies on which IRQ the SCI will internally appear */ - u32 sci_irq; - - /* Configure serial IRQ (SERIRQ) line */ - enum serirq_mode serirq_mode; - - /* Configure LPSS S0ix Enable */ - bool lpss_s0ix_enable; - - /* Enable DPTF support */ - bool dptf_enable; - - /* TCC activation offset value in degrees Celsius */ - int tcc_offset; - - /* - * Configure Audio clk gate and power gate - * IOSF-SB port ID 92 offset 0x530 [5] and [3] - */ - bool hdaudio_clk_gate_enable; - bool hdaudio_pwr_gate_enable; - bool hdaudio_bios_config_lockdown; - - /* SLP S3 minimum assertion width */ - int slp_s3_assertion_width_usecs; - - /* GPIO pin for PERST_0 */ - u32 prt0_gpio; - - /* USB2 eye diagram settings per port */ - struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS]; - - /* GPIO SD card detect pin */ - unsigned int sdcard_cd_gpio; - - /* - * PRMRR size setting with three options - * 0x02000000 - 32MiB - * 0x04000000 - 64MiB - * 0x08000000 - 128MiB - */ - u32 PrmrrSize; - - /* - * Enable SGX feature. - * Enabling SGX feature is 2 step process, - * (1) set sgx_enable = 1 - * (2) set PrmrrSize to supported size - */ - bool sgx_enable; - - /* - * Select PNP Settings. - * (0) Performance, - * (1) Power - * (2) Power & Performance - */ - enum pnp_settings pnp_settings; - - /* - * PMIC PCH_PWROK delay configuration - IPC Configuration - * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address - * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) - */ - u32 pmic_pmc_ipc_ctrl; - - /* - * Options to disable XHCI Link Compliance Mode. Default is FALSE to not - * disable Compliance Mode. Set TRUE to disable Compliance Mode. - * 0:FALSE(Default), 1:True. - */ - bool disable_compliance_mode; - - /* - * Options to change USB3 ModPhy setting for the Integrated Filter (IF) - * value. Default is 0 to not changing default IF value (0x12). Set - * value with the range from 0x01 to 0xff to change IF value. - */ - u32 mod_phy_if_value; - - /* - * Options to bump USB3 LDO voltage. Default is FALSE to not increasing - * LDO voltage. Set TRUE to increase LDO voltage with 40mV. - * 0:FALSE (default), 1:True. - */ - bool mod_phy_voltage_bump; - - /* - * Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting - * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage - * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16) - * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]: - * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default). - */ - u32 pmic_vdd2_voltage; - - /* Option to enable VTD feature */ - bool enable_vtd; -}; - -static int get_config(struct udevice *dev, struct apl_config *apl) -{ - const u8 *ptr; - ofnode node; - u32 emmc[4]; - int ret; - - memset(apl, '\0', sizeof(*apl)); - - node = dev_read_subnode(dev, "fsp-s"); - if (!ofnode_valid(node)) - return log_msg_ret("fsp-s settings", -ENOENT); - - ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin", - MAX_PCIE_PORTS); - if (!ptr) - return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL); - memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS); - - ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio); - if (ret) - return log_msg_ret("prt0-gpio", ret); - ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio); - if (ret) - return log_msg_ret("sdcard-cd-gpio", ret); - - ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc)); - if (ret) - return log_msg_ret("emmc", ret); - apl->emmc_tx_data_cntl1 = emmc[0]; - apl->emmc_tx_data_cntl2 = emmc[1]; - apl->emmc_rx_cmd_data_cntl1 = emmc[2]; - apl->emmc_rx_cmd_data_cntl2 = emmc[3]; - - apl->dptf_enable = ofnode_read_bool(node, "dptf-enable"); - - apl->hdaudio_clk_gate_enable = ofnode_read_bool(node, - "hdaudio-clk-gate-enable"); - apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node, - "hdaudio-pwr-gate-enable"); - apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node, - "hdaudio-bios-config-lockdown"); - apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable"); - - /* Santa */ - apl->usb2eye[1].per_port_pe_txi_set = 7; - apl->usb2eye[1].per_port_txi_set = 2; - - return 0; -} - -static void apl_fsp_silicon_init_params_cb(struct apl_config *apl, - struct fsp_s_config *cfg) -{ - u8 port; - - for (port = 0; port < MAX_USB2_PORTS; port++) { - if (apl->usb2eye[port].per_port_tx_pe_half) - cfg->port_usb20_per_port_tx_pe_half[port] = - apl->usb2eye[port].per_port_tx_pe_half; - - if (apl->usb2eye[port].per_port_pe_txi_set) - cfg->port_usb20_per_port_pe_txi_set[port] = - apl->usb2eye[port].per_port_pe_txi_set; - - if (apl->usb2eye[port].per_port_txi_set) - cfg->port_usb20_per_port_txi_set[port] = - apl->usb2eye[port].per_port_txi_set; - - if (apl->usb2eye[port].hs_skew_sel) - cfg->port_usb20_hs_skew_sel[port] = - apl->usb2eye[port].hs_skew_sel; - - if (apl->usb2eye[port].usb_tx_emphasis_en) - cfg->port_usb20_i_usb_tx_emphasis_en[port] = - apl->usb2eye[port].usb_tx_emphasis_en; - - if (apl->usb2eye[port].per_port_rxi_set) - cfg->port_usb20_per_port_rxi_set[port] = - apl->usb2eye[port].per_port_rxi_set; - - if (apl->usb2eye[port].hs_npre_drv_sel) - cfg->port_usb20_hs_npre_drv_sel[port] = - apl->usb2eye[port].hs_npre_drv_sel; - } -} - int fsps_update_config(struct udevice *dev, ulong rom_offset, struct fsps_upd *upd) { struct fsp_s_config *cfg = &upd->config; - struct apl_config *apl; - struct binman_entry vbt; - void *buf; - int ret; - - ret = binman_entry_find("intel-vbt", &vbt); - if (ret) - return log_msg_ret("Cannot find VBT", ret); - vbt.image_pos += rom_offset; - buf = malloc(vbt.size); - if (!buf) - return log_msg_ret("Alloc VBT", -ENOMEM); + ofnode node; - /* - * Load VBT before devicetree-specific config. This only supports - * memory-mapped SPI at present. - */ - bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); - memcpy(buf, (void *)vbt.image_pos, vbt.size); - bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); - if (*(u32 *)buf != VBT_SIGNATURE) - return log_msg_ret("VBT signature", -EINVAL); - cfg->graphics_config_ptr = (ulong)buf; - - apl = malloc(sizeof(*apl)); - if (!apl) - return log_msg_ret("config", -ENOMEM); - get_config(dev, apl); - - cfg->ish_enable = 0; - cfg->enable_sata = 0; - cfg->pcie_root_port_en[2] = 0; - cfg->pcie_rp_hot_plug[2] = 0; - cfg->pcie_root_port_en[3] = 0; - cfg->pcie_rp_hot_plug[3] = 0; - cfg->pcie_root_port_en[4] = 0; - cfg->pcie_rp_hot_plug[4] = 0; - cfg->pcie_root_port_en[5] = 0; - cfg->pcie_rp_hot_plug[5] = 0; - cfg->pcie_root_port_en[1] = 0; - cfg->pcie_rp_hot_plug[1] = 0; - cfg->usb_otg = 0; - cfg->i2c6_enable = 0; - cfg->i2c7_enable = 0; - cfg->hsuart3_enable = 0; - cfg->spi1_enable = 0; - cfg->spi2_enable = 0; - cfg->sdio_enabled = 0; - - memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin, - sizeof(cfg->pcie_rp_clk_req_number)); - - memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable, - sizeof(cfg->pcie_rp_hot_plug)); - - switch (apl->serirq_mode) { - case SERIRQ_QUIET: - cfg->sirq_enable = 1; - cfg->sirq_mode = 0; - break; - case SERIRQ_CONTINUOUS: - cfg->sirq_enable = 1; - cfg->sirq_mode = 1; - break; - case SERIRQ_OFF: - default: - cfg->sirq_enable = 0; - break; + if (IS_ENABLED(CONFIG_HAVE_VBT)) { + struct binman_entry vbt; + void *vbt_buf; + int ret; + + ret = binman_entry_find("intel-vbt", &vbt); + if (ret) + return log_msg_ret("Cannot find VBT", ret); + vbt.image_pos += rom_offset; + vbt_buf = malloc(vbt.size); + if (!vbt_buf) + return log_msg_ret("Alloc VBT", -ENOMEM); + + /* + * Load VBT before devicetree-specific config. This only + * supports memory-mapped SPI at present. + */ + bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); + memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size); + bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); + if (*(u32 *)vbt_buf != VBT_SIGNATURE) + return log_msg_ret("VBT signature", -EINVAL); + + cfg->graphics_config_ptr = (ulong)vbt_buf; } - if (apl->emmc_tx_cmd_cntl) - cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl; - if (apl->emmc_tx_data_cntl1) - cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1; - if (apl->emmc_tx_data_cntl2) - cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2; - if (apl->emmc_rx_cmd_data_cntl1) - cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1; - if (apl->emmc_rx_strobe_cntl) - cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl; - if (apl->emmc_rx_cmd_data_cntl2) - cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2; - if (apl->emmc_host_max_speed) - cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed; - - cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable; - - cfg->skip_mp_init = true; - - /* Disable setting of EISS bit in FSP */ - cfg->spi_eiss = 0; - - /* Disable FSP from locking access to the RTC NVRAM */ - cfg->rtc_lock = 0; - - /* Enable Audio clk gate and power gate */ - cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable; - cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable; - /* Bios config lockdown Audio clk and power gate */ - cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown; - apl_fsp_silicon_init_params_cb(apl, cfg); - - cfg->usb_otg = true; - cfg->vtd_enable = apl->enable_vtd; + node = dev_read_subnode(dev, "fsp-s"); + if (!ofnode_valid(node)) + return log_msg_ret("fsp-s settings", -ENOENT); - return 0; + return fsp_s_update_config_from_dtb(node, cfg); } static void p2sb_set_hide_bit(pci_dev_t dev, int hide) diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index 0f04c4f8e9..a5d31d1dea 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -69,6 +69,17 @@ static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) info->vbnv_size = vbnv->vbnv_size; } +static void cb_parse_cbmem_entry(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_entry *entry = (struct cb_cbmem_entry *)ptr; + + if (entry->id != CBMEM_ID_SMBIOS) + return; + + info->smbios_start = entry->address; + info->smbios_size = entry->entry_size; +} + static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) { int i; @@ -206,6 +217,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); break; + case CB_TAG_CBMEM_ENTRY: + cb_parse_cbmem_entry(ptr, info); + break; default: cb_parse_unhandled(rec->tag, ptr); break; diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index d48ef3573e..dea35b73a0 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -21,6 +21,8 @@ #include <asm/arch-apollolake/iomap.h> #include <asm/arch-apollolake/pm.h> #include <dt-bindings/clock/intel-clock.h> +#include <asm/arch-apollolake/fsp/fsp_m_upd.h> +#include <asm/arch-apollolake/fsp/fsp_s_upd.h> / { model = "Google Coral"; @@ -436,7 +438,42 @@ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ >; - lpddr4-swizzle = /bits/ 8 < + fspm,package = <PACKAGE_BGA>; + fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; + fspm,memory-down = <MEMORY_DOWN_YES>; + fspm,scrambler-support = <1>; + fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>; + fspm,channel-hash-mask = <0x36>; + fspm,slice-hash-mask = <0x9>; + fspm,dual-rank-support-enable = <1>; + fspm,low-memory-max-value = <2048>; + fspm,ch0-rank-enable = <1>; + fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch1-rank-enable = <1>; + fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch2-rank-enable = <1>; + fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch3-rank-enable = <1>; + fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,fspm,skip-cse-rbp = <1>; + + fspm,ch-bit-swizzling = /bits/ 8 < /* LP4_PHYS_CH0A */ /* DQA[0:7] pins of LPDDR4 module */ @@ -484,8 +521,19 @@ &fsp_s { u-boot,dm-pre-proper; + fsps,ish-enable = <0>; + fsps,enable-sata = <0>; + fsps,pcie-root-port-en = [00 00 00 00 00 01]; + fsps,pcie-rp-hot-plug = [00 00 00 00 00 01]; + fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>; + fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>; + fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>; + fsps,spi1-enable = <SPIX_ENABLE_DISABLED>; + fsps,spi2-enable = <SPIX_ENABLE_DISABLED>; + fsps,sdio-enabled = <0>; + /* Disable unused clkreq of PCIe root ports */ - pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */ + fsps,pcie-rp-clk-req-number = /bits/ 8 <0 /* wifi/bt */ CLKREQ_DISABLED CLKREQ_DISABLED CLKREQ_DISABLED @@ -539,18 +587,27 @@ * [14:8] steps of delay for Auto Tuning Mode, each 125ps * [6:0] steps of delay for HS200, each 125ps */ - emmc = <0x0c16 0x28162828 0x00181717 0x10008>; - /* Enable DPTF */ dptf-enable; + fsps,emmc-tx-data-cntl1 = <0x0c16>; + fsps,emmc-tx-data-cntl2 = <0x28162828>; + fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>; + fsps,emmc-rx-cmd-data-cntl2 = <0x10008>; /* Enable Audio Clock and Power gating */ - hdaudio-clk-gate-enable; - hdaudio-pwr-gate-enable; - hdaudio-bios-config-lockdown; + fsps,hd-audio-clk-gate = <1>; + fsps,hd-audio-pwr-gate = <1>; + fsps,bios-cfg-lock-down = <1>; /* Enable lpss s0ix */ - lpss-s0ix-enable; + fsps,lpss-s0ix-enable = <1>; + + fsps,skip-mp-init = <1>; + fsps,spi-eiss = <0>; + fsps,rtc-lock = <0>; + + fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01]; + fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03]; /* * TODO(sjg@chromium.org): Move this to the I2C nodes diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h index 93bee5b2d1..a77964f30c 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h @@ -7,6 +7,7 @@ #ifndef __ASM_ARCH_FSP_M_UDP_H #define __ASM_ARCH_FSP_M_UDP_H +#ifndef __ASSEMBLY__ #include <asm/fsp2/fsp_api.h> #define FSP_DRAM_CHANNELS 4 @@ -119,5 +120,172 @@ struct __packed fspm_upd { u8 unused_upd_space2[158]; u16 upd_terminator; }; +#endif + +#define SERIAL_DEBUG_PORT_TYPE_NONE 0 +#define SERIAL_DEBUG_PORT_TYPE_IO 1 +#define SERIAL_DEBUG_PORT_TYPE_MMIO 2 + +#define SERIAL_DEBUG_PORT_DEVICE_UART0 0 +#define SERIAL_DEBUG_PORT_DEVICE_UART1 1 +#define SERIAL_DEBUG_PORT_DEVICE_UART2 2 +#define SERIAL_DEBUG_PORT_DEVICE_EXTERNAL 3 + +#define SERIAL_DEBUG_PORT_STRIDE_SIZE_1 0 +#define SERIAL_DEBUG_PORT_STRIDE_SIZE_4 2 + +#define IGD_DVMT_50_PRE_ALLOC_64M 0x02 +#define IGD_DVMT_50_PRE_ALLOC_96M 0x03 +#define IGD_DVMT_50_PRE_ALLOC_128M 0x04 +#define IGD_DVMT_50_PRE_ALLOC_160M 0x05 +#define IGD_DVMT_50_PRE_ALLOC_192M 0x06 +#define IGD_DVMT_50_PRE_ALLOC_224M 0x07 +#define IGD_DVMT_50_PRE_ALLOC_256M 0x08 +#define IGD_DVMT_50_PRE_ALLOC_288M 0x09 +#define IGD_DVMT_50_PRE_ALLOC_320M 0x0a +#define IGD_DVMT_50_PRE_ALLOC_352M 0x0b +#define IGD_DVMT_50_PRE_ALLOC_384M 0x0c +#define IGD_DVMT_50_PRE_ALLOC_416M 0x0d +#define IGD_DVMT_50_PRE_ALLOC_448M 0x0e +#define IGD_DVMT_50_PRE_ALLOC_480M 0x0f +#define IGD_DVMT_50_PRE_ALLOC_512M 0x10 + +#define IGD_APERTURE_SIZE_128M 0x1 +#define IGD_APERTURE_SIZE_256M 0x2 +#define IGD_APERTURE_SIZE_512M 0x3 + +#define GTT_SIZE_2M 1 +#define GTT_SIZE_4M 2 +#define GTT_SIZE_8M 3 + +#define PRIMARY_VIDEO_ADAPTER_AUTO 0 +#define PRIMARY_VIDEO_ADAPTER_IGD 2 +#define PRIMARY_VIDEO_ADAPTER_PCI 3 + +#define PACKAGE_SODIMM 0 +#define PACKAGE_BGA 1 +#define PACKAGE_BGA_MIRRORED 2 +#define PACKAGE_SODIMM_UDIMM_RANK_MIRRORED 3 + +#define PROFILE_WIO2_800_7_8_8 0x1 +#define PROFILE_WIO2_1066_9_10_10 0x2 +#define PROFILE_LPDDR3_1066_8_10_10 0x3 +#define PROFILE_LPDDR3_1333_10_12_12 0x4 +#define PROFILE_LPDDR3_1600_12_15_15 0x5 +#define PROFILE_LPDDR3_1866_14_17_17 0x6 +#define PROFILE_LPDDR3_2133_16_20_20 0x7 +#define PROFILE_LPDDR4_1066_10_10_10 0x8 +#define PROFILE_LPDDR4_1600_14_15_15 0x9 +#define PROFILE_LPDDR4_2133_20_20_20 0xa +#define PROFILE_LPDDR4_2400_24_22_22 0xb +#define PROFILE_LPDDR4_2666_24_24_24 0xc +#define PROFILE_LPDDR4_2933_28_27_27 0xd +#define PROFILE_LPDDR4_3200_28_29_29 0xe +#define PROFILE_DDR3_1066_6_6_6 0xf +#define PROFILE_DDR3_1066_7_7_7 0x10 +#define PROFILE_DDR3_1066_8_8_8 0x11 +#define PROFILE_DDR3_1333_7_7_7 0x12 +#define PROFILE_DDR3_1333_8_8_8 0x13 +#define PROFILE_DDR3_1333_9_9_9 0x14 +#define PROFILE_DDR3_1333_10_10_10 0x15 +#define PROFILE_DDR3_1600_8_8_8 0x16 +#define PROFILE_DDR3_1600_9_9_9 0x17 +#define PROFILE_DDR3_1600_10_10_10 0x18 +#define PROFILE_DDR3_1600_11_11_11 0x19 +#define PROFILE_DDR3_1866_10_10_10 0x1a +#define PROFILE_DDR3_1866_11_11_11 0x1b +#define PROFILE_DDR3_1866_12_12_12 0x1c +#define PROFILE_DDR3_1866_13_13_13 0x1d +#define PROFILE_DDR3_2133_11_11_11 0x1e +#define PROFILE_DDR3_2133_12_12_12 0x1f +#define PROFILE_DDR3_2133_13_13_13 0x20 +#define PROFILE_DDR3_2133_14_14_14 0x21 +#define PROFILE_DDR4_1333_10_10_10 0x22 +#define PROFILE_DDR4_1600_10_10_10 0x23 +#define PROFILE_DDR4_1600_11_11_11 0x24 +#define PROFILE_DDR4_1600_12_12_12 0x25 +#define PROFILE_DDR4_1866_12_12_12 0x26 +#define PROFILE_DDR4_1866_13_13_13 0x27 +#define PROFILE_DDR4_1866_14_14_14 0x28 +#define PROFILE_DDR4_2133_14_14_14 0x29 +#define PROFILE_DDR4_2133_15_15_15 0x2a +#define PROFILE_DDR4_2133_16_16_16 0x2b +#define PROFILE_DDR4_2400_15_15_15 0x2c +#define PROFILE_DDR4_2400_16_16_16 0x2d +#define PROFILE_DDR4_2400_17_17_17 0x2e +#define PROFILE_DDR4_2400_18_18_18 0x2f + +#define MEMORY_DOWN_NO 0 +#define MEMORY_DOWN_YES 1 +#define MEMORY_DOWN_MD_SODIMM 2 +#define MEMORY_DOWN_LPDDR4 3 + +#define DDR3L_PAGE_SIZE_1KB 1 +#define DDR3L_PAGE_SIZE_2KB 2 + +#define INTERLEAVED_MODE_DISABLE 0 +#define INTERLEAVED_MODE_ENABLE 2 + +#define RMT_MODE_DISABLE 0 +#define RMT_MODE_ENABLE 3 + +#define CHX_DEVICE_WIDTH_X8 0 +#define CHX_DEVICE_WIDTH_X16 1 +#define CHX_DEVICE_WIDTH_X32 2 +#define CHX_DEVICE_WIDTH_X64 3 + +#define CHX_DEVICE_DENSITY_4GB 0 +#define CHX_DEVICE_DENSITY_6GB 1 +#define CHX_DEVICE_DENSITY_8GB 2 +#define CHX_DEVICE_DENSITY_12GB 3 +#define CHX_DEVICE_DENSITY_16GB 4 +#define CHX_DEVICE_DENSITY_2GB 5 + +#define CHX_OPTION_RANK_INTERLEAVING 0x1 +#define CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE 0x2 +#define CHX_OPTION_CH1_CLK_DISABLE 0x4 +#define CHX_OPTION_ADDRESS_MAP_2KB 0x10 + +#define CHX_ODT_CONFIG_DDR3_RX_ODT 0x1 +#define CHX_ODT_CONFIG_DDR4_CA_ODT 0x2 +#define CHX_ODT_CONFIG_DDR3L_TX_ODT 0x10 + +#define CHX_MODE2N_AUTO 0 +#define CHX_MODE2N_FORCE 1 + +#define CHX_ODT_LEVELS_CONNECTED_TO_SOC 0x0 +#define CHX_ODT_LEVELS_HELD_HIGH 0x1 + +#define NPK_EN_DISABLE 0 +#define NPK_EN_ENABLE 1 +#define NPK_EN_DEBUGGER 2 +#define NPK_EN_AUTO 3 + +#define FW_TRACE_DESTINATION_NPK_TRACE_TO_MEMORY 1 +#define FW_TRACE_DESTINATION_NPK_TRACE_TO_DCI 2 +#define FW_TRACE_DESTINATION_NPK_NPK_TRACE_TO_BSSB 3 +#define FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI 4 + +#define MSC_X_WRAP_0 0 +#define MSC_X_WRAP_1 1 + +#define MSC_X_SIZE_0M 0 +#define MSC_X_SIZE_1M 1 +#define MSC_X_SIZE_8M 2 +#define MSC_X_SIZE_64M 3 +#define MSC_X_SIZE_128M 4 +#define MSC_X_SIZE_256M 5 +#define MSC_X_SIZE_512M 6 +#define MSC_X_SIZE_1GB 7 + +#define PTI_MODE_0 0 +#define PTI_MODE_x4 1 +#define PTI_MODE_x8 2 +#define PTI_MODE_x12 3 +#define PTI_MODE_x16 4 + +#define PTI_SPEED_FULL 0 +#define PTI_SPEED_HALF 1 +#define PTI_SPEED_QUARTER 2 #endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h index 4a868e80ba..87596ffd9d 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h @@ -6,6 +6,7 @@ #ifndef __ASM_ARCH_FSP_S_UDP_H #define __ASM_ARCH_FSP_S_UDP_H +#ifndef __ASSEMBLY__ #include <asm/fsp2/fsp_api.h> struct __packed fsp_s_config { @@ -288,5 +289,206 @@ struct __packed fsps_upd { u8 unused_upd_space2[46]; u16 upd_terminator; }; +#endif + +#define PROC_TRACE_MEM_SIZE_DISABLE 0xff + +#define BOOT_P_STATE_HFM 0 +#define BOOT_P_STATE_LFM 1 + +#define PKG_C_STATE_LIMIT_C0_C1 0 +#define PKG_C_STATE_LIMIT_C2 1 +#define PKG_C_STATE_LIMIT_C3 2 +#define PKG_C_STATE_LIMIT_C6 3 +#define PKG_C_STATE_LIMIT_C7 4 +#define PKG_C_STATE_LIMIT_C7S 5 +#define PKG_C_STATE_LIMIT_C8 6 +#define PKG_C_STATE_LIMIT_C9 7 +#define PKG_C_STATE_LIMIT_C10 8 +#define PKG_C_STATE_LIMIT_CMAX 9 +#define PKG_C_STATE_LIMIT_CPU_DEFAULT 254 +#define PKG_C_STATE_LIMIT_AUTO 255 + +#define C_STATE_AUTO_DEMOTION_DISABLE_C1_C3 0 +#define C_STATE_AUTO_DEMOTION_ENABLE_C3_C6_C7_TO_C1 1 +#define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C3 2 +#define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C1_C3 3 + +#define C_STATE_UN_DEMOTION_DISABLE_C1_C3 0 +#define C_STATE_UN_DEMOTION_ENABLE_C1 1 +#define C_STATE_UN_DEMOTION_ENABLE_C3 2 +#define C_STATE_UN_DEMOTION_ENABLE_C1_C3 3 + +#define MAX_CORE_C_STATE_UNLIMITED 0 +#define MAX_CORE_C_STATE_C1 1 +#define MAX_CORE_C_STATE_C3 2 +#define MAX_CORE_C_STATE_C6 3 +#define MAX_CORE_C_STATE_C7 4 +#define MAX_CORE_C_STATE_C8 5 +#define MAX_CORE_C_STATE_C9 6 +#define MAX_CORE_C_STATE_C10 7 +#define MAX_CORE_C_STATE_CCX 8 + +#define IPU_ACPI_MODE_DISABLE 0 +#define IPU_ACPI_MODE_IGFX_CHILD_DEVICE 1 +#define IPU_ACPI_MODE_ACPI_DEVICE 1 + +#define CD_CLOCK_FREQ_144MHZ 0 +#define CD_CLOCK_FREQ_288MHZ 1 +#define CD_CLOCK_FREQ_384MHZ 2 +#define CD_CLOCK_FREQ_576MHZ 3 +#define CD_CLOCK_FREQ_624MHZ 4 + +#define HDA_IO_BUFFER_OWNERSHIP_HDA_ALL_IO 0 +#define HDA_IO_BUFFER_OWNERSHIP_HDA_I2S_SPLIT 1 +#define HDA_IO_BUFFER_OWNERSHIP_I2S_ALL_IO 2 + +#define HDA_IO_BUFFER_VOLTAGE_3V3 0 +#define HDA_IO_BUFFER_VOLTAGE_1V8 1 + +#define HDA_VC_TYPE_VC0 0 +#define HDA_VC_TYPE_VC1 1 + +#define HDA_LINK_FREQ_6MHZ 0 +#define HDA_LINK_FREQ_12MHZ 1 +#define HDA_LINK_FREQ_24MHZ 2 +#define HDA_LINK_FREQ_48MHZ 3 +#define HDA_LINK_FREQ_96MHZ 4 +#define HDA_LINK_FREQ_INVALID 5 + +#define HDA_I_DISP_LINK_FREQ_6MHZ 0 +#define HDA_I_DISP_LINK_FREQ_12MHZ 1 +#define HDA_I_DISP_LINK_FREQ_24MHZ 2 +#define HDA_I_DISP_LINK_FREQ_48MHZ 3 +#define HDA_I_DISP_LINK_FREQ_96MHZ 4 +#define HDA_I_DISP_LINK_FREQ_INVALID 5 + +#define HDA_I_DISP_LINK_T_MODE_2T 0 +#define HDA_I_DISP_LINK_T_MODE_1T 1 + +#define HDA_DISP_DMIC_DISABLE 0 +#define HDA_DISP_DMIC_2CH_ARRAY 1 +#define HDA_DISP_DMIC_4CH_ARRAY 2 + +#define HDA_CSE_MEM_TRANSFERS_VC0 0 +#define HDA_CSE_MEM_TRANSFERS_VC2 1 + +#define HDA_HOST_MEM_TRANSFERS_VC0 0 +#define HDA_HOST_MEM_TRANSFERS_VC2 1 + +#define HDA_DSP_FEATURE_MASK_WOV 0x1 +#define HDA_DSP_FEATURE_MASK_BT_SIDEBAND 0x2 +#define HDA_DSP_FEATURE_MASK_CODEC_VAD 0x4 +#define HDA_DSP_FEATURE_MASK_BT_INTEL_HFP 0x20 +#define HDA_DSP_FEATURE_MASK_BT_INTEL_A2DP 0x40 +#define HDA_DSP_FEATURE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80 + +#define HDA_DSP_PP_MODULE_MASK_WOV 0x1 +#define HDA_DSP_PP_MODULE_MASK_BT_SIDEBAND 0x2 +#define HDA_DSP_PP_MODULE_MASK_CODEC_VAD 0x4 +#define HDA_DSP_PP_MODULE_MASK_BT_INTEL_HFP 0x20 +#define HDA_DSP_PP_MODULE_MASK_BT_INTEL_A2DP 0x40 +#define HDA_DSP_PP_MODULE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80 + +#define I2CX_ENABLE_DISABLED 0 +#define I2CX_ENABLE_PCI_MODE 1 +#define I2CX_ENABLE_ACPI_MODE 2 + +#define HSUARTX_ENABLE_DISABLED 0 +#define HSUARTX_ENABLE_PCI_MODE 1 +#define HSUARTX_ENABLE_ACPI_MODE 2 + +#define SPIX_ENABLE_DISABLED 0 +#define SPIX_ENABLE_PCI_MODE 1 +#define SPIX_ENABLE_ACPI_MODE 2 + +#define PCIE_RP_SPEED_AUTO 0 +#define PCIE_RP_SPEED_GEN1 1 +#define PCIE_RP_SPEED_GEN2 2 +#define PCIE_RP_SPEED_GEN3 3 + +#define PCIE_RP_ASPM_DISABLE 0 +#define PCIE_RP_ASPM_L0S 1 +#define PCIE_RP_ASPM_L1 2 +#define PCIE_RP_ASPM_L0S_L1 3 +#define PCIE_RP_ASPM_AUTO 4 + +#define PCIE_RP_L1_SUBSTATES_DISABLE 0 +#define PCIE_RP_L1_SUBSTATES_L1_1 1 +#define PCIE_RP_L1_SUBSTATES_L1_2 2 +#define PCIE_RP_L1_SUBSTATES_L1_1_L1_2 3 + +#define SATA_MODE_AHCI 0 +#define SATA_MODE_RAID 1 + +#define SATA_SPEED_LIMIT_SC_SATA_SPEED 0 +#define SATA_SPEED_LIMIT_1_5GBS 1 +#define SATA_SPEED_LIMIT_3GBS 2 +#define SATA_SPEED_LIMIT_6GBS 3 + +#define SATA_PORT_SOLID_STATE_DRIVE_HARD_DISK_DRIVE 0 +#define SATA_PORT_SOLID_STATE_DRIVE_SOLID_STATE_DRIVE 1 + +#define CRID_SETTING_DISABLE 0 +#define CRID_SETTING_CRID_1 1 +#define CRID_SETTING_CRID_2 2 +#define CRID_SETTING_CRID_3 3 + +#define RESET_SELECT_WARM_RESET 0x6 +#define RESET_SELECT_COLD_RESET 0xe + +#define EMMC_HOST_SPEED_MAX_HS400 0 +#define EMMC_HOST_SPEED_MAX_HS200 1 +#define EMMC_HOST_SPEED_MAX_DDR50 2 + +#define SERIAL_IRQ_MODE_QUIET_MODE 0 +#define SERIAL_IRQ_MODE_CONTINUOUS_MODE 1 + +#define START_FRAME_PULSE_WIDTH_SCSFPW4CLK 0 +#define START_FRAME_PULSE_WIDTH_SCSFPW6CLK 1 +#define START_FRAME_PULSE_WIDTH_SCSFPW8CLK 1 + +#define USB30_MODE_DISABLE 0 +#define USB30_MODE_ENABLE 1 +#define USB30_MODE_AUTO 2 + +#define USB_OTG_DISABLE 0 +#define USB_OTG_PCI_MODE 1 +#define USB_OTG_ACPI_MODE 2 + +#define SSIC_RATE_A_SERIES 1 +#define SSIC_RATE_B_SERIES 2 + +#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0 +#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1 +#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2 + +#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0 +#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1 +#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2 +#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3 +#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4 +#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5 + +#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0 +#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1 +#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2 + +#define PWR_BTN_OVERRIDE_PERIOD_4S 0 +#define PWR_BTN_OVERRIDE_PERIOD_6S 1 +#define PWR_BTN_OVERRIDE_PERIOD_8S 2 +#define PWR_BTN_OVERRIDE_PERIOD_10S 3 +#define PWR_BTN_OVERRIDE_PERIOD_12S 4 +#define PWR_BTN_OVERRIDE_PERIOD_14S 5 + +#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0 +#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1 +#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2 +#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3 +#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4 +#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5 + +#define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0 +#define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1 #endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp_bindings.h b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h new file mode 100644 index 0000000000..b4939519ce --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + * Copyright 2020 B&R Industrial Automation GmbH - http://www.br-automation.com + */ + +#ifndef __ASM_ARCH_FSP_BINDINGS_H +#define __ASM_ARCH_FSP_BINDINGS_H + +#include <asm/arch/fsp/fsp_m_upd.h> +#include <asm/arch/fsp/fsp_s_upd.h> + +#define ARRAY_SIZE_OF_MEMBER(s, m) (ARRAY_SIZE((((s *)0)->m))) +#define SIZE_OF_MEMBER(s, m) (sizeof((((s *)0)->m))) + +enum conf_type { + FSP_UINT8, + FSP_UINT16, + FSP_UINT32, + FSP_STRING, + FSP_LPDDR4_SWIZZLE, +}; + +/** + * struct fsp_binding - Binding describing devicetree/FSP relationships + * @offset: Offset within the FSP config structure + * @propname: Name of property to read + * @type: Type of the property to read + * @count: If the property is expected to be an array, this is the + * number of expected elements + * Set to 0 if the property is expected to be a scalar + * + * The struct fsp_binding is used to describe the relationship between + * values stored in devicetree and where they are placed in the FSP + * configuration structure. + */ +struct fsp_binding { + size_t offset; + char *propname; + enum conf_type type; + size_t count; +}; + +/* + * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. + * There are four physical LPDDR4 channels, each 32-bits wide. There are two + * logical channels using two physical channels together to form a 64-bit + * interface to memory for each logical channel. + */ + +enum { + LP4_PHYS_CH0A, + LP4_PHYS_CH0B, + LP4_PHYS_CH1A, + LP4_PHYS_CH1B, + + LP4_NUM_PHYS_CHANNELS, +}; + +/* + * The DQs within a physical channel can be bit-swizzled within each byte. + * Within a channel the bytes can be swapped, but the DQs need to be routed + * with the corresponding DQS (strobe). + */ +enum { + LP4_DQS0, + LP4_DQS1, + LP4_DQS2, + LP4_DQS3, + + LP4_NUM_BYTE_LANES, + DQ_BITS_PER_DQS = 8, +}; + +/* Provide bit swizzling per DQS and byte swapping within a channel */ +struct lpddr4_chan_swizzle_cfg { + u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS]; +}; + +struct lpddr4_swizzle_cfg { + struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS]; +}; + +/** + * fsp_m_update_config_from_dtb() - Read FSP-M config from devicetree node + * @node: Valid node reference to read property from + * @cfg: Pointer to FSP-M config structure + * @return 0 on success, -ve on error + * + * This function reads the configuration for FSP-M from the provided + * devicetree node and saves it in the FSP-M configuration structure. + * Configuration options that are not present in the devicetree are + * left at their current value. + */ +int fsp_m_update_config_from_dtb(ofnode node, struct fsp_m_config *cfg); + +/** + * fsp_s_update_config_from_dtb() - Read FSP-S config from devicetree node + * @node: Valid node reference to read property from + * @cfg: Pointer to FSP-S config structure + * @return 0 on success, -ve on error + * + * This function reads the configuration for FSP-S from the provided + * devicetree node and saves it in the FSP-S configuration structure. + * Configuration options that are not present in the devicetree are + * left at their current value. + */ +int fsp_s_update_config_from_dtb(ofnode node, struct fsp_s_config *cfg); + +#endif diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h b/arch/x86/include/asm/arch-coreboot/sysinfo.h index dd8d1cba92..419ec52933 100644 --- a/arch/x86/include/asm/arch-coreboot/sysinfo.h +++ b/arch/x86/include/asm/arch-coreboot/sysinfo.h @@ -49,6 +49,8 @@ struct sysinfo_t { u32 vdat_size; void *tstamp_table; void *cbmem_cons; + u64 smbios_start; + u32 smbios_size; struct cb_serial *serial; }; diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 268284f43c..7e1576768b 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -214,6 +214,17 @@ struct cb_vbnv { uint32_t vbnv_size; }; +#define CB_TAG_CBMEM_ENTRY 0x0031 +#define CBMEM_ID_SMBIOS 0x534d4254 + +struct cb_cbmem_entry { + uint32_t tag; + uint32_t size; + uint64_t address; + uint32_t entry_size; + uint32_t id; +}; + #define CB_TAG_CMOS_OPTION_TABLE 0x00c8 struct cb_cmos_option_table { diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index 8c577902b2..85cae54a0c 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -81,11 +81,10 @@ static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base, * 'COREBOOT' (CBFS, size 1814528, offset 2117632). */ ulong cbfs_base = 0x205000; - ulong cbfs_size = 0x1bb000; struct cbfs_priv *cbfs; int ret; - ret = cbfs_init_mem(map_base + cbfs_base, cbfs_size, &cbfs); + ret = cbfs_init_mem(map_base + cbfs_base, &cbfs); if (ret) return ret; if (!ret) { |