diff options
Diffstat (limited to 'arch/x86')
29 files changed, 348 insertions, 211 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cbbaa4f2ce..e8968a7182 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -369,4 +369,14 @@ config PCIE_ECAM_BASE assigned to PCI devices - i.e. the memory and prefetch regions, as passed to pci_set_region(). +config PCIE_ECAM_SIZE + hex + default 0x10000000 + help + This is the size of memory-mapped address of PCI configuration space, + which is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, + so a default 0x10000000 size covers all of the 256 buses which is the + maximum number of PCI buses as defined by the PCI specification. + endmenu diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index af927b94e0..b9134cfef3 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -363,13 +363,26 @@ int x86_cpu_init_f(void) mtrr_cap = native_read_msr(MTRR_CAP_MSR); if (mtrr_cap & MTRR_CAP_FIX) { /* Mark the VGA RAM area as uncacheable */ - native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0); - - /* Mark the PCI ROM area as uncacheable */ - native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0); - native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0); - native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0); - native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0); + native_write_msr(MTRR_FIX_16K_A0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); + + /* + * Mark the PCI ROM area as cacheable to improve ROM + * execution performance. + */ + native_write_msr(MTRR_FIX_4K_C0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_C8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); /* Enable the fixed range MTRRs */ msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); @@ -683,6 +696,15 @@ __weak int x86_init_cpus(void) #ifdef CONFIG_SMP debug("Init additional CPUs\n"); x86_mp_init(); +#else + struct udevice *dev; + + /* + * This causes the cpu-x86 driver to be probed. + * We don't check return value here as we want to allow boards + * which have not been converted to use cpu uclass driver to boot. + */ + uclass_first_device(UCLASS_CPU, &dev); #endif return 0; diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index c777d3646f..853c82f5a7 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -32,14 +32,76 @@ DECLARE_GLOBAL_DATA_PTR; "pushl $"#x"\n" \ "jmp irq_common_entry\n" +static char *exceptions[] = { + "Divide Error", + "Debug", + "NMI Interrupt", + "Breakpoint", + "Overflow", + "BOUND Range Exceeded", + "Invalid Opcode (Undefined Opcode)", + "Device Not Avaiable (No Math Coprocessor)", + "Double Fault", + "Coprocessor Segment Overrun", + "Invalid TSS", + "Segment Not Present", + "Stack Segment Fault", + "Gerneral Protection", + "Page Fault", + "Reserved", + "x87 FPU Floating-Point Error", + "Alignment Check", + "Machine Check", + "SIMD Floating-Point Exception", + "Virtualization Exception", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved" +}; + static void dump_regs(struct irq_regs *regs) { + unsigned long cs, eip, eflags; unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; unsigned long d0, d1, d2, d3, d6, d7; unsigned long sp; + /* + * Some exceptions cause an error code to be saved on the current stack + * after the EIP value. We should extract CS/EIP/EFLAGS from different + * position on the stack based on the exception number. + */ + switch (regs->irq_id) { + case EXC_DF: + case EXC_TS: + case EXC_NP: + case EXC_SS: + case EXC_GP: + case EXC_PF: + case EXC_AC: + cs = regs->context.ctx2.xcs; + eip = regs->context.ctx2.eip; + eflags = regs->context.ctx2.eflags; + /* We should fix up the ESP due to error code */ + regs->esp += 4; + break; + default: + cs = regs->context.ctx1.xcs; + eip = regs->context.ctx1.eip; + eflags = regs->context.ctx1.eflags; + break; + } + printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n", - (u16)regs->xcs, regs->eip, regs->eflags); + (u16)cs, eip, eflags); printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n", regs->eax, regs->ebx, regs->ecx, regs->edx); @@ -85,6 +147,13 @@ static void dump_regs(struct irq_regs *regs) } } +static void do_exception(struct irq_regs *regs) +{ + printf("%s\n", exceptions[regs->irq_id]); + dump_regs(regs); + hang(); +} + struct idt_entry { u16 base_low; u16 selector; @@ -201,111 +270,10 @@ void irq_llsr(struct irq_regs *regs) * Order Number: 253665-029US, November 2008 * Table 6-1. Exceptions and Interrupts */ - switch (regs->irq_id) { - case 0x00: - printf("Divide Error (Division by zero)\n"); - dump_regs(regs); - hang(); - break; - case 0x01: - printf("Debug Interrupt (Single step)\n"); - dump_regs(regs); - break; - case 0x02: - printf("NMI Interrupt\n"); - dump_regs(regs); - break; - case 0x03: - printf("Breakpoint\n"); - dump_regs(regs); - break; - case 0x04: - printf("Overflow\n"); - dump_regs(regs); - hang(); - break; - case 0x05: - printf("BOUND Range Exceeded\n"); - dump_regs(regs); - hang(); - break; - case 0x06: - printf("Invalid Opcode (UnDefined Opcode)\n"); - dump_regs(regs); - hang(); - break; - case 0x07: - printf("Device Not Available (No Math Coprocessor)\n"); - dump_regs(regs); - hang(); - break; - case 0x08: - printf("Double fault\n"); - dump_regs(regs); - hang(); - break; - case 0x09: - printf("Co-processor segment overrun\n"); - dump_regs(regs); - hang(); - break; - case 0x0a: - printf("Invalid TSS\n"); - dump_regs(regs); - break; - case 0x0b: - printf("Segment Not Present\n"); - dump_regs(regs); - hang(); - break; - case 0x0c: - printf("Stack Segment Fault\n"); - dump_regs(regs); - hang(); - break; - case 0x0d: - printf("General Protection\n"); - dump_regs(regs); - break; - case 0x0e: - printf("Page fault\n"); - dump_regs(regs); - hang(); - break; - case 0x0f: - printf("Floating-Point Error (Math Fault)\n"); - dump_regs(regs); - break; - case 0x10: - printf("Alignment check\n"); - dump_regs(regs); - break; - case 0x11: - printf("Machine Check\n"); - dump_regs(regs); - break; - case 0x12: - printf("SIMD Floating-Point Exception\n"); - dump_regs(regs); - break; - case 0x13: - case 0x14: - case 0x15: - case 0x16: - case 0x17: - case 0x18: - case 0x19: - case 0x1a: - case 0x1b: - case 0x1c: - case 0x1d: - case 0x1e: - case 0x1f: - printf("Reserved Exception\n"); - dump_regs(regs); - break; - - default: + if (regs->irq_id < 32) { + /* Architecture defined exception */ + do_exception(regs); + } else { /* Hardware or User IRQ */ do_irq(regs->irq_id); } diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index ea169b05e9..89d4a5e9cc 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -16,7 +16,6 @@ #include <asm/pci.h> #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h> -#include <linux/kconfig.h> struct gt_powermeter { u16 reg; diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index bc1a0f06fb..3efd3e841f 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -252,7 +252,6 @@ static void pch_rtc_init(pci_dev_t dev) /* TODO: Handle power failure */ if (rtc_failed) printf("RTC power failed\n"); - rtc_init(); } /* CougarPoint PCH Power Management init */ diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index af907c5b9b..7f3b13d357 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -128,6 +128,14 @@ static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry) static int read_seed_from_cmos(struct pei_data *pei_data) { u16 c1, c2, checksum, seed_checksum; + struct udevice *dev; + int rcode = 0; + + rcode = uclass_get_device(UCLASS_RTC, 0, &dev); + if (rcode) { + debug("Cannot find RTC: err=%d\n", rcode); + return -ENODEV; + } /* * Read scrambler seeds from CMOS RAM. We don't want to store them in @@ -135,11 +143,11 @@ static int read_seed_from_cmos(struct pei_data *pei_data) * the flash too much. So we store these in CMOS and the large MRC * data in SPI flash. */ - pei_data->scrambler_seed = rtc_read32(CMOS_OFFSET_MRC_SEED); + rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); - pei_data->scrambler_seed_s3 = rtc_read32(CMOS_OFFSET_MRC_SEED_S3); + rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, &pei_data->scrambler_seed_s3); debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); @@ -150,8 +158,8 @@ static int read_seed_from_cmos(struct pei_data *pei_data) sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2); - seed_checksum = rtc_read8(CMOS_OFFSET_MRC_SEED_CHK); - seed_checksum |= rtc_read8(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; + seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK); + seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; if (checksum != seed_checksum) { debug("%s: invalid seed checksum\n", __func__); @@ -223,13 +231,21 @@ static int build_mrc_data(struct mrc_data_container **datap) static int write_seeds_to_cmos(struct pei_data *pei_data) { u16 c1, c2, checksum; + struct udevice *dev; + int rcode = 0; + + rcode = uclass_get_device(UCLASS_RTC, 0, &dev); + if (rcode) { + debug("Cannot find RTC: err=%d\n", rcode); + return -ENODEV; + } /* Save the MRC seed values to CMOS */ - rtc_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); + rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); - rtc_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); + rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); @@ -240,8 +256,8 @@ static int write_seeds_to_cmos(struct pei_data *pei_data) sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2); - rtc_write8(CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); - rtc_write8(CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); + rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); + rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); return 0; } diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index c209f15ec4..f8da08035e 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -152,23 +152,32 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, return 0; } -void pci_assign_irqs(int bus, int device, int func, u8 irq[4]) +void pci_assign_irqs(int bus, int device, u8 irq[4]) { pci_dev_t bdf; + int func; + u16 vendor; u8 pin, line; - bdf = PCI_BDF(bus, device, func); + for (func = 0; func < 8; func++) { + bdf = PCI_BDF(bus, device, func); + vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID); + if (vendor == 0xffff || vendor == 0x0000) + continue; - pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN); + pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN); - /* PCI spec says all values except 1..4 are reserved */ - if ((pin < 1) || (pin > 4)) - return; + /* PCI spec says all values except 1..4 are reserved */ + if ((pin < 1) || (pin > 4)) + continue; - line = irq[pin - 1]; + line = irq[pin - 1]; + if (!line) + continue; - debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", - line, bus, device, func, 'A' + pin - 1); + debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", + line, bus, device, func, 'A' + pin - 1); - x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); + x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); + } } diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index 1a9140b46e..2e944569b5 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +static bool i440fx; + void board_pci_setup_hose(struct pci_controller *hose) { hose->first_busno = 0; @@ -50,7 +52,7 @@ void board_pci_setup_hose(struct pci_controller *hose) int board_pci_post_scan(struct pci_controller *hose) { int ret = 0; - u16 device; + u16 device, xbcs; int pam, i; pci_dev_t vga; ulong start; @@ -61,7 +63,8 @@ int board_pci_post_scan(struct pci_controller *hose) * PCI device ID. */ device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); - pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM; + i440fx = (device == PCI_DEVICE_ID_INTEL_82441); + pam = i440fx ? I440FX_PAM : Q35_PAM; /* * Initialize Programmable Attribute Map (PAM) Registers @@ -71,7 +74,7 @@ int board_pci_post_scan(struct pci_controller *hose) for (i = 0; i < PAM_NUM; i++) x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); - if (device == PCI_DEVICE_ID_INTEL_82441) { + if (i440fx) { /* * Enable legacy IDE I/O ports decode * @@ -82,6 +85,15 @@ int board_pci_post_scan(struct pci_controller *hose) */ x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); + + /* Enable I/O APIC */ + xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); + xbcs |= APIC_EN; + x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + } else { + /* Configure PCIe ECAM base address */ + x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, + CONFIG_PCIE_ECAM_BASE | BAR_EN); } /* @@ -92,10 +104,35 @@ int board_pci_post_scan(struct pci_controller *hose) * board, it shows as device 2, while for Q35 and ICH9 chipset board, * it shows as device 1. */ - vga = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_VGA : Q35_VGA; + vga = i440fx ? I440FX_VGA : Q35_VGA; start = get_timer(0); ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE); debug("BIOS ran in %lums\n", get_timer(start)); return ret; } + +#ifdef CONFIG_GENERATE_MP_TABLE +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + u8 irq; + + if (i440fx) { + /* + * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not + * connected to I/O APIC INTPIN#16-19. Instead they are routed + * to an irq number controled by the PIRQ routing register. + */ + irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), + PCI_INTERRUPT_LINE); + } else { + /* + * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. + * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. + */ + irq = pirq < 8 ? pirq + 16 : pirq + 12; + } + + return irq; +} +#endif diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index d8761fdfbd..660f9678bd 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -6,4 +6,3 @@ obj-y += fsp_configs.o obj-y += tnc.o topcliff.o -obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index d27b2d9ec6..de50893e6f 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -25,7 +25,6 @@ static void unprotect_spi_flash(void) int arch_cpu_init(void) { - struct pci_controller *hose; int ret; post_code(POST_CPU_INIT); @@ -37,10 +36,6 @@ int arch_cpu_init(void) if (ret) return ret; - ret = pci_early_init_hose(&hose); - if (ret) - return ret; - unprotect_spi_flash(); return 0; diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c deleted file mode 100644 index 6c291f9ee9..0000000000 --- a/arch/x86/cpu/queensbay/tnc_pci.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <pci.h> -#include <asm/pci.h> -#include <asm/fsp/fsp_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - pci_set_region(hose->regions + 3, - 0, - 0, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; -} diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 7c7034c7eb..ad390bf117 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Google Link"; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 4eccefdb8c..84eae3ab65 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Google Panther"; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 60da1f544b..3af9cc3d26 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -90,8 +90,12 @@ pci { #address-cells = <3>; #size-cells = <2>; - compatible = "intel,pci"; + compatible = "pci-x86"; device_type = "pci"; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; pcie@17,0 { #address-cells = <3>; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 2ba081e9dc..d77ff8ad55 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -10,6 +10,7 @@ #include <dt-bindings/interrupt-router/intel-irq.h> /include/ "skeleton.dtsi" +/include/ "rtc.dtsi" / { model = "Intel Galileo"; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 0e59b18d34..9527233d7f 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Intel Minnowboard Max"; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 557428a459..c26c71bcf7 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "QEMU x86 (I440FX)"; @@ -23,6 +24,18 @@ stdout-path = "/serial"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index c259f2a3d2..2e785fa4bf 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -20,6 +20,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "QEMU x86 (Q35)"; @@ -34,6 +35,18 @@ stdout-path = "/serial"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi index 93dacd7307..1797e042da 100644 --- a/arch/x86/dts/rtc.dtsi +++ b/arch/x86/dts/rtc.dtsi @@ -1,6 +1,7 @@ / { rtc { compatible = "motorola,mc146818"; + u-boot,dm-pre-reloc; reg = <0x70 2>; }; }; diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h index 5cbfffffee..b67d3428ee 100644 --- a/arch/x86/include/asm/arch-qemu/qemu.h +++ b/arch/x86/include/asm/arch-qemu/qemu.h @@ -13,10 +13,18 @@ #define PAM_NUM 7 #define PAM_RW 0x33 +/* X-Bus Chip Select Register */ +#define XBCS 0x4e +#define APIC_EN (1 << 8) + /* IDE Timing Register */ #define IDE0_TIM 0x40 #define IDE1_TIM 0x42 -#define IDE_DECODE_EN 0x8000 +#define IDE_DECODE_EN (1 << 15) + +/* PCIe ECAM Base Address Register */ +#define PCIEX_BAR 0x60 +#define BAR_EN (1 << 0) /* I/O Ports */ #define CMOS_ADDR_PORT 0x70 diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index 00cbe07ed1..fcd766ba9b 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -13,6 +13,30 @@ #include <asm/types.h> +/* Architecture defined exceptions */ +enum x86_exception { + EXC_DE = 0, + EXC_DB, + EXC_NMI, + EXC_BP, + EXC_OF, + EXC_BR, + EXC_UD, + EXC_NM, + EXC_DF, + EXC_CSO, + EXC_TS, + EXC_NP, + EXC_SS, + EXC_GP, + EXC_PF, + EXC_MF = 16, + EXC_AC, + EXC_MC, + EXC_XM, + EXC_VE +}; + /* arch/x86/cpu/interrupts.c */ void set_vector(u8 intnum, void *routine); diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index efa9231f92..ad8eba947b 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -432,6 +432,23 @@ void mp_write_compat_address_space(struct mp_config_table *mc, int busid, u32 mptable_finalize(struct mp_config_table *mc); /** + * mp_determine_pci_dstirq() - Determine PCI device's int pin on the I/O APIC + * + * This determines a PCI device's interrupt pin number on the I/O APIC. + * + * This can be implemented by platform codes to handle specifal cases, which + * do not conform to the normal chipset/board design where PIRQ[A-H] are mapped + * directly to I/O APIC INTPIN#16-23. + * + * @bus: bus number of the pci device + * @dev: device number of the pci device + * @func: function number of the pci device + * @pirq: PIRQ number the PCI device's interrupt pin is routed to + * @return: interrupt pin number on the I/O APIC + */ +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq); + +/** * write_mp_table() - Write MP table * * This writes MP table at a given address. diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 70762eed10..f9b30f68bd 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -55,6 +55,8 @@ #define MTRR_FIX_4K_F0000_MSR 0x26e #define MTRR_FIX_4K_F8000_MSR 0x26f +#define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t) + #if !defined(__ASSEMBLER__) /** diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 56eaa25b0c..f7e968e0b0 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -72,11 +72,10 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, * * @bus: PCI bus number * @device: PCI device number - * @func: PCI function number * @irq: An array of IRQ numbers that are assigned to INTA through * INTD of this PCI device. */ -void pci_assign_irqs(int bus, int device, int func, u8 irq[4]); +void pci_assign_irqs(int bus, int device, u8 irq[4]); #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index a727dbfb05..3849bc0756 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -63,9 +63,19 @@ struct irq_regs { /* Pushed by vector handler (irq_<num>) */ long irq_id; /* Pushed by cpu in response to interrupt */ - long eip; - long xcs; - long eflags; + union { + struct { + long eip; + long xcs; + long eflags; + } ctx1; + struct { + long err; + long eip; + long xcs; + long eflags; + } ctx2; + } context; } __attribute__ ((packed)); /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 4c0a7c82ca..28552fa15a 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -77,5 +77,11 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) num_entries++; } + /* Mark PCIe ECAM address range as reserved */ + entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; + entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; + entries[num_entries].type = E820_RESERVED; + num_entries++; + return num_entries; } diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index f16fbcbb0d..f3ad116316 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -21,6 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; +static bool isa_irq_occupied[16]; + struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf) { u32 mc; @@ -243,10 +245,18 @@ static void mptable_add_isa_interrupts(struct mp_config_table *mc, int bus_isa, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0, apicid, 2); - for (i = 3; i < 16; i++) + for (i = 3; i < 16; i++) { + /* + * Do not write ISA interrupt entry if it is already occupied + * by the platform devices. + */ + if (isa_irq_occupied[i]) + continue; + mp_write_intsrc(mc, MP_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, i, apicid, i); + } } /* @@ -269,6 +279,13 @@ static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base, return (i == entry_num) ? false : true; } +/* TODO: move this to driver model */ +__weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + /* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */ + return pirq + 16; +} + static int mptable_add_intsrc(struct mp_config_table *mc, int bus_isa, int apicid) { @@ -280,10 +297,6 @@ static int mptable_add_intsrc(struct mp_config_table *mc, const u32 *cell; int i; - /* Legacy Interrupts */ - debug("Writing ISA IRQs\n"); - mptable_add_isa_interrupts(mc, bus_isa, apicid, 0); - /* Get I/O interrupt information from device tree */ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER); if (node < 0) { @@ -304,28 +317,41 @@ static int mptable_add_intsrc(struct mp_config_table *mc, for (i = 0; i < count; i++) { struct pirq_routing pr; + int bus, dev, func; + int dstirq; pr.bdf = fdt_addr_to_cpu(cell[0]); pr.pin = fdt_addr_to_cpu(cell[1]); pr.pirq = fdt_addr_to_cpu(cell[2]); + bus = PCI_BUS(pr.bdf); + dev = PCI_DEV(pr.bdf); + func = PCI_FUNC(pr.bdf); if (check_dup_entry(intsrc_base, intsrc_entries, - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin)) { + bus, dev, pr.pin)) { debug("found entry for bus %d device %d INT%c, skipping\n", - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), - 'A' + pr.pin - 1); + bus, dev, 'A' + pr.pin - 1); cell += sizeof(struct pirq_routing) / sizeof(u32); continue; } - /* PIRQ[A-H] are always connected to I/O APIC INTPIN#16-23 */ - mp_write_pci_intsrc(mc, MP_INT, PCI_BUS(pr.bdf), - PCI_DEV(pr.bdf), pr.pin, apicid, - pr.pirq + 16); + dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq); + /* + * For PIRQ which is connected to I/O APIC interrupt pin#0-15, + * mark it as occupied so that we can skip it later. + */ + if (dstirq < 16) + isa_irq_occupied[dstirq] = true; + mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin, + apicid, dstirq); intsrc_entries++; cell += sizeof(struct pirq_routing) / sizeof(u32); } + /* Legacy Interrupts */ + debug("Writing ISA IRQs\n"); + mptable_add_isa_interrupts(mc, bus_isa, apicid, 0); + return 0; } diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index 7a34dcf366..ba4116908c 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -98,8 +98,7 @@ void pirq_route_irqs(struct irq_info *irq, int num) } /* Bus, device, slots IRQs for {A,B,C,D} */ - pci_assign_irqs(irq->bus, irq->devfn >> 3, irq->devfn & 7, - irq_slot); + pci_assign_irqs(irq->bus, irq->devfn >> 3, irq_slot); irq++; } diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 144471c5bb..a1ec57e8d3 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -61,8 +61,11 @@ __weak unsigned install_e820_map(unsigned max_entries, entries[2].addr = ISA_END_ADDRESS; entries[2].size = gd->ram_size - ISA_END_ADDRESS; entries[2].type = E820_RAM; + entries[3].addr = CONFIG_PCIE_ECAM_BASE; + entries[3].size = CONFIG_PCIE_ECAM_SIZE; + entries[3].type = E820_RESERVED; - return 3; + return 4; } static void build_command_line(char *command_line, int auto_boot) |