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-rw-r--r--arch/arm/Kconfig37
-rw-r--r--arch/arm/cpu/arm1176/Makefile1
-rw-r--r--arch/arm/cpu/arm1176/bcm2835/Kconfig6
-rw-r--r--arch/arm/cpu/arm1176/start.S22
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/Makefile6
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/aemif.c78
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/clock.c432
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/init.c22
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S10
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/mux.c319
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/timer.c93
-rw-r--r--arch/arm/cpu/arm920t/Makefile2
-rw-r--r--arch/arm/cpu/arm920t/a320/Makefile9
-rw-r--r--arch/arm/cpu/arm920t/a320/reset.S10
-rw-r--r--arch/arm/cpu/arm920t/a320/timer.c118
-rw-r--r--arch/arm/cpu/arm920t/ks8695/Makefile9
-rw-r--r--arch/arm/cpu/arm920t/ks8695/lowlevel_init.S189
-rw-r--r--arch/arm/cpu/arm920t/ks8695/timer.c77
-rw-r--r--arch/arm/cpu/arm926ejs/Makefile2
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/Makefile8
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/clock.c27
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/reset.c24
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/timer.c115
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/Makefile9
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/cpu.c85
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/dram.c117
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/timer.c201
-rw-r--r--arch/arm/cpu/armv7/exynos/Kconfig28
-rw-r--r--arch/arm/cpu/armv7/ls102xa/cpu.c231
-rw-r--r--arch/arm/cpu/armv7/omap3/Kconfig10
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/Kconfig4
-rw-r--r--arch/arm/cpu/armv7/uniphier/Kconfig4
-rw-r--r--arch/arm/cpu/armv8/cache.S6
-rw-r--r--arch/arm/cpu/armv8/cache_v8.c18
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/cpu.c62
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/fdt.c28
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S132
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/mp.c8
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/mp.h1
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/speed.c16
-rw-r--r--arch/arm/include/asm/arch-a320/a320.h22
-rw-r--r--arch/arm/include/asm/arch-fsl-lsch3/config.h38
-rw-r--r--arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h3
-rw-r--r--arch/arm/include/asm/arch-ks8695/platform.h294
-rw-r--r--arch/arm/include/asm/arch-ls102xa/config.h15
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h40
-rw-r--r--arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h57
-rw-r--r--arch/arm/include/asm/arch-mb86r0x/hardware.h15
-rw-r--r--arch/arm/include/asm/arch-mb86r0x/mb86r0x.h599
-rw-r--r--arch/arm/include/asm/arch-pantheon/config.h53
-rw-r--r--arch/arm/include/asm/arch-pantheon/cpu.h77
-rw-r--r--arch/arm/include/asm/arch-pantheon/gpio.h0
-rw-r--r--arch/arm/include/asm/arch-pantheon/mfp.h39
-rw-r--r--arch/arm/include/asm/arch-pantheon/pantheon.h38
-rw-r--r--arch/arm/include/asm/arch-tnetv107x/clock.h53
-rw-r--r--arch/arm/include/asm/arch-tnetv107x/hardware.h160
-rw-r--r--arch/arm/include/asm/arch-tnetv107x/mux.h291
-rw-r--r--arch/arm/include/asm/armv8/mmu.h3
-rw-r--r--arch/arm/include/asm/global_data.h3
-rw-r--r--arch/arm/include/asm/system.h1
-rw-r--r--arch/arm/lib/asm-offsets.c46
-rw-r--r--arch/arm/lib/bootm.c2
-rw-r--r--arch/arm/mach-davinci/Kconfig4
-rw-r--r--arch/arm/mach-tegra/Kconfig14
64 files changed, 610 insertions, 3833 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 820ba1ccab..7a2f91c48e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -73,10 +73,6 @@ config TARGET_INTEGRATORCP_CM920T
bool "Support integratorcp_cm920t"
select CPU_ARM920T
-config TARGET_A320EVB
- bool "Support a320evb"
- select CPU_ARM920T
-
config ARCH_AT91
bool "Atmel AT91"
@@ -88,14 +84,6 @@ config TARGET_SCB9328
bool "Support scb9328"
select CPU_ARM920T
-config TARGET_CM4008
- bool "Support cm4008"
- select CPU_ARM920T
-
-config TARGET_CM41XX
- bool "Support cm41xx"
- select CPU_ARM920T
-
config TARGET_VCMA9
bool "Support VCMA9"
select CPU_ARM920T
@@ -144,10 +132,6 @@ config TARGET_DEVKIT3250
bool "Support devkit3250"
select CPU_ARM926EJS
-config TARGET_JADECPU
- bool "Support jadecpu"
- select CPU_ARM926EJS
-
config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
@@ -227,10 +211,6 @@ config ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
-config TARGET_DKB
- bool "Support dkb"
- select CPU_ARM926EJS
-
config TARGET_SPEAR300
bool "Support spear300"
select CPU_ARM926EJS
@@ -314,10 +294,6 @@ config TARGET_RPI_2
bool "Support rpi_2"
select CPU_V7
-config TARGET_TNETV107X_EVM
- bool "Support tnetv107x_evm"
- select CPU_ARM1176
-
config TARGET_INTEGRATORAP_CM946ES
bool "Support integratorap_cm946es"
select CPU_ARM946ES
@@ -620,9 +596,8 @@ config TEGRA
bool "NVIDIA Tegra"
select SUPPORT_SPL
select SPL
- select OF_CONTROL if !SPL_BUILD
- select CPU_ARM720T if SPL_BUILD
- select CPU_V7 if !SPL_BUILD
+ select OF_CONTROL
+ select CPU_V7
config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
@@ -714,7 +689,7 @@ config ARCH_UNIPHIER
select CPU_V7
select SUPPORT_SPL
select SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
endchoice
@@ -762,7 +737,6 @@ source "board/BuR/tseries/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/db-mv784mp-gp/Kconfig"
-source "board/Marvell/dkb/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/altera/socfpga/Kconfig"
source "board/armadeus/apf27/Kconfig"
@@ -779,8 +753,6 @@ source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
-source "board/cm4008/Kconfig"
-source "board/cm41xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
@@ -790,7 +762,6 @@ source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
-source "board/faraday/a320evb/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
@@ -853,14 +824,12 @@ source "board/st-ericsson/snowball/Kconfig"
source "board/st-ericsson/u8500/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
-source "board/syteco/jadecpu/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
-source "board/ti/tnetv107xevm/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/tqc/tqma6/Kconfig"
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
index ead2303373..480e130489 100644
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
@@ -12,4 +12,3 @@ extra-y = start.o
obj-y = cpu.o
obj-$(CONFIG_BCM2835) += bcm2835/
-obj-$(CONFIG_TNETV107X) += tnetv107x/
diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig
index 162f973f6c..73cc72b411 100644
--- a/arch/arm/cpu/arm1176/bcm2835/Kconfig
+++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig
@@ -1,12 +1,12 @@
if TARGET_RPI || TARGET_RPI_2
config DM
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
endif
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 0704bdde27..ac937bf5b0 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -96,28 +96,6 @@ mmu_disable:
mov pc, r2
mmu_disable_phys:
-#ifdef CONFIG_DISABLE_TCM
- /*
- * Disable the TCMs
- */
- mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
- cmp r0, #0
- beq skip_tcmdisable
- mov r1, #0
- mov r2, #1
- tst r0, r2
- mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
- tst r0, r2, LSL #16
- mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
- /* Peri port setup */
- ldr r0, =CONFIG_PERIPORT_BASE
- orr r0, r0, #CONFIG_PERIPORT_SIZE
- mcr p15,0,r0,c15,c2,4
#endif
/*
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
deleted file mode 100644
index a4c1edfc71..0000000000
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += aemif.o clock.o init.o mux.o timer.o
-obj-y += lowlevel_init.o
diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
deleted file mode 100644
index a0f57289e9..0000000000
--- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * TNETV107X: Asynchronous EMIF Configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4)
-#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c)
-#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60)
-#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4)
-
-#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
-#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
-#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26)
-#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20)
-#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17)
-#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13)
-#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7)
-#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4)
-#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2)
-#define CONFIG_WIDTH(v) (((v) & 0x03) << 0)
-
-#define NUM_CS 4
-
-#define set_config_field(reg, field, val) \
- do { \
- if (val != -1) { \
- reg &= ~CONFIG_##field(0xffffffff); \
- reg |= CONFIG_##field(val); \
- } \
- } while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
- unsigned long tmp;
-
- if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
- tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
-
- } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
- tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
- }
-
- tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
-
- set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
- set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
- set_config_field(tmp, WR_SETUP, cfg->wr_setup);
- set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
- set_config_field(tmp, WR_HOLD, cfg->wr_hold);
- set_config_field(tmp, RD_SETUP, cfg->rd_setup);
- set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
- set_config_field(tmp, RD_HOLD, cfg->rd_hold);
- set_config_field(tmp, TURN_AROUND, cfg->turn_around);
- set_config_field(tmp, WIDTH, cfg->width);
-
- __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
- int cs;
-
- clk_enable(TNETV107X_LPSC_AEMIF);
-
- for (cs = 0; cs < num_cs; cs++)
- configure_async_emif(cs, config + cs);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
deleted file mode 100644
index 7ba28d329f..0000000000
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * TNETV107X: Clock management APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/clock.h>
-
-#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
-#define PSC_BASE TNETV107X_PSC_BASE
-
-#define BIT(x) (1 << (x))
-
-#define MAX_PREDIV 64
-#define MAX_POSTDIV 8UL
-#define MAX_MULT 512
-#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
-
-/* LPSC registers */
-#define PSC_PTCMD 0x120
-#define PSC_PTSTAT 0x128
-#define PSC_MDSTAT(n) (0x800 + (n) * 4)
-#define PSC_MDCTL(n) (0xA00 + (n) * 4)
-
-#define PSC_MDCTL_LRSTZ BIT(8)
-
-#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
-#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
-
-/* SSPLL registers */
-struct sspll_regs {
- u32 modes;
- u32 postdiv;
- u32 prediv;
- u32 mult_factor;
- u32 divider_range;
- u32 bw_divider;
- u32 spr_amount;
- u32 spr_rate_div;
- u32 diag;
-};
-
-/* SSPLL base addresses */
-static struct sspll_regs *sspll_regs[] = {
- (struct sspll_regs *)(CLOCK_BASE + 0x040),
- (struct sspll_regs *)(CLOCK_BASE + 0x080),
- (struct sspll_regs *)(CLOCK_BASE + 0x0c0),
-};
-
-#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
-#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
-#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
-
-
-/* PLL Control Registers */
-struct pllctl_regs {
- u32 ctl; /* 00 */
- u32 ocsel; /* 04 */
- u32 secctl; /* 08 */
- u32 __pad0;
- u32 mult; /* 10 */
- u32 prediv; /* 14 */
- u32 div1; /* 18 */
- u32 div2; /* 1c */
- u32 div3; /* 20 */
- u32 oscdiv1; /* 24 */
- u32 postdiv; /* 28 */
- u32 bpdiv; /* 2c */
- u32 wakeup; /* 30 */
- u32 __pad1;
- u32 cmd; /* 38 */
- u32 stat; /* 3c */
- u32 alnctl; /* 40 */
- u32 dchange; /* 44 */
- u32 cken; /* 48 */
- u32 ckstat; /* 4c */
- u32 systat; /* 50 */
- u32 ckctl; /* 54 */
- u32 __pad2[2];
- u32 div4; /* 60 */
- u32 div5; /* 64 */
- u32 div6; /* 68 */
- u32 div7; /* 6c */
- u32 div8; /* 70 */
-};
-
-struct lpsc_map {
- int pll, div;
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
- (struct pllctl_regs *)(CLOCK_BASE + 0x700),
- (struct pllctl_regs *)(CLOCK_BASE + 0x300),
- (struct pllctl_regs *)(CLOCK_BASE + 0x500),
-};
-
-#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val) \
- pllctl_reg_write(pll, reg, \
- (pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, mask, 0)
-
-/* PLLCTL Bits */
-#define PLLCTL_CLKMODE BIT(8)
-#define PLLCTL_PLLSELB BIT(7)
-#define PLLCTL_PLLENSRC BIT(5)
-#define PLLCTL_PLLDIS BIT(4)
-#define PLLCTL_PLLRST BIT(3)
-#define PLLCTL_PLLPWRDN BIT(1)
-#define PLLCTL_PLLEN BIT(0)
-
-#define PLLDIV_ENABLE BIT(15)
-
-static int pll_div_offset[] = {
-#define div_offset(reg) offsetof(struct pllctl_regs, reg)
- div_offset(div1), div_offset(div2), div_offset(div3),
- div_offset(div4), div_offset(div5), div_offset(div6),
- div_offset(div7), div_offset(div8),
-};
-
-static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
-static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
-
-/* Mappings from PLL+DIV to subsystem clocks */
-#define sys_arm1176_clk {SYS_PLL, 0}
-#define sys_dsp_clk {SYS_PLL, 1}
-#define sys_ddr_clk {SYS_PLL, 2}
-#define sys_full_clk {SYS_PLL, 3}
-#define sys_lcd_clk {SYS_PLL, 4}
-#define sys_vlynq_ref_clk {SYS_PLL, 5}
-#define sys_tsc_clk {SYS_PLL, 6}
-#define sys_half_clk {SYS_PLL, 7}
-
-#define eth_clk_5 {ETH_PLL, 0}
-#define eth_clk_50 {ETH_PLL, 1}
-#define eth_clk_125 {ETH_PLL, 2}
-#define eth_clk_250 {ETH_PLL, 3}
-#define eth_clk_25 {ETH_PLL, 4}
-
-#define tdm_clk {TDM_PLL, 0}
-#define tdm_extra_clk {TDM_PLL, 1}
-#define tdm1_clk {TDM_PLL, 2}
-
-static const struct lpsc_map lpsc_clk_map[] = {
- [TNETV107X_LPSC_ARM] = sys_arm1176_clk,
- [TNETV107X_LPSC_GEM] = sys_dsp_clk,
- [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
- [TNETV107X_LPSC_TPCC] = sys_full_clk,
- [TNETV107X_LPSC_TPTC0] = sys_full_clk,
- [TNETV107X_LPSC_TPTC1] = sys_full_clk,
- [TNETV107X_LPSC_RAM] = sys_full_clk,
- [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
- [TNETV107X_LPSC_LCD] = sys_lcd_clk,
- [TNETV107X_LPSC_ETHSS] = eth_clk_125,
- [TNETV107X_LPSC_AEMIF] = sys_full_clk,
- [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
- [TNETV107X_LPSC_TSC] = sys_tsc_clk,
- [TNETV107X_LPSC_ROM] = sys_half_clk,
- [TNETV107X_LPSC_UART2] = sys_half_clk,
- [TNETV107X_LPSC_PKTSEC] = sys_half_clk,
- [TNETV107X_LPSC_SECCTL] = sys_half_clk,
- [TNETV107X_LPSC_KEYMGR] = sys_half_clk,
- [TNETV107X_LPSC_KEYPAD] = sys_half_clk,
- [TNETV107X_LPSC_GPIO] = sys_half_clk,
- [TNETV107X_LPSC_MDIO] = sys_half_clk,
- [TNETV107X_LPSC_SDIO0] = sys_half_clk,
- [TNETV107X_LPSC_UART0] = sys_half_clk,
- [TNETV107X_LPSC_UART1] = sys_half_clk,
- [TNETV107X_LPSC_TIMER0] = sys_half_clk,
- [TNETV107X_LPSC_TIMER1] = sys_half_clk,
- [TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
- [TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
- [TNETV107X_LPSC_SSP] = sys_half_clk,
- [TNETV107X_LPSC_TDM0] = tdm_clk,
- [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
- [TNETV107X_LPSC_MCDMA] = sys_half_clk,
- [TNETV107X_LPSC_USB0] = sys_half_clk,
- [TNETV107X_LPSC_TDM1] = tdm1_clk,
- [TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
- [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
- [TNETV107X_LPSC_SYSTEM] = sys_half_clk,
- [TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
- [TNETV107X_LPSC_SPARE] = sys_half_clk,
- [TNETV107X_LPSC_SDIO1] = sys_half_clk,
- [TNETV107X_LPSC_USB1] = sys_half_clk,
- [TNETV107X_LPSC_USBSS] = sys_half_clk,
- [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
- [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
-};
-
-static const unsigned long pll_ext_freq[] = {
- [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
- [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
- [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
-};
-
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, postdiv = 1;
- unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
- unsigned long ret;
- u32 bypass;
-
- bypass = __raw_readl((u32 *)(CLOCK_BASE));
- if (!(bypass & pll_bypass_mask[pll])) {
- mult = sspll_reg_read(pll, mult_factor);
- prediv = sspll_reg_read(pll, prediv) + 1;
- postdiv = sspll_reg_read(pll, postdiv) + 1;
- }
-
- if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
- ref = pll_ext_freq[pll];
-
- if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
- return ref;
-
- ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
- ret /= (prediv * postdiv);
-
- return ret;
-}
-
-static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
- int div)
-{
- int divider = 1;
- unsigned long divreg;
-
- divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
-
- if (divreg & PLLDIV_ENABLE)
- divider = (divreg & pll_div_mask[pll]) + 1;
-
- return fpll / divider;
-}
-
-static unsigned long pll_div_freq_get(int pll, int div)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
- unsigned long hz)
-{
- int divider = (fpll / hz - 1);
-
- divider &= pll_div_mask[pll];
- divider |= PLLDIV_ENABLE;
-
- __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
- pllctl_reg_setbits(pll, alnctl, (1 << div));
- pllctl_reg_setbits(pll, dchange, (1 << div));
-}
-
-static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- __pll_div_freq_set(pll, fpll, div, hz);
-
- pllctl_reg_write(pll, cmd, 1);
-
- /* Wait until new divider takes effect */
- while (pllctl_reg_read(pll, stat) & 0x01);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
-}
-
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
-{
- unsigned long fpll, divider, pll;
-
- pll = lpsc_clk_map[clk].pll;
- fpll = pll_freq_get(pll);
- divider = (fpll / hz - 1);
- divider &= pll_div_mask[pll];
-
- return fpll / (divider + 1);
-}
-
-int clk_set_rate(unsigned int clk, unsigned long _hz)
-{
- unsigned long hz;
-
- hz = clk_round_rate(clk, _hz);
- if (hz != _hz)
- return -EINVAL; /* Cannot set to target freq */
-
- pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
- return 0;
-}
-
-void lpsc_control(int mod, unsigned long state, int lrstz)
-{
- u32 mdctl;
-
- mdctl = psc_reg_read(PSC_MDCTL(mod));
- mdctl &= ~0x1f;
- mdctl |= state;
-
- if (lrstz == 0)
- mdctl &= ~PSC_MDCTL_LRSTZ;
- else if (lrstz == 1)
- mdctl |= PSC_MDCTL_LRSTZ;
-
- psc_reg_write(PSC_MDCTL(mod), mdctl);
-
- psc_reg_write(PSC_PTCMD, 1);
-
- /* wait for power domain transition to end */
- while (psc_reg_read(PSC_PTSTAT) & 1);
-
- /* Wait for module state change */
- while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
-}
-
-int lpsc_status(unsigned int id)
-{
- return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
-}
-
-static void init_pll(const struct pll_init_data *data)
-{
- unsigned long fpll;
- unsigned long best_pre = 0, best_post = 0, best_mult = 0;
- unsigned long div, prediv, postdiv, mult;
- unsigned long delta, actual;
- long best_delta = -1;
- int i;
- u32 tmp;
-
- if (data->pll == SYS_PLL)
- return; /* cannot reconfigure system pll on the fly */
-
- tmp = pllctl_reg_read(data->pll, ctl);
- if (data->internal_osc) {
- tmp &= ~PLLCTL_CLKMODE;
- fpll = CONFIG_SYS_INT_OSC_FREQ;
- } else {
- tmp |= PLLCTL_CLKMODE;
- fpll = pll_ext_freq[data->pll];
- }
- pllctl_reg_write(data->pll, ctl, tmp);
-
- mult = data->pll_freq / fpll;
- for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
- div = (fpll * mult) / data->pll_freq;
- if (div < 1 || div > MAX_DIV)
- continue;
-
- for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
- prediv = div / postdiv;
- if (prediv < 1 || prediv > MAX_PREDIV)
- continue;
-
- actual = (fpll / prediv) * (mult / postdiv);
- delta = (actual - data->pll_freq);
- if (delta < 0)
- delta = -delta;
- if ((delta < best_delta) || (best_delta == -1)) {
- best_delta = delta;
- best_mult = mult;
- best_pre = prediv;
- best_post = postdiv;
- if (delta == 0)
- goto done;
- }
- }
- }
-done:
-
- if (best_delta == -1) {
- printf("pll cannot derive %lu from %lu\n",
- data->pll_freq, fpll);
- return;
- }
-
- fpll = fpll * best_mult;
- fpll /= best_pre * best_post;
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
-
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
-
- sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
- sspll_reg_write(data->pll, prediv, best_pre - 1);
- sspll_reg_write(data->pll, postdiv, best_post - 1);
-
- for (i = 0; i < 10; i++)
- if (data->div_freq[i])
- __pll_div_freq_set(data->pll, fpll, i,
- data->div_freq[i]);
-
- pllctl_reg_write(data->pll, cmd, 1);
-
- /* Wait until pll "go" operation completes */
- while (pllctl_reg_read(data->pll, stat) & 0x01);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
- int i;
-
- for (i = 0; i < num_pll; i++)
- init_pll(&config[i]);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c
deleted file mode 100644
index d8708267d7..0000000000
--- a/arch/arm/cpu/arm1176/tnetv107x/init.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * TNETV107X: Architecture initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void chip_configuration_unlock(void)
-{
- __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
- __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
-}
-
-int arch_cpu_init(void)
-{
- icache_enable();
- chip_configuration_unlock();
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
deleted file mode 100644
index a8bce4784c..0000000000
--- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * TNETV107X: Low-level pre-relocation initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.globl lowlevel_init
-lowlevel_init:
- /* nothing for now, maybe needed for more exotic boot modes */
- mov pc, lr
diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c
deleted file mode 100644
index 310d84dfb4..0000000000
--- a/arch/arm/cpu/arm1176/tnetv107x/mux.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * TNETV107X: Pinmux configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define MUX_MODE_1 0x00
-#define MUX_MODE_2 0x04
-#define MUX_MODE_3 0x0c
-#define MUX_MODE_4 0x1c
-
-#define MUX_DEBUG 0
-
-static const struct pin_config pin_table[] = {
- /* reg shift mode */
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(11, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(11, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(19, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(20, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(26, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_2),
-};
-
-const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
-
-int mux_select_pin(short index)
-{
- const struct pin_config *cfg;
- unsigned long mask, mode, reg;
-
- if (index >= pin_table_size)
- return 0;
-
- cfg = &pin_table[index];
-
- mask = 0x1f << cfg->mask_offset;
- mode = cfg->mode << cfg->mask_offset;
-
- reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
- reg = (reg & ~mask) | mode;
- __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
-
- return 1;
-}
-
-int mux_select_pins(const short *pins)
-{
- int i, ret = 1;
-
- for (i = 0; pins[i] >= 0; i++)
- ret &= mux_select_pin(pins[i]);
-
- return ret;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c
deleted file mode 100644
index 6e0dd0d2bd..0000000000
--- a/arch/arm/cpu/arm1176/tnetv107x/timer.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * TNETV107X: Timer implementation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-struct timer_regs {
- u_int32_t pid12;
- u_int32_t pad[3];
- u_int32_t tim12;
- u_int32_t tim34;
- u_int32_t prd12;
- u_int32_t prd34;
- u_int32_t tcr;
- u_int32_t tgcr;
- u_int32_t wdtcr;
-};
-
-#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
-
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV 16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
- clk_enable(TNETV107X_LPSC_TIMER0);
-
- lastinc = timestamp = 0;
-
- /* We are using timer34 in unchained 32-bit mode, full speed */
- __raw_writel(0x0, &regs->tcr);
- __raw_writel(0x0, &regs->tgcr);
- __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
- __raw_writel(0x0, &regs->tim34);
- __raw_writel(TIMER_LOAD_VAL, &regs->prd34);
- __raw_writel(2 << 22, &regs->tcr);
-
- return 0;
-}
-
-static ulong get_timer_raw(void)
-{
- ulong now = __raw_readl(&regs->tim34);
-
- if (now >= lastinc)
- timestamp += now - lastinc;
- else
- timestamp += now + TIMER_LOAD_VAL - lastinc;
-
- lastinc = now;
-
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= (1000 * TIM_CLK_DIV);
-
- endtime = get_timer_raw() + tmo;
-
- do {
- ulong now = get_timer_raw();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index a16838b479..6582938db0 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -10,8 +10,6 @@ extra-y = start.o
obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
-obj-$(if $(filter a320,$(SOC)),y) += a320/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
-obj-$(CONFIG_KS8695) += ks8695/
obj-$(CONFIG_S3C24X0) += s3c24x0/
diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile
deleted file mode 100644
index bbdab588c5..0000000000
--- a/arch/arm/cpu/arm920t/a320/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += reset.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S
deleted file mode 100644
index 81f9dc983f..0000000000
--- a/arch/arm/cpu/arm920t/a320/reset.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.global reset_cpu
-reset_cpu:
- b reset_cpu
diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c
deleted file mode 100644
index 1ac5b60129..0000000000
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <faraday/ftpmu010.h>
-#include <faraday/fttmr010.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TIMER_CLOCK 32768
-#define TIMER_LOAD_VAL 0xffffffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->arch.timer_rate_hz);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= gd->arch.timer_rate_hz;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-int timer_init(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- unsigned int cr;
-
- debug("%s()\n", __func__);
-
- /* disable timers */
- writel(0, &tmr->cr);
-
- /* use 32768Hz oscillator for RTC, WDT, TIMER */
- ftpmu010_32768osc_enable();
-
- /* setup timer */
- writel(TIMER_LOAD_VAL, &tmr->timer3_load);
- writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
- writel(0, &tmr->timer3_match1);
- writel(0, &tmr->timer3_match2);
-
- /* we don't want timer to issue interrupts */
- writel(FTTMR010_TM3_MATCH1 |
- FTTMR010_TM3_MATCH2 |
- FTTMR010_TM3_OVERFLOW,
- &tmr->interrupt_mask);
-
- cr = readl(&tmr->cr);
- cr |= FTTMR010_TM3_CLOCK; /* use external clock */
- cr |= FTTMR010_TM3_ENABLE;
- writel(cr, &tmr->cr);
-
- gd->arch.timer_rate_hz = TIMER_CLOCK;
- gd->arch.tbu = gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long start;
- ulong tmo;
-
- start = get_ticks(); /* get current timestamp */
- tmo = usec_to_tick(usec); /* convert usecs to ticks */
- while ((get_ticks() - start) < tmo)
- ; /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
- return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile
deleted file mode 100644
index 400aa89e99..0000000000
--- a/arch/arm/cpu/arm920t/ks8695/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = lowlevel_init.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
deleted file mode 100644
index a2a07f2f23..0000000000
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * lowlevel_init.S - basic hardware initialization for the KS8695 CPU
- *
- * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/platform.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- *************************************************************************
- *
- * Handy dandy macros
- *
- *************************************************************************
- */
-
-/* Delay a bit */
-.macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
-.endm
-
-/*
- *************************************************************************
- *
- * Some local storage.
- *
- *************************************************************************
- */
-
-/* Should we boot with an interactive console or not */
-.globl serial_console
-
-/*
- *************************************************************************
- *
- * Raw hardware initialization code. The important thing is to get
- * SDRAM setup and running. We do some other basic things here too,
- * like getting the PLL set for high speed, and init the LEDs.
- *
- *************************************************************************
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-#if DEBUG
- /*
- * enable UART for early debug trace
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
- mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
- str r2, [r1]
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
- mov r2, #KS8695_UART_LINEC_WLEN8
- str r2, [r1] /* 8 data bits, no parity, 1 stop */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x41
- str r2, [r1] /* write 'A' */
-#endif
-#if DEBUG
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x42
- str r2, [r1]
-#endif
-
- /*
- * remap the memory and flash regions. we want to end up with
- * ram from address 0, and flash at 32MB.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
- ldr r2, =0xbfc00040
- str r2, [r1] /* large flash map */
- ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
-highflash:
- ldr r2, =0x8fe00040
- str r2, [r1] /* remap flash range */
-
- /*
- * remap the second select region to the 4MB immediately after
- * the first region. This way if you have a larger flash (say 8Mb)
- * then you can have it all mapped nicely. Has no effect if you
- * only have a 4Mb or smaller flash.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
- ldr r2, =0x9fe40040
- str r2, [r1] /* remap flash2 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30000005
- str r2, [r1] /* enable both flash selects */
-
-#ifdef CONFIG_CM41xx
- /*
- * map the second flash chip, using the external IO lines.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
- ldr r2, =0xafe80b6d
- str r2, [r1] /* remap io0 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
- ldr r2, =0xbfec0b6d
- str r2, [r1] /* remap io1 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30050005
- str r2, [r1] /* enable second flash */
-#endif
-
- /*
- * before relocating, we have to setup RAM timing
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
- ldr r2, =0x7fc0000e /* 32MB */
-#else
- ldr r2, =0x3fc0000e /* 16MB */
-#endif
- str r2, [r1] /* configure sdram bank0 setup */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
- mov r2, #0
- str r2, [r1] /* configure sdram bank1 setup */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
- ldr r2, =0x0000000a
- str r2, [r1] /* set RAS/CAS timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00030000
- str r2, [r1] /* send NOP command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00010000
- str r2, [r1] /* send PRECHARGE-ALL */
- DELAY_FOR 0x100, r0
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
- ldr r2, =0x00000020
- str r2, [r1] /* set for fast refresh */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00000190
- str r2, [r1] /* set normal refresh timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00020033
- str r2, [r1] /* send mode command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x01f00000
- str r2, [r1] /* enable sdram fifos */
-
- /*
- * set pll to top speed
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
- mov r2, #0
- str r2, [r1] /* set pll clock to 166MHz */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
- ldr r2, [r1] /* Get switch ctrl0 register */
- and r2, r2, #0x0fc00000 /* Mask out LED control bits */
- orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
- str r2, [r1]
-
-#ifdef CONFIG_CM4008
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
- ldr r2, =0x0000fe30
- str r2, [r1] /* enable LED's as outputs */
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
- ldr r2, =0x0000fe20
- str r2, [r1] /* turn on power LED */
-#endif
-#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
- ldr r2, [r1] /* get current GPIO input data */
- tst r2, #0x8 /* check if "erase" depressed */
- beq nobutton
- mov r2, #0 /* be quiet on boot, no console */
- ldr r1, =serial_console
- str r2, [r1]
-nobutton:
-#endif
-
- add lr, lr, #0x02000000 /* flash is now mapped high */
- add ip, ip, #0x02000000 /* this is a hack */
- mov pc, lr /* all done, return */
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c
deleted file mode 100644
index 23db5572de..0000000000
--- a/arch/arm/cpu/arm920t/ks8695/timer.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-
-/*
- * Initial timer set constants. Nothing complicated, just set for a 1ms
- * tick.
- */
-#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
-#define TIMER_COUNT (TIMER_INTERVAL / 2)
-#define TIMER_PULSE TIMER_COUNT
-
-/*
- * Handy KS8695 register access functions.
- */
-#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
-#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
-
-ulong timer_ticks;
-
-int timer_init (void)
-{
- /* Set the hadware timer for 1ms */
- ks8695_write(KS8695_TIMER1, TIMER_COUNT);
- ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
- ks8695_write(KS8695_TIMER_CTRL, 0x2);
- timer_ticks = 0;
-
- return 0;
-}
-
-ulong get_timer_masked(void)
-{
- /* Check for timer wrap */
- if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
- /* Clear interrupt condition */
- ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
- timer_ticks++;
- }
- return timer_ticks;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_masked() - base);
-}
-
-void __udelay(ulong usec)
-{
- ulong start = get_timer_masked();
- ulong end;
-
- /* Only 1ms resolution :-( */
- end = usec / 1000;
- while (get_timer(start) < end)
- ;
-}
-
-void reset_cpu (ulong ignored)
-{
- ulong tc;
-
- /* Set timer0 to watchdog, and let it timeout */
- tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
- ks8695_write(KS8695_TIMER_CTRL, tc);
- ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
- ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
-
- /* Should only wait here till watchdog resets */
- for (;;)
- ;
-}
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index f5944cc965..63fa159db6 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -16,9 +16,7 @@ endif
obj-$(CONFIG_ARMADA100) += armada100/
obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
-obj-$(CONFIG_MB86R0x) += mb86r0x/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
-obj-$(CONFIG_PANTHEON) += pantheon/
obj-$(if $(filter spear,$(SOC)),y) += spear/
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
deleted file mode 100644
index 365892c413..0000000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = clock.o reset.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
deleted file mode 100644
index 1f6f66eba2..0000000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Get the peripheral bus frequency depending on pll pin settings
- */
-ulong get_bus_freq(ulong dummy)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
- uint32_t pllmode;
-
- pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
-
- if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
- return 40000000;
-
- return 41164767;
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
deleted file mode 100644
index 7bd77ff202..0000000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Reset the cpu by setting software reset request bit
- */
-void reset_cpu(ulong ignored)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
-
- writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
- while (1)
- /* NOP */;
- /* Never reached */
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
deleted file mode 100644
index bb078196d0..0000000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <div64.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, TIMER_FREQ);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= TIMER_FREQ;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong ctrl = readl(&timer->control);
-
- writel(TIMER_LOAD_VAL, &timer->load);
-
- ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
- MB86R0x_TIMER_SIZE_32;
-
- writel(ctrl, &timer->control);
-
- /* capture current value time */
- lastdec = readl(&timer->value);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-unsigned long long get_ticks(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong now = readl(&timer->value);
-
- if (now <= lastdec) {
- /* normal mode (non roll) */
- /* move stamp forward with absolut diff ticks */
- timestamp += lastdec - now;
- } else {
- /* we have rollover of incrementer */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
- lastdec = now;
- return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = usec_to_tick(usec);
- tmp = get_ticks(); /* get current timestamp */
-
- while ((get_ticks() - tmp) < tmo) /* loop till event */
- /*NOP*/;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
- tbclk = TIMER_FREQ;
- return tbclk;
-}
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
deleted file mode 100644
index 988341f8fb..0000000000
--- a/arch/arm/cpu/arm926ejs/pantheon/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
deleted file mode 100644
index 4e2a177c0d..0000000000
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID (1<<8)
-#define L2C_RAM_SEL (1<<4)
-
-int arch_cpu_init(void)
-{
- u32 val;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- struct panthapb_registers *apbclkres =
- (struct panthapb_registers*) PANTHEON_APBC_BASE;
-
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
-
- struct panthapmu_registers *apmu =
- (struct panthapmu_registers *) PANTHEON_APMU_BASE;
-
- /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
- val = readl(&cpuregs->cpu_conf);
- val = val | SET_MRVL_ID;
- writel(val, &cpuregs->cpu_conf);
-
- /* Turn on clock gating (PMUM_CCGR) */
- writel(0xFFFFFFFF, &mpmu->ccgr);
-
- /* Turn on clock gating (PMUM_ACGR) */
- writel(0xFFFFFFFF, &mpmu->acgr);
-
- /* Turn on uart2 clock */
- writel(UARTCLK14745KHZ, &apbclkres->uart0);
-
- /* Enable GPIO clock */
- writel(APBC_APBCLK, &apbclkres->gpio);
-
-#ifdef CONFIG_I2C_MV
- /* Enable I2C clock */
- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
- writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
-#endif
-
-#ifdef CONFIG_MV_SDHCI
- /* Enable mmc clock */
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd1);
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd3);
-#endif
-
- icache_enable();
-
- return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u32 id;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- id = readl(&cpuregs->chip_id);
- printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
deleted file mode 100644
index f77e3d0ab5..0000000000
--- a/arch/arm/cpu/arm926ejs/pantheon/dram.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>,
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pantheon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Pantheon DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet 4.4
- */
-struct panthddr_map_registers {
- u32 cs; /* Memory Address Map Register -CS */
- u32 pad[3];
-};
-
-struct panthddr_registers {
- u8 pad[0x100 - 0x000];
- struct panthddr_map_registers mmap[2];
-};
-
-/*
- * panth_sdram_base - reads SDRAM Base Address Register
- */
-u32 panth_sdram_base(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
- return result;
-}
-
-/*
- * panth_sdram_size - reads SDRAM size
- */
-u32 panth_sdram_size(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs);
- result = (result >> 16) & 0xF;
- if (result < 0x7) {
- printf("Unknown DRAM Size\n");
- return -1;
- } else {
- return ((0x8 << (result - 0x7)) * 1024 * 1024);
- }
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
- int i;
-
- gd->ram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = panth_sdram_base(i);
- gd->bd->bi_dram[i].size = panth_sdram_size(i);
- /*
- * It is assumed that all memory banks are consecutive
- * and without gaps.
- * If the gap is found, ram_size will be reported for
- * consecutive memory only
- */
- if (gd->bd->bi_dram[i].start != gd->ram_size)
- break;
-
- gd->ram_size += gd->bd->bi_dram[i].size;
-
- }
-
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- /*
- * If above loop terminated prematurely, we need to set
- * remaining banks' start address & size as 0. Otherwise other
- * u-boot functions and Linux kernel gets wrong values which
- * could result in crash
- */
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
- return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
- dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
deleted file mode 100644
index 6382d3b0cf..0000000000
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-/*
- * Timer registers
- * Refer 6.2.9 in Datasheet
- */
-struct panthtmr_registers {
- u32 clk_ctrl; /* Timer clk control reg */
- u32 match[9]; /* Timer match registers */
- u32 count[3]; /* Timer count registers */
- u32 status[3];
- u32 ie[3];
- u32 preload[3]; /* Timer preload value */
- u32 preload_ctrl[3];
- u32 wdt_match_en;
- u32 wdt_match_r;
- u32 wdt_val;
- u32 wdt_sts;
- u32 icr[3];
- u32 wdt_icr;
- u32 cer; /* Timer count enable reg */
- u32 cmr;
- u32 ilr[3];
- u32 wcr;
- u32 wfar;
- u32 wsar;
- u32 cvwr[3];
-};
-
-#define TIMER 0 /* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x) ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 0xffffffff
-#define COUNT_RD_REQ 0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/*
- * For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
- volatile int loop=100;
- ulong val;
-
- writel(COUNT_RD_REQ, &panthtimers->cvwr);
- while (loop--)
- val = readl(&panthtimers->cvwr);
-
- /*
- * This stop gcc complain and prevent loop mistake init to 0
- */
- val = readl(&panthtimers->cvwr);
-
- return val;
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (now >= gd->arch.tbl) {
- /* normal mode */
- gd->arch.tbu += now - gd->arch.tbl;
- } else {
- /* we have an overflow ... */
- gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
- }
- gd->arch.tbl = now;
-
- return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
- return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
- base);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong delayticks;
- ulong endtime;
-
- delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
- endtime = get_timer_masked() + delayticks;
-
- while (get_timer_masked() < endtime)
- ;
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
- struct panthapb_registers *apb1clkres =
- (struct panthapb_registers *) PANTHEON_APBC_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-
- /* Enable Timer clock at 3.25 MHZ */
- writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
- /* load value into timer */
- writel(0x0, &panthtimers->clk_ctrl);
- /* Use Timer 0 Match Resiger 0 */
- writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
- /* Preload value is 0 */
- writel(0x0, &panthtimers->preload[TIMER]);
- /* Enable match comparator 0 for Timer 0 */
- writel(0x1, &panthtimers->preload_ctrl[TIMER]);
-
- /* Enable timer 0 */
- writel(0x1, &panthtimers->cer);
- /* init the gd->arch.tbu and gd->arch.tbl value */
- gd->arch.tbl = read_timer();
- gd->arch.tbu = 0;
-
- return 0;
-}
-
-#define MPMU_APRR_WDTR (1<<4)
-#define TMR_WFAR 0xbaba /* WDT Register First key */
-#define TMP_WSAR 0xeb10 /* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
- u32 val;
-
- /* negate hardware reset to the WDT after system reset */
- val = readl(&mpmu->aprr);
- val = val | MPMU_APRR_WDTR;
- writel(val, &mpmu->aprr);
-
- /* reset/enable WDT clock */
- writel(APBC_APBCLK, &mpmu->wdtpcr);
-
- /* clear previous WDT status */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0, &panthtimers->wdt_sts);
-
- /* set match counter */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0xf, &panthtimers->wdt_match_r);
-
- /* enable WDT reset */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0x3, &panthtimers->wdt_match_en);
-
- /*enable functional WDT clock */
- writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index 2064efa761..eb86a7fe7d 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -6,7 +6,7 @@ choice
config TARGET_SMDKV310
select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_TRATS
bool "Exynos4210 Trats board"
@@ -33,32 +33,32 @@ config TARGET_ARNDALE
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SMDK5250
bool "SMDK5250 board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SNOW
bool "Snow board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SMDK5420
bool "SMDK5420 board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_PEACH_PI
bool "Peach Pi board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_PEACH_PIT
bool "Peach Pit board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
endchoice
@@ -66,25 +66,25 @@ config SYS_SOC
default "exynos"
config DM
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
config DM_SPI
- default y if !SPL_BUILD
+ default y
config DM_SPI_FLASH
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
config SYS_MALLOC_F
- default y if !SPL_BUILD
+ default y
config SYS_MALLOC_F_LEN
- default 0x400 if !SPL_BUILD
+ default 0x400
source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index ce2d92f5a6..1a640bbb9c 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -8,14 +8,214 @@
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/cache.h>
+#include <asm/system.h>
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#include "fsl_epu.h"
+#define DCSR_RCPM2_BLOCK_OFFSET 0x223000
+#define DCSR_RCPM2_CPMFSMCR0 0x400
+#define DCSR_RCPM2_CPMFSMSR0 0x404
+#define DCSR_RCPM2_CPMFSMCR1 0x414
+#define DCSR_RCPM2_CPMFSMSR1 0x418
+#define CPMFSMSR_FSM_STATE_MASK 0x7f
+
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Bit[1] of the descriptor indicates the descriptor type,
+ * and bit[0] indicates whether the descriptor is valid.
+ */
+#define PMD_TYPE_TABLE 0x3
+#define PMD_TYPE_SECT 0x1
+
+/* AttrIndx[2:0] */
+#define PMD_ATTRINDX(t) ((t) << 2)
+
+/* Section */
+#define PMD_SECT_AF (1 << 10)
+
+#define BLOCK_SIZE_L1 (1UL << 30)
+#define BLOCK_SIZE_L2 (1UL << 21)
+
+/* TTBCR flags */
+#define TTBCR_EAE (1 << 31)
+#define TTBCR_T0SZ(x) ((x) << 0)
+#define TTBCR_T1SZ(x) ((x) << 16)
+#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
+#define TTBCR_IRGN0_NC (0 << 8)
+#define TTBCR_IRGN0_WBWA (1 << 8)
+#define TTBCR_IRGN0_WT (2 << 8)
+#define TTBCR_IRGN0_WBNWA (3 << 8)
+#define TTBCR_IRGN0_MASK (3 << 8)
+#define TTBCR_ORGN0_NC (0 << 10)
+#define TTBCR_ORGN0_WBWA (1 << 10)
+#define TTBCR_ORGN0_WT (2 << 10)
+#define TTBCR_ORGN0_WBNWA (3 << 10)
+#define TTBCR_ORGN0_MASK (3 << 10)
+#define TTBCR_SHARED_NON (0 << 12)
+#define TTBCR_SHARED_OUTER (2 << 12)
+#define TTBCR_SHARED_INNER (3 << 12)
+#define TTBCR_EPD0 (0 << 7)
+#define TTBCR (TTBCR_SHARED_NON | \
+ TTBCR_ORGN0_NC | \
+ TTBCR_IRGN0_NC | \
+ TTBCR_USING_TTBR0 | \
+ TTBCR_EAE)
+
+/*
+ * Memory region attributes for LPAE (defined in pgtable):
+ *
+ * n = AttrIndx[2:0]
+ *
+ * n MAIR
+ * UNCACHED 000 00000000
+ * BUFFERABLE 001 01000100
+ * DEV_WC 001 01000100
+ * WRITETHROUGH 010 10101010
+ * WRITEBACK 011 11101110
+ * DEV_CACHED 011 11101110
+ * DEV_SHARED 100 00000100
+ * DEV_NONSHARED 100 00000100
+ * unused 101
+ * unused 110
+ * WRITEALLOC 111 11111111
+ */
+#define MT_MAIR0 0xeeaa4400
+#define MT_MAIR1 0xff000004
+#define MT_STRONLY_ORDER 0
+#define MT_NORMAL_NC 1
+#define MT_DEVICE_MEM 4
+#define MT_NORMAL 7
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
+{
+ u32 value = phy_addr | PMD_TYPE_TABLE;
+
+ page_table[2 * index] = value;
+ page_table[2 * index + 1] = 0;
+}
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
+ u32 memory_type)
+{
+ u64 value;
+
+ value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
+ value |= PMD_ATTRINDX(memory_type);
+ page_table[2 * index] = value & 0xFFFFFFFF;
+ page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
+}
+
+/*
+ * Start MMU after DDR is available, we create MMU table in DRAM.
+ * The base address of TTLB is gd->arch.tlb_addr. We use two
+ * levels of translation tables here to cover 40-bit address space.
+ *
+ * The TTLBs are located at PHY 2G~4G.
+ *
+ * VA mapping:
+ *
+ * ------- <---- 0GB
+ * | |
+ * | |
+ * |-------| <---- 0x24000000
+ * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
+ * |-------| <---- 0x300000000
+ * | |
+ * |-------| <---- 0x34000000
+ * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
+ * |-------| <---- 0x40000000
+ * | |
+ * |-------| <---- 0x80000000 DDR0 space start
+ * |\\\\\\\|
+ *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
+ * |\\\\\\\|
+ * ------- <---- 4GB DDR0 space end
+ */
+static void mmu_setup(void)
+{
+ u32 *level0_table = (u32 *)gd->arch.tlb_addr;
+ u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
+ u64 va_start = 0;
+ u32 reg;
+ int i;
+
+ /* Level 0 Table 2-3 are used to map DDR */
+ set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
+ set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
+ /* Level 0 Table 1 is used to map device */
+ set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
+ /* Level 0 Table 0 is used to map device including PCIe MEM */
+ set_pgtable(level0_table, 0, (u32)level1_table);
+
+ /* Level 1 has 512 entries */
+ for (i = 0; i < 512; i++) {
+ /* Mapping for PCIe 1 */
+ if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
+ va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
+ CONFIG_SYS_PCIE_MMAP_SIZE))
+ set_pgsection(level1_table, i,
+ CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+ MT_DEVICE_MEM);
+ /* Mapping for PCIe 2 */
+ else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
+ va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
+ CONFIG_SYS_PCIE_MMAP_SIZE))
+ set_pgsection(level1_table, i,
+ CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+ MT_DEVICE_MEM);
+ else
+ set_pgsection(level1_table, i,
+ va_start,
+ MT_DEVICE_MEM);
+ va_start += BLOCK_SIZE_L2;
+ }
+
+ asm volatile("dsb sy;isb");
+ asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
+ : : "r" (TTBCR) : "memory");
+ asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
+ : : "r" ((u32)level0_table), "r" (0) : "memory");
+ asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
+ : : "r" (MT_MAIR0) : "memory");
+ asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
+ : : "r" (MT_MAIR1) : "memory");
+
+ /* Set the access control to all-supervisor */
+ asm volatile("mcr p15, 0, %0, c3, c0, 0"
+ : : "r" (~0));
+
+ /* Enable the mmu */
+ reg = get_cr();
+ set_cr(reg | CR_M);
+}
+
+/*
+ * This function is called from lib/board.c. It recreates MMU
+ * table in main memory. MMU and i/d-cache are enabled here.
+ */
+void enable_caches(void)
+{
+ /* Invalidate all TLB */
+ mmu_page_table_flush(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ /* Set up and enable mmu */
+ mmu_setup();
+
+ /* Invalidate & Enable d-cache */
+ invalidate_dcache_all();
+ set_cr(get_cr() | CR_C);
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
@@ -78,16 +278,6 @@ int print_cpuinfo(void)
}
#endif
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
#ifdef CONFIG_FSL_ESDHC
int cpu_mmc_init(bd_t *bis)
{
@@ -107,6 +297,27 @@ int cpu_eth_init(bd_t *bis)
int arch_cpu_init(void)
{
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *rcpm2_base =
+ (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ u32 state;
+
+ /*
+ * The RCPM FSM state may not be reset after power-on.
+ * So, reset them.
+ */
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
+ }
+
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
+ }
/*
* After wakeup from deep sleep, Clear EPU registers
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 46440981b3..4a0ac2c987 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -94,19 +94,19 @@ config TARGET_TWISTER
endchoice
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if DM && !SPL_BUILD
+ default y if DM
config DM_SERIAL
- default y if DM && !SPL_BUILD
+ default y if DM
config SYS_MALLOC_F
- default y if DM && !SPL_BUILD
+ default y if DM
config SYS_MALLOC_F_LEN
- default 0x400 if DM && !SPL_BUILD
+ default 0x400 if DM
config SYS_SOC
default "omap3"
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
index 628813423f..bc73813832 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig
+++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
@@ -5,11 +5,11 @@ choice
config TARGET_S5P_GONI
bool "S5P Goni board"
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SMDKC100
bool "Support smdkc100 board"
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
endchoice
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 1a47ac9029..8335685e32 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -52,7 +52,7 @@ config SYS_MALLOC_F
default y
config SYS_MALLOC_F_LEN
- default 0x2000
+ default 0x400
config CMD_PINMON
bool "Enable boot mode pins monitor command"
@@ -64,14 +64,12 @@ config CMD_PINMON
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
- depends on !SPL_BUILD
help
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
choice
prompt "DDR3 Frequency select"
- depends on SPL_BUILD
config DDR_FREQ_1600
bool "DDR3 1600"
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 9c6e8243bb..fa447bce16 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -155,3 +155,9 @@ ENTRY(__asm_invalidate_icache_all)
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)
+
+ENTRY(__asm_flush_l3_cache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_flush_l3_cache)
+ .weak __asm_flush_l3_cache
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 9dbcdf22af..c5ec5297cd 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -73,17 +73,21 @@ void invalidate_dcache_all(void)
__asm_invalidate_dcache_all();
}
-void __weak flush_l3_cache(void)
-{
-}
-
/*
- * Performs a clean & invalidation of the entire data cache at all levels
+ * Performs a clean & invalidation of the entire data cache at all levels.
+ * This function needs to be inline to avoid using stack.
+ * __asm_flush_l3_cache return status of timeout
*/
-void flush_dcache_all(void)
+inline void flush_dcache_all(void)
{
+ int ret;
+
__asm_flush_dcache_all();
- flush_l3_cache();
+ ret = __asm_flush_l3_cache();
+ if (ret)
+ debug("flushing dcache returns 0x%x\n", ret);
+ else
+ debug("flushing dcache successfully.\n");
}
/*
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 47b947f44f..49974878b9 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -10,10 +10,10 @@
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/fsl_mc.h>
#include "cpu.h"
#include "mp.h"
#include "speed.h"
-#include <fsl_mc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -150,7 +150,7 @@ static inline void final_mmu_setup(void)
* set level 2 table 0 to cache-inhibit, covering 0 to 1GB
*/
section_l1t0 = 0;
- section_l1t1 = BLOCK_SIZE_L0;
+ section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE;
section_l2 = 0;
for (i = 0; i < 512; i++) {
set_pgtable_section(level1_table_0, i, section_l1t0,
@@ -168,10 +168,10 @@ static inline void final_mmu_setup(void)
(u64)level2_table_0 | PMD_TYPE_TABLE;
level1_table_0[2] =
0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_ATTRINDX(MT_NORMAL);
+ PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
level1_table_0[3] =
0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_ATTRINDX(MT_NORMAL);
+ PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
/* Rewrite table to enable cache */
set_pgtable_section(level2_table_0,
@@ -243,59 +243,6 @@ int arch_cpu_init(void)
}
/*
- * flush_l3_cache
- * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power
- * state, by writing to HP-F P-state request register.
- * Fixme: This function should moved to a common file if other SoCs also use
- * the same Dickens.
- */
-#define HNF0_PSTATE_REQ 0x04200010
-#define HNF1_PSTATE_REQ 0x04210010
-#define HNF2_PSTATE_REQ 0x04220010
-#define HNF3_PSTATE_REQ 0x04230010
-#define HNF4_PSTATE_REQ 0x04240010
-#define HNF5_PSTATE_REQ 0x04250010
-#define HNF6_PSTATE_REQ 0x04260010
-#define HNF7_PSTATE_REQ 0x04270010
-#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC)
-#define HNFPSTAT_FAM 0x3
-#define HNFPSTAT_SFONLY 0x01
-
-static void hnf_pstate_req(u64 *ptr, u64 state)
-{
- int timeout = 1000;
- out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3));
- ptr++;
- /* checking if the transition is completed */
- while (timeout > 0) {
- if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3))
- break;
- udelay(100);
- timeout--;
- }
-}
-
-void flush_l3_cache(void)
-{
- hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM);
-}
-
-/*
* This function is called from lib/board.c.
* It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
* There is no need to disable d-cache for this operation.
@@ -420,6 +367,7 @@ int print_cpuinfo(void)
printf("\n Bus: %-4s MHz ",
strmhz(buf, sysinfo.freq_systembus));
printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
+ printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
puts("\n");
return 0;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
index e392eb9149..7eb9b6aa4b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -16,7 +16,7 @@ void ft_fixup_cpu(void *blob)
__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
fdt32_t *reg;
int addr_cells;
- u64 val;
+ u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
off = fdt_path_offset(blob, "/cpus");
@@ -29,15 +29,20 @@ void ft_fixup_cpu(void *blob)
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+ core_id = of_read_number(reg, addr_cells);
if (reg) {
- val = spin_tbl_addr;
- val += id_to_core(of_read_number(reg, addr_cells))
- * SPIN_TABLE_ELEM_SIZE;
- val = cpu_to_fdt64(val);
- fdt_setprop_string(blob, off, "enable-method",
- "spin-table");
- fdt_setprop(blob, off, "cpu-release-addr",
- &val, sizeof(val));
+ if (core_id == 0 || (is_core_online(core_id))) {
+ val = spin_tbl_addr;
+ val += id_to_core(core_id) *
+ SPIN_TABLE_ELEM_SIZE;
+ val = cpu_to_fdt64(val);
+ fdt_setprop_string(blob, off, "enable-method",
+ "spin-table");
+ fdt_setprop(blob, off, "cpu-release-addr",
+ &val, sizeof(val));
+ } else {
+ debug("skipping offline core\n");
+ }
} else {
puts("Warning: found cpu node without reg property\n");
}
@@ -55,4 +60,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_MP
ft_fixup_cpu(blob);
#endif
+
+#ifdef CONFIG_SYS_NS16550
+ do_fixup_by_compat_u32(blob, "ns16550",
+ "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+#endif
}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 2a88aab283..886576ef99 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -42,10 +42,142 @@ ENTRY(lowlevel_init)
ldr x0, =secondary_boot_func
blr x0
2:
+
+#ifdef CONFIG_FSL_TZPC_BP147
+ /* Set Non Secure access for all devices protected via TZPC */
+ ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
+ orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
+ str w0, [x1]
+
+ isb
+ dsb sy
+#endif
+
+#ifdef CONFIG_FSL_TZASC_400
+ /* Set TZASC so that:
+ * a. We use only Region0 whose global secure write/read is EN
+ * b. We use only Region0 whose NSAID write/read is EN
+ *
+ * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
+ * placeholders.
+ */
+ ldr x1, =TZASC_GATE_KEEPER(0)
+ ldr x0, [x1] /* Filter 0 Gate Keeper Register */
+ orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
+ str x0, [x1]
+
+ ldr x1, =TZASC_GATE_KEEPER(1)
+ ldr x0, [x1] /* Filter 0 Gate Keeper Register */
+ orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
+ str x0, [x1]
+
+ ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
+ ldr x0, [x1] /* Region-0 Attributes Register */
+ orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str x0, [x1]
+
+ ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
+ ldr x0, [x1] /* Region-1 Attributes Register */
+ orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str x0, [x1]
+
+ ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
+ ldr w0, [x1] /* Region-0 Access Register */
+ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
+ str w0, [x1]
+
+ ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
+ ldr w0, [x1] /* Region-1 Attributes Register */
+ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
+ str w0, [x1]
+
+ isb
+ dsb sy
+#endif
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
+hnf_pstate_poll:
+ /* x0 has the desired status, return 0 for success, 1 for timeout
+ * clobber x1, x2, x3, x4, x6, x7
+ */
+ mov x1, x0
+ mov x7, #0 /* flag for timeout */
+ mrs x3, cntpct_el0 /* read timer */
+ add x3, x3, #1200 /* timeout after 100 microseconds */
+ mov x0, #0x18
+ movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
+ mov w6, #8 /* HN-F node count */
+1:
+ ldr x2, [x0]
+ cmp x2, x1 /* check status */
+ b.eq 2f
+ mrs x4, cntpct_el0
+ cmp x4, x3
+ b.ls 1b
+ mov x7, #1 /* timeout */
+ b 3f
+2:
+ add x0, x0, #0x10000 /* move to next node */
+ subs w6, w6, #1
+ cbnz w6, 1b
+3:
+ mov x0, x7
+ ret
+
+hnf_set_pstate:
+ /* x0 has the desired state, clobber x1, x2, x6 */
+ mov x1, x0
+ /* power state to SFONLY */
+ mov w6, #8 /* HN-F node count */
+ mov x0, #0x10
+ movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
+1: /* set pstate to sfonly */
+ ldr x2, [x0]
+ and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
+ orr x2, x2, x1
+ str x2, [x0]
+ add x0, x0, #0x10000 /* move to next node */
+ subs w6, w6, #1
+ cbnz w6, 1b
+
+ ret
+
+ENTRY(__asm_flush_l3_cache)
+ /*
+ * Return status in x0
+ * success 0
+ * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
+ */
+ mov x29, lr
+ mov x8, #0
+
+ dsb sy
+ mov x0, #0x1 /* HNFPSTAT_SFONLY */
+ bl hnf_set_pstate
+
+ mov x0, #0x4 /* SFONLY status */
+ bl hnf_pstate_poll
+ cbz x0, 1f
+ mov x8, #1 /* timeout */
+1:
+ dsb sy
+ mov x0, #0x3 /* HNFPSTAT_FAM */
+ bl hnf_set_pstate
+
+ mov x0, #0xc /* FAM status */
+ bl hnf_pstate_poll
+ cbz x0, 1f
+ add x8, x8, #0x2
+1:
+ mov x0, x8
+ mov lr, x29
+ ret
+ENDPROC(__asm_flush_l3_cache)
+
/* Keep literals not used by the secondary boot code outside it */
.ltorg
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
index 94998bf37b..ce9c0c1bdb 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
@@ -83,6 +83,14 @@ int is_core_valid(unsigned int core)
return !!((1 << core) & cpu_mask());
}
+int is_core_online(u64 cpu_id)
+{
+ u64 *table;
+ int pos = id_to_core(cpu_id);
+ table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
+ return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
+}
+
int cpu_reset(int nr)
{
puts("Feature is not implemented.\n");
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
index 06ac0bcf36..66144d6101 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
@@ -32,5 +32,6 @@ int fsl_lsch3_wake_seconday_cores(void);
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
+int is_core_online(u64 cpu_id);
#endif
#endif /* _FSL_CH3_MP_H */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index dc4a34bce5..72cd999c5f 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -77,8 +77,10 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
#else
sys_info->freq_ddrbus = sysclk;
+ sys_info->freq_ddrbus2 = sysclk;
#endif
sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
@@ -87,6 +89,9 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+ sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
/*
@@ -129,7 +134,7 @@ int get_clocks(void)
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
-
+ gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif /* defined(CONFIG_FSL_ESDHC) */
@@ -156,11 +161,18 @@ ulong get_bus_freq(ulong dummy)
* get_ddr_freq
* return ddr bus freq in Hz
*********************************************/
-ulong get_ddr_freq(ulong dummy)
+ulong get_ddr_freq(ulong ctrl_num)
{
if (!gd->mem_clk)
get_clocks();
+ /*
+ * DDR controller 0 & 1 are on memory complex 0
+ * DDR controler 2 is on memory complext 1
+ */
+ if (ctrl_num >= 2)
+ return gd->arch.mem2_clk;
+
return gd->mem_clk;
}
diff --git a/arch/arm/include/asm/arch-a320/a320.h b/arch/arm/include/asm/arch-a320/a320.h
deleted file mode 100644
index f2db8e1061..0000000000
--- a/arch/arm/include/asm/arch-a320/a320.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __A320_H
-#define __A320_H
-
-/*
- * Hardware register bases
- */
-#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
-#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
-#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
-#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
-#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
-#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
-#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
-
-#endif /* __A320_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index da551e8839..b140c1fac2 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -30,11 +30,44 @@
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
+#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
+
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE 0x02200000
+#define TZPCR0SIZE_BASE (TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
+#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
+#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
+#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06100000
@@ -68,4 +101,9 @@
#error SoC not defined
#endif
+#ifdef CONFIG_LS2085A
+#define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008514
+#endif
+
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index ee1d6512d9..dd11ef79c8 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -15,6 +15,7 @@ struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
unsigned long freq_ddrbus;
+ unsigned long freq_ddrbus2;
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -60,6 +61,8 @@ struct ccsr_gur {
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
u8 res_280[0x300-0x280];
diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h
deleted file mode 100644
index 02f6049263..0000000000
--- a/arch/arm/include/asm/arch-ks8695/platform.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __address_h
-#define __address_h 1
-
-#define KS8695_SDRAM_START 0x00000000
-#define KS8695_SDRAM_SIZE 0x01000000
-#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE
-#define KS8695_MEM_START KS8695_SDRAM_START
-
-#define KS8695_PCMCIA_IO_BASE 0x03800000
-#define KS8695_PCMCIA_IO_SIZE 0x00040000
-
-#define KS8695_IO_BASE 0x03FF0000
-#define KS8695_IO_SIZE 0x00010000
-
-#define KS8695_SYSTEN_CONFIG 0x00
-#define KS8695_SYSTEN_BUS_CLOCK 0x04
-
-#define KS8695_FLASH_START 0x02800000
-#define KS8695_FLASH_SIZE 0x00400000
-
-/*i/o control registers offset difinitions*/
-#define KS8695_IO_CTRL0 0x4000
-#define KS8695_IO_CTRL1 0x4004
-#define KS8695_IO_CTRL2 0x4008
-#define KS8695_IO_CTRL3 0x400C
-
-/*memory control registers offset difinitions*/
-#define KS8695_MEM_CTRL0 0x4010
-#define KS8695_MEM_CTRL1 0x4014
-#define KS8695_MEM_CTRL2 0x4018
-#define KS8695_MEM_CTRL3 0x401C
-#define KS8695_MEM_GENERAL 0x4020
-#define KS8695_SDRAM_CTRL0 0x4030
-#define KS8695_SDRAM_CTRL1 0x4034
-#define KS8695_SDRAM_GENERAL 0x4038
-#define KS8695_SDRAM_BUFFER 0x403C
-#define KS8695_SDRAM_REFRESH 0x4040
-
-/*WAN control registers offset difinitions*/
-#define KS8695_WAN_DMA_TX 0x6000
-#define KS8695_WAN_DMA_RX 0x6004
-#define KS8695_WAN_DMA_TX_START 0x6008
-#define KS8695_WAN_DMA_RX_START 0x600C
-#define KS8695_WAN_TX_LIST 0x6010
-#define KS8695_WAN_RX_LIST 0x6014
-#define KS8695_WAN_MAC_LOW 0x6018
-#define KS8695_WAN_MAC_HIGH 0x601C
-#define KS8695_WAN_MAC_ELOW 0x6080
-#define KS8695_WAN_MAC_EHIGH 0x6084
-
-/*LAN control registers offset difinitions*/
-#define KS8695_LAN_DMA_TX 0x8000
-#define KS8695_LAN_DMA_RX 0x8004
-#define KS8695_LAN_DMA_TX_START 0x8008
-#define KS8695_LAN_DMA_RX_START 0x800C
-#define KS8695_LAN_TX_LIST 0x8010
-#define KS8695_LAN_RX_LIST 0x8014
-#define KS8695_LAN_MAC_LOW 0x8018
-#define KS8695_LAN_MAC_HIGH 0x801C
-#define KS8695_LAN_MAC_ELOW 0X8080
-#define KS8695_LAN_MAC_EHIGH 0X8084
-
-/*HPNA control registers offset difinitions*/
-#define KS8695_HPNA_DMA_TX 0xA000
-#define KS8695_HPNA_DMA_RX 0xA004
-#define KS8695_HPNA_DMA_TX_START 0xA008
-#define KS8695_HPNA_DMA_RX_START 0xA00C
-#define KS8695_HPNA_TX_LIST 0xA010
-#define KS8695_HPNA_RX_LIST 0xA014
-#define KS8695_HPNA_MAC_LOW 0xA018
-#define KS8695_HPNA_MAC_HIGH 0xA01C
-#define KS8695_HPNA_MAC_ELOW 0xA080
-#define KS8695_HPNA_MAC_EHIGH 0xA084
-
-/*UART control registers offset difinitions*/
-#define KS8695_UART_RX_BUFFER 0xE000
-#define KS8695_UART_TX_HOLDING 0xE004
-
-#define KS8695_UART_FIFO_CTRL 0xE008
-#define KS8695_UART_FIFO_TRIG01 0x00
-#define KS8695_UART_FIFO_TRIG04 0x80
-#define KS8695_UART_FIFO_TXRST 0x03
-#define KS8695_UART_FIFO_RXRST 0x02
-#define KS8695_UART_FIFO_FEN 0x01
-
-#define KS8695_UART_LINE_CTRL 0xE00C
-#define KS8695_UART_LINEC_BRK 0x40
-#define KS8695_UART_LINEC_EPS 0x10
-#define KS8695_UART_LINEC_PEN 0x08
-#define KS8695_UART_LINEC_STP2 0x04
-#define KS8695_UART_LINEC_WLEN8 0x03
-#define KS8695_UART_LINEC_WLEN7 0x02
-#define KS8695_UART_LINEC_WLEN6 0x01
-#define KS8695_UART_LINEC_WLEN5 0x00
-
-#define KS8695_UART_MODEM_CTRL 0xE010
-#define KS8695_UART_MODEMC_RTS 0x02
-#define KS8695_UART_MODEMC_DTR 0x01
-
-#define KS8695_UART_LINE_STATUS 0xE014
-#define KS8695_UART_LINES_TXFE 0x20
-#define KS8695_UART_LINES_BE 0x10
-#define KS8695_UART_LINES_FE 0x08
-#define KS8695_UART_LINES_PE 0x04
-#define KS8695_UART_LINES_OE 0x02
-#define KS8695_UART_LINES_RXFE 0x01
-#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
-
-#define KS8695_UART_MODEM_STATUS 0xE018
-#define KS8695_UART_MODEM_DCD 0x80
-#define KS8695_UART_MODEM_DSR 0x20
-#define KS8695_UART_MODEM_CTS 0x10
-#define KS8695_UART_MODEM_DDCD 0x08
-#define KS8695_UART_MODEM_DDSR 0x02
-#define KS8695_UART_MODEM_DCTS 0x01
-#define UART8695_MODEM_ANY 0xFF
-
-#define KS8695_UART_DIVISOR 0xE01C
-#define KS8695_UART_STATUS 0xE020
-
-/*Interrupt controlller registers offset difinitions*/
-#define KS8695_INT_CONTL 0xE200
-#define KS8695_INT_ENABLE 0xE204
-#define KS8695_INT_ENABLE_MODEM 0x0800
-#define KS8695_INT_ENABLE_ERR 0x0400
-#define KS8695_INT_ENABLE_RX 0x0200
-#define KS8695_INT_ENABLE_TX 0x0100
-
-#define KS8695_INT_STATUS 0xE208
-#define KS8695_INT_WAN_PRIORITY 0xE20C
-#define KS8695_INT_HPNA_PRIORITY 0xE210
-#define KS8695_INT_LAN_PRIORITY 0xE214
-#define KS8695_INT_TIMER_PRIORITY 0xE218
-#define KS8695_INT_UART_PRIORITY 0xE21C
-#define KS8695_INT_EXT_PRIORITY 0xE220
-#define KS8695_INT_CHAN_PRIORITY 0xE224
-#define KS8695_INT_BUSERROR_PRO 0xE228
-#define KS8695_INT_MASK_STATUS 0xE22C
-#define KS8695_FIQ_PEND_PRIORITY 0xE230
-#define KS8695_IRQ_PEND_PRIORITY 0xE234
-
-/*timer registers offset difinitions*/
-#define KS8695_TIMER_CTRL 0xE400
-#define KS8695_TIMER1 0xE404
-#define KS8695_TIMER0 0xE408
-#define KS8695_TIMER1_PCOUNT 0xE40C
-#define KS8695_TIMER0_PCOUNT 0xE410
-
-/*GPIO registers offset difinitions*/
-#define KS8695_GPIO_MODE 0xE600
-#define KS8695_GPIO_CTRL 0xE604
-#define KS8695_GPIO_DATA 0xE608
-
-/*SWITCH registers offset difinitions*/
-#define KS8695_SWITCH_CTRL0 0xE800
-#define KS8695_SWITCH_CTRL1 0xE804
-#define KS8695_SWITCH_PORT1 0xE808
-#define KS8695_SWITCH_PORT2 0xE80C
-#define KS8695_SWITCH_PORT3 0xE810
-#define KS8695_SWITCH_PORT4 0xE814
-#define KS8695_SWITCH_PORT5 0xE818
-#define KS8695_SWITCH_AUTO0 0xE81C
-#define KS8695_SWITCH_AUTO1 0xE820
-#define KS8695_SWITCH_LUE_CTRL 0xE824
-#define KS8695_SWITCH_LUE_HIGH 0xE828
-#define KS8695_SWITCH_LUE_LOW 0xE82C
-#define KS8695_SWITCH_ADVANCED 0xE830
-
-#define KS8695_SWITCH_LPPM12 0xE874
-#define KS8695_SWITCH_LPPM34 0xE878
-
-/*host communication registers difinitions*/
-#define KS8695_DSCP_HIGH 0xE834
-#define KS8695_DSCP_LOW 0xE838
-#define KS8695_SWITCH_MAC_HIGH 0xE83C
-#define KS8695_SWITCH_MAC_LOW 0xE840
-
-/*miscellaneours registers difinitions*/
-#define KS8695_MANAGE_COUNTER 0xE844
-#define KS8695_MANAGE_DATA 0xE848
-#define KS8695_LAN12_POWERMAGR 0xE84C
-#define KS8695_LAN34_POWERMAGR 0xE850
-
-#define KS8695_DEVICE_ID 0xEA00
-#define KS8695_REVISION_ID 0xEA04
-
-#define KS8695_MISC_CONTROL 0xEA08
-#define KS8695_WAN_CONTROL 0xEA0C
-#define KS8695_WAN_POWERMAGR 0xEA10
-#define KS8695_WAN_PHY_CONTROL 0xEA14
-#define KS8695_WAN_PHY_STATUS 0xEA18
-
-/* bus clock definitions*/
-#define KS8695_BUS_CLOCK_125MHZ 0x0
-#define KS8695_BUS_CLOCK_100MHZ 0x1
-#define KS8695_BUS_CLOCK_62MHZ 0x2
-#define KS8695_BUS_CLOCK_50MHZ 0x3
-#define KS8695_BUS_CLOCK_41MHZ 0x4
-#define KS8695_BUS_CLOCK_33MHZ 0x5
-#define KS8695_BUS_CLOCK_31MHZ 0x6
-#define KS8695_BUS_CLOCK_25MHZ 0x7
-
-/* -------------------------------------------------------------------------------
- * definations for IRQ
- * -------------------------------------------------------------------------------*/
-
-#define KS8695_INT_EXT_INT0 2
-#define KS8695_INT_EXT_INT1 3
-#define KS8695_INT_EXT_INT2 4
-#define KS8695_INT_EXT_INT3 5
-#define KS8695_INT_TIMERINT0 6
-#define KS8695_INT_TIMERINT1 7
-#define KS8695_INT_UART_TX 8
-#define KS8695_INT_UART_RX 9
-#define KS8695_INT_UART_LINE_ERR 10
-#define KS8695_INT_UART_MODEMS 11
-#define KS8695_INT_LAN_STOP_RX 12
-#define KS8695_INT_LAN_STOP_TX 13
-#define KS8695_INT_LAN_BUF_RX_STATUS 14
-#define KS8695_INT_LAN_BUF_TX_STATUS 15
-#define KS8695_INT_LAN_RX_STATUS 16
-#define KS8695_INT_LAN_TX_STATUS 17
-#define KS8695_INT_HPAN_STOP_RX 18
-#define KS8695_INT_HPNA_STOP_TX 19
-#define KS8695_INT_HPNA_BUF_RX_STATUS 20
-#define KS8695_INT_HPNA_BUF_TX_STATUS 21
-#define KS8695_INT_HPNA_RX_STATUS 22
-#define KS8695_INT_HPNA_TX_STATUS 23
-#define KS8695_INT_BUS_ERROR 24
-#define KS8695_INT_WAN_STOP_RX 25
-#define KS8695_INT_WAN_STOP_TX 26
-#define KS8695_INT_WAN_BUF_RX_STATUS 27
-#define KS8695_INT_WAN_BUF_TX_STATUS 28
-#define KS8695_INT_WAN_RX_STATUS 29
-#define KS8695_INT_WAN_TX_STATUS 30
-
-#define KS8695_INT_UART KS8695_INT_UART_TX
-
-/* -------------------------------------------------------------------------------
- * Interrupt bit positions
- *
- * -------------------------------------------------------------------------------
- */
-
-#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 )
-#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 )
-#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 )
-#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 )
-#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 )
-#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 )
-#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX )
-#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX )
-#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR )
-#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS )
-#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX )
-#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX )
-#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX )
-#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX )
-#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
-#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
-#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS )
-#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS )
-#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR )
-#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX )
-#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX )
-#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS )
-#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS )
-
-#define KS8695_SC_VALID_INT 0xFFFFFFFF
-#define MAXIRQNUM 31
-
-/*
- * Timer definitions
- *
- * Use timer 1 & 2
- * (both run at 25MHz).
- *
- */
-#define TICKS_PER_uSEC 25
-#define mSEC_1 1000
-#define mSEC_10 (mSEC_1 * 10)
-
-#endif
-
-/* END */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 791551841c..3b6a1696d8 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -36,6 +36,7 @@
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
@@ -61,6 +62,20 @@
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
+#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
+#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
+#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
+/*
+ * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
+ * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
+ */
+#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \
+ CONFIG_SYS_PCIE1_VIRT_ADDR)
+#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
+ CONFIG_SYS_PCIE2_VIRT_ADDR)
+
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index f70d568d46..3a64afce46 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -37,6 +37,43 @@
#define DCFG_DCSR_PORCR1 0
+/*
+ * Define default values for some CCSR macros to make header files cleaner
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
@@ -133,8 +170,7 @@ struct ccsr_scfg {
u32 pex1rdmmsgrqsr;
u32 pex2rdmmsgrqsr;
u32 spimsiclrcr;
- u32 pex1mscportsr;
- u32 pex2mscportsr;
+ u32 pexmscportsr[2];
u32 pex2pmwrcr;
u32 resv5[24];
u32 mac1_streamid;
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index abd70fc706..fa571b3a38 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -7,11 +7,68 @@
#ifndef __FSL_LS102XA_STREAM_ID_H_
#define __FSL_LS102XA_STREAM_ID_H_
+#include <fsl_sec.h>
+
+#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
+ { .compat = name, \
+ .id = { idA }, .num_ids = 1, \
+ .reg_offset = off + CONFIG_SYS_IMMR, \
+ .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ }
+
+#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
+ { .compat = name, \
+ .id = { idA, idB }, .num_ids = 2, \
+ .reg_offset = off + CONFIG_SYS_IMMR, \
+ .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ }
+
+/*
+ * handle both old and new versioned SEC properties:
+ * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
+ */
+#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
+ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
+ offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
+ SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
+ offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
+
+/* This is a bit evil since we treat rtic param as both a string & hex value */
+#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
+ SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
+ liodnA, \
+ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
+ liodnA, \
+ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+
+#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
+ SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
+ offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, 0)
+
+struct liodn_id_table {
+ const char *compat;
+ u32 id[2];
+ u8 num_ids;
+ phys_addr_t compat_offset;
+ unsigned long reg_offset;
+};
+
struct smmu_stream_id {
uint16_t offset;
uint16_t stream_id;
char dev_name[32];
};
+void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
#endif
diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h
deleted file mode 100644
index 42a52bc36c..0000000000
--- a/arch/arm/include/asm/arch-mb86r0x/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * Author : Carsten Schneider, mycable GmbH
- * <cs@mycable.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <linux/sizes.h>
-#include <asm/arch/mb86r0x.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
deleted file mode 100644
index 7fec9715b1..0000000000
--- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * mb86r0x definitions
- *
- * Author : Carsten Schneider, mycable GmbH
- * <cs@mycable.de>
- *
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef MB86R0X_H
-#define MB86R0X_H
-
-#ifndef __ASSEMBLY__
-
-/* GPIO registers */
-struct mb86r0x_gpio {
- uint32_t gpdr0;
- uint32_t gpdr1;
- uint32_t gpdr2;
- uint32_t res;
- uint32_t gpddr0;
- uint32_t gpddr1;
- uint32_t gpddr2;
-};
-
-/* PWM registers */
-struct mb86r0x_pwm {
- uint32_t bcr;
- uint32_t tpr;
- uint32_t pr;
- uint32_t dr;
- uint32_t cr;
- uint32_t sr;
- uint32_t ccr;
- uint32_t ir;
-};
-
-/* The mb86r0x chip control (CCNT) register set. */
-struct mb86r0x_ccnt {
- uint32_t ccid;
- uint32_t csrst;
- uint32_t pad0[2];
- uint32_t cist;
- uint32_t cistm;
- uint32_t cgpio_ist;
- uint32_t cgpio_istm;
- uint32_t cgpio_ip;
- uint32_t cgpio_im;
- uint32_t caxi_bw;
- uint32_t caxi_ps;
- uint32_t cmux_md;
- uint32_t cex_pin_st;
- uint32_t cmlb;
- uint32_t pad1[1];
- uint32_t cusb;
- uint32_t pad2[41];
- uint32_t cbsc;
- uint32_t cdcrc;
- uint32_t cmsr0;
- uint32_t cmsr1;
- uint32_t pad3[2];
-};
-
-/* The mb86r0x clock reset generator */
-struct mb86r0x_crg {
- uint32_t crpr;
- uint32_t pad0;
- uint32_t crwr;
- uint32_t crsr;
- uint32_t crda;
- uint32_t crdb;
- uint32_t crha;
- uint32_t crpa;
- uint32_t crpb;
- uint32_t crhb;
- uint32_t cram;
-};
-
-/* The mb86r0x timer */
-struct mb86r0x_timer {
- uint32_t load;
- uint32_t value;
- uint32_t control;
- uint32_t intclr;
- uint32_t ris;
- uint32_t mis;
- uint32_t bgload;
-};
-
-/* mb86r0x gdc display controller */
-struct mb86r0x_gdc_dsp {
- /* Display settings */
- uint32_t dcm0;
- uint16_t pad00;
- uint16_t htp;
- uint16_t hdp;
- uint16_t hdb;
- uint16_t hsp;
- uint8_t hsw;
- uint8_t vsw;
- uint16_t pad01;
- uint16_t vtr;
- uint16_t vsp;
- uint16_t vdp;
- uint16_t wx;
- uint16_t wy;
- uint16_t ww;
- uint16_t wh;
-
- /* Layer 0 */
- uint32_t l0m;
- uint32_t l0oa;
- uint32_t l0da;
- uint16_t l0dx;
- uint16_t l0dy;
-
- /* Layer 1 */
- uint32_t l1m;
- uint32_t cbda0;
- uint32_t cbda1;
- uint32_t pad02;
-
- /* Layer 2 */
- uint32_t l2m;
- uint32_t l2oa0;
- uint32_t l2da0;
- uint32_t l2oa1;
- uint32_t l2da1;
- uint16_t l2dx;
- uint16_t l2dy;
-
- /* Layer 3 */
- uint32_t l3m;
- uint32_t l3oa0;
- uint32_t l3da0;
- uint32_t l3oa1;
- uint32_t l3da1;
- uint16_t l3dx;
- uint16_t l3dy;
-
- /* Layer 4 */
- uint32_t l4m;
- uint32_t l4oa0;
- uint32_t l4da0;
- uint32_t l4oa1;
- uint32_t l4da1;
- uint16_t l4dx;
- uint16_t l4dy;
-
- /* Layer 5 */
- uint32_t l5m;
- uint32_t l5oa0;
- uint32_t l5da0;
- uint32_t l5oa1;
- uint32_t l5da1;
- uint16_t l5dx;
- uint16_t l5dy;
-
- /* Cursor */
- uint16_t cutc;
- uint8_t cpm;
- uint8_t csize;
- uint32_t cuoa0;
- uint16_t cux0;
- uint16_t cuy0;
- uint32_t cuoa1;
- uint16_t cux1;
- uint16_t cuy1;
-
- /* Layer blending */
- uint32_t l0bld;
- uint32_t pad03;
- uint32_t l0tc;
- uint16_t l3tc;
- uint16_t l2tc;
- uint32_t pad04[15];
-
- /* Display settings */
- uint32_t dcm1;
- uint32_t dcm2;
- uint32_t dcm3;
- uint32_t pad05;
-
- /* Layer 0 extended */
- uint32_t l0em;
- uint16_t l0wx;
- uint16_t l0wy;
- uint16_t l0ww;
- uint16_t l0wh;
- uint32_t pad06;
-
- /* Layer 1 extended */
- uint32_t l1em;
- uint16_t l1wx;
- uint16_t l1wy;
- uint16_t l1ww;
- uint16_t l1wh;
- uint32_t pad07;
-
- /* Layer 2 extended */
- uint32_t l2em;
- uint16_t l2wx;
- uint16_t l2wy;
- uint16_t l2ww;
- uint16_t l2wh;
- uint32_t pad08;
-
- /* Layer 3 extended */
- uint32_t l3em;
- uint16_t l3wx;
- uint16_t l3wy;
- uint16_t l3ww;
- uint16_t l3wh;
- uint32_t pad09;
-
- /* Layer 4 extended */
- uint32_t l4em;
- uint16_t l4wx;
- uint16_t l4wy;
- uint16_t l4ww;
- uint16_t l4wh;
- uint32_t pad10;
-
- /* Layer 5 extended */
- uint32_t l5em;
- uint16_t l5wx;
- uint16_t l5wy;
- uint16_t l5ww;
- uint16_t l5wh;
- uint32_t pad11;
-
- /* Multi screen control */
- uint32_t msc;
- uint32_t pad12[3];
- uint32_t dls;
- uint32_t dbgc;
-
- /* Layer blending */
- uint32_t l1bld;
- uint32_t l2bld;
- uint32_t l3bld;
- uint32_t l4bld;
- uint32_t l5bld;
- uint32_t pad13;
-
- /* Extended transparency control */
- uint32_t l0etc;
- uint32_t l1etc;
- uint32_t l2etc;
- uint32_t l3etc;
- uint32_t l4etc;
- uint32_t l5etc;
- uint32_t pad14[10];
-
- /* YUV coefficients */
- uint32_t l1ycr0;
- uint32_t l1ycr1;
- uint32_t l1ycg0;
- uint32_t l1ycg1;
- uint32_t l1ycb0;
- uint32_t l1ycb1;
- uint32_t pad15[130];
-
- /* Layer palletes */
- uint32_t l0pal[256];
- uint32_t l1pal[256];
- uint32_t pad16[256];
- uint32_t l2pal[256];
- uint32_t l3pal[256];
- uint32_t pad17[256];
-
- /* PWM settings */
- uint32_t vpwmm;
- uint16_t vpwms;
- uint16_t vpwme;
- uint32_t vpwmc;
- uint32_t pad18[253];
-};
-
-/* mb86r0x gdc capture controller */
-struct mb86r0x_gdc_cap {
- uint32_t vcm;
- uint32_t csc;
- uint32_t vcs;
- uint32_t pad01;
-
- uint32_t cbm;
- uint32_t cboa;
- uint32_t cbla;
- uint16_t cihstr;
- uint16_t civstr;
- uint16_t cihend;
- uint16_t civend;
- uint32_t pad02;
-
- uint32_t chp;
- uint32_t cvp;
- uint32_t pad03[4];
-
- uint32_t clpf;
- uint32_t pad04;
- uint32_t cmss;
- uint32_t cmds;
- uint32_t pad05[12];
-
- uint32_t rgbhc;
- uint32_t rgbhen;
- uint32_t rgbven;
- uint32_t pad06;
- uint32_t rgbs;
- uint32_t pad07[11];
-
- uint32_t rgbcmy;
- uint32_t rgbcmcb;
- uint32_t rgbcmcr;
- uint32_t rgbcmb;
- uint32_t pad08[12 + 1984];
-};
-
-/* mb86r0x gdc draw */
-struct mb86r0x_gdc_draw {
- uint32_t ys;
- uint32_t xs;
- uint32_t dxdy;
- uint32_t xus;
- uint32_t dxudy;
- uint32_t xls;
- uint32_t dxldy;
- uint32_t usn;
- uint32_t lsn;
- uint32_t pad01[7];
- uint32_t rs;
- uint32_t drdx;
- uint32_t drdy;
- uint32_t gs;
- uint32_t dgdx;
- uint32_t dgdy;
- uint32_t bs;
- uint32_t dbdx;
- uint32_t dbdy;
- uint32_t pad02[7];
- uint32_t zs;
- uint32_t dzdx;
- uint32_t dzdy;
- uint32_t pad03[13];
- uint32_t ss;
- uint32_t dsdx;
- uint32_t dsdy;
- uint32_t ts;
- uint32_t dtdx;
- uint32_t dtdy;
- uint32_t qs;
- uint32_t dqdx;
- uint32_t dqdy;
- uint32_t pad04[23];
- uint32_t lpn;
- uint32_t lxs;
- uint32_t lxde;
- uint32_t lys;
- uint32_t lyde;
- uint32_t lzs;
- uint32_t lzde;
- uint32_t pad05[13];
- uint32_t pxdc;
- uint32_t pydc;
- uint32_t pzdc;
- uint32_t pad06[25];
- uint32_t rxs;
- uint32_t rys;
- uint32_t rsizex;
- uint32_t rsizey;
- uint32_t pad07[12];
- uint32_t saddr;
- uint32_t sstride;
- uint32_t srx;
- uint32_t sry;
- uint32_t daddr;
- uint32_t dstride;
- uint32_t drx;
- uint32_t dry;
- uint32_t brsizex;
- uint32_t brsizey;
- uint32_t tcolor;
- uint32_t pad08[93];
- uint32_t blpo;
- uint32_t pad09[7];
- uint32_t ctr;
- uint32_t ifsr;
- uint32_t ifcnt;
- uint32_t sst;
- uint32_t ds;
- uint32_t pst;
- uint32_t est;
- uint32_t pad10;
- uint32_t mdr0;
- uint32_t mdr1;
- uint32_t mdr2;
- uint32_t mdr3;
- uint32_t mdr4;
- uint32_t pad14[2];
- uint32_t mdr7;
- uint32_t fbr;
- uint32_t xres;
- uint32_t zbr;
- uint32_t tbr;
- uint32_t pfbr;
- uint32_t cxmin;
- uint32_t cxmax;
- uint32_t cymin;
- uint32_t cymax;
- uint32_t txs;
- uint32_t tis;
- uint32_t toa;
- uint32_t sho;
- uint32_t abr;
- uint32_t pad15[2];
- uint32_t fc;
- uint32_t bc;
- uint32_t alf;
- uint32_t blp;
- uint32_t pad16;
- uint32_t tbc;
- uint32_t pad11[42];
- uint32_t lx0dc;
- uint32_t ly0dc;
- uint32_t lx1dc;
- uint32_t ly1dc;
- uint32_t pad12[12];
- uint32_t x0dc;
- uint32_t y0dc;
- uint32_t x1dc;
- uint32_t y1dc;
- uint32_t x2dc;
- uint32_t y2dc;
- uint32_t pad13[666];
-};
-
-/* mb86r0x gdc geometry engine */
-struct mb86r0x_gdc_geom {
- uint32_t gctr;
- uint32_t pad00[15];
- uint32_t gmdr0;
- uint32_t gmdr1;
- uint32_t gmdr2;
- uint32_t pad01[237];
- uint32_t dfifog;
- uint32_t pad02[767];
-};
-
-/* mb86r0x gdc */
-struct mb86r0x_gdc {
- uint32_t pad00[2];
- uint32_t lts;
- uint32_t pad01;
- uint32_t lsta;
- uint32_t pad02[3];
- uint32_t ist;
- uint32_t imask;
- uint32_t pad03[6];
- uint32_t lsa;
- uint32_t lco;
- uint32_t lreq;
-
- uint32_t pad04[16*1024 - 19];
- struct mb86r0x_gdc_dsp dsp0;
- struct mb86r0x_gdc_dsp dsp1;
- uint32_t pad05[4*1024 - 2];
- uint32_t vccc;
- uint32_t vcsr;
- struct mb86r0x_gdc_cap cap0;
- struct mb86r0x_gdc_cap cap1;
- uint32_t pad06[4*1024];
- uint32_t texture_base[16*1024];
- struct mb86r0x_gdc_draw draw;
- uint32_t pad07[7*1024];
- struct mb86r0x_gdc_geom geom;
- uint32_t pad08[7*1024];
-};
-
-/* mb86r0x ddr2c */
-struct mb86r0x_ddr2c {
- uint16_t dric;
- uint16_t dric1;
- uint16_t dric2;
- uint16_t drca;
- uint16_t drcm;
- uint16_t drcst1;
- uint16_t drcst2;
- uint16_t drcr;
- uint16_t pad00[8];
- uint16_t drcf;
- uint16_t pad01[7];
- uint16_t drasr;
- uint16_t pad02[15];
- uint16_t drims;
- uint16_t pad03[7];
- uint16_t dros;
- uint16_t pad04;
- uint16_t dribsodt1;
- uint16_t dribsocd;
- uint16_t dribsocd2;
- uint16_t pad05[3];
- uint16_t droaba;
- uint16_t pad06[9];
- uint16_t drobs;
- uint16_t pad07[5];
- uint16_t drimr1;
- uint16_t drimr2;
- uint16_t drimr3;
- uint16_t drimr4;
- uint16_t droisr1;
- uint16_t droisr2;
-};
-
-/* mb86r0x memc */
-struct mb86r0x_memc {
- uint32_t mcfmode[8];
- uint32_t mcftim[8];
- uint32_t mcfarea[8];
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Physical Address Defines
- */
-#define MB86R0x_DDR2_BASE 0xf3000000
-#define MB86R0x_GDC_BASE 0xf1fc0000
-#define MB86R0x_CCNT_BASE 0xfff42000
-#define MB86R0x_CAN0_BASE 0xfff54000
-#define MB86R0x_CAN1_BASE 0xfff55000
-#define MB86R0x_I2C0_BASE 0xfff56000
-#define MB86R0x_I2C1_BASE 0xfff57000
-#define MB86R0x_EHCI_BASE 0xfff80000
-#define MB86R0x_OHCI_BASE 0xfff81000
-#define MB86R0x_IRC1_BASE 0xfffb0000
-#define MB86R0x_MEMC_BASE 0xfffc0000
-#define MB86R0x_TIMER_BASE 0xfffe0000
-#define MB86R0x_UART0_BASE 0xfffe1000
-#define MB86R0x_UART1_BASE 0xfffe2000
-#define MB86R0x_IRCE_BASE 0xfffe4000
-#define MB86R0x_CRG_BASE 0xfffe7000
-#define MB86R0x_IRC0_BASE 0xfffe8000
-#define MB86R0x_GPIO_BASE 0xfffe9000
-#define MB86R0x_PWM0_BASE 0xfff41000
-#define MB86R0x_PWM1_BASE 0xfff41100
-
-#define MB86R0x_CRSR_SWRSTREQ (1 << 1)
-
-/*
- * Timer register bits
- */
-#define MB86R0x_TIMER_ENABLE (1 << 7)
-#define MB86R0x_TIMER_MODE_MSK (1 << 6)
-#define MB86R0x_TIMER_MODE_FR (0 << 6)
-#define MB86R0x_TIMER_MODE_PD (1 << 6)
-
-#define MB86R0x_TIMER_INT_EN (1 << 5)
-#define MB86R0x_TIMER_PRS_MSK (3 << 2)
-#define MB86R0x_TIMER_PRS_4S (1 << 2)
-#define MB86R0x_TIMER_PRS_8S (1 << 3)
-#define MB86R0x_TIMER_SIZE_32 (1 << 1)
-#define MB86R0x_TIMER_ONE_SHT (1 << 0)
-
-/*
- * Clock reset generator bits
- */
-#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8)
-#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0)
-/*
- * DDR2 controller bits
- */
-#define MB86R0x_DDR2_DRCI_DRINI (1 << 15)
-#define MB86R0x_DDR2_DRCI_CKEN (1 << 14)
-#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0)
-#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \
- MB86R0x_DDR2_DRCI_CKEN | \
- MB86R0x_DDR2_DRCI_DRCMD)
-#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \
- MB86R0x_DDR2_DRCI_CKEN)
-#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN
-#endif /* MB86R0X_H */
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
deleted file mode 100644
index 1eed7b1d56..0000000000
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PANTHEON_CONFIG_H
-#define _PANTHEON_CONFIG_H
-
-#include <asm/arch/pantheon.h>
-
-/* default Dcache Line length for pantheon */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
-#define MV_MFPR_BASE PANTHEON_MFPR_BASE
-#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE
-#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
- represents UART Unit Enable */
-/*
- * I2C definition
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MV 1
-#define CONFIG_MV_I2C_REG 0xd4011000
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 0
-#define CONFIG_SYS_I2C_SLAVE 0xfe
-#endif
-
-/*
- * MMC definition
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT 1
-#define CONFIG_MMC 1
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_SDHCI 1
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
-#define CONFIG_MMC_SDMA 1
-#define CONFIG_MV_SDHCI 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-#define CONFIG_SYS_MMC_NUM 2
-#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000}
-#endif
-
-#endif /* _PANTHEON_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
deleted file mode 100644
index 3ccdf8a359..0000000000
--- a/arch/arm/include/asm/arch-pantheon/cpu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PANTHEON_CPU_H
-#define _PANTHEON_CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Register Datasheet 9.1
- */
-struct panthmpmu_registers {
- u8 pad0[0x0024];
- u32 ccgr; /*0x0024*/
- u8 pad1[0x0200 - 0x024 - 4];
- u32 wdtpcr; /*0x0200*/
- u8 pad2[0x1020 - 0x200 - 4];
- u32 aprr; /*0x1020*/
- u32 acgr; /*0x1024*/
-};
-
-/*
- * Application Power Management (APMU) Registers
- * Refer Register Datasheet 9.2
- */
-struct panthapmu_registers {
- u8 pad0[0x0054];
- u32 sd1; /*0x0054*/
- u8 pad1[0x00e0 - 0x054 - 4];
- u32 sd3; /*0x00e0*/
-};
-
-/*
- * APB Clock Reset/Control Registers
- * Refer Register Datasheet 6.14
- */
-struct panthapb_registers {
- u32 uart0; /*0x000*/
- u32 uart1; /*0x004*/
- u32 gpio; /*0x008*/
- u8 pad0[0x02c - 0x08 - 4];
- u32 twsi; /*0x02c*/
- u8 pad1[0x034 - 0x2c - 4];
- u32 timers; /*0x034*/
-};
-
-/*
- * CPU Interface Registers
- * Refer Register Datasheet 4.3
- */
-struct panthcpu_registers {
- u32 chip_id; /* Chip Id Reg */
- u32 pad;
- u32 cpu_conf; /* CPU Conf Reg */
- u32 pad1;
- u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
- u32 pad2;
- u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
- u32 mcb_conf; /* MCB Conf Reg */
- u32 sys_boot_ctl; /* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 panth_sdram_base(int);
-u32 panth_sdram_size(int);
-int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
-
-#endif /* _PANTHEON_CPU_H */
diff --git a/arch/arm/include/asm/arch-pantheon/gpio.h b/arch/arm/include/asm/arch-pantheon/gpio.h
deleted file mode 100644
index e69de29bb2..0000000000
--- a/arch/arm/include/asm/arch-pantheon/gpio.h
+++ /dev/null
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h
deleted file mode 100644
index 7909d53d46..0000000000
--- a/arch/arm/include/asm/arch-pantheon/mfp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Based on arch/arm/include/asm/arch-armada100/mfp.h
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PANTHEON_MFP_H
-#define __PANTHEON_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART2 */
-#define MFP47_UART2_RXD (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP48_UART2_TXD (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* More macros can be defined here... */
-#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-
-#define MFP_PIN_MAX 117
-#endif
diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
deleted file mode 100644
index c3a71bfce4..0000000000
--- a/arch/arm/include/asm/arch-pantheon/pantheon.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PANTHEON_H
-#define _PANTHEON_H
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
-#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
-#define APBC_RST (1<<2) /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
-
-/* Common APMU register bit definitions */
-#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */
-#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/
-#define APMU_PERI_RST (1<<1) /* Peripheral Reset */
-#define APMU_AXI_RST (1<<0) /* AXI Reset */
-
-/* Register Base Addresses */
-#define PANTHEON_DRAM_BASE 0xB0000000
-#define PANTHEON_TIMER_BASE 0xD4014000
-#define PANTHEON_WD_TIMER_BASE 0xD4080000
-#define PANTHEON_APBC_BASE 0xD4015000
-#define PANTHEON_UART1_BASE 0xD4017000
-#define PANTHEON_UART2_BASE 0xD4018000
-#define PANTHEON_GPIO_BASE 0xD4019000
-#define PANTHEON_MFPR_BASE 0xD401E000
-#define PANTHEON_MPMU_BASE 0xD4050000
-#define PANTHEON_APMU_BASE 0xD4282800
-#define PANTHEON_CPU_BASE 0xD4282C00
-
-#endif /* _PANTHEON_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h
deleted file mode 100644
index dfc3b1bfa5..0000000000
--- a/arch/arm/include/asm/arch-tnetv107x/clock.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * TNETV107X: Clock APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0
-#define PSC_MDCTL_NEXT_SYNCRST 0x1
-#define PSC_MDCTL_NEXT_DISABLE 0x2
-#define PSC_MDCTL_NEXT_ENABLE 0x3
-
-#define CONFIG_SYS_INT_OSC_FREQ 24000000
-
-#ifndef __ASSEMBLY__
-
-/* PLL identifiers */
-enum pll_type_e {
- SYS_PLL,
- TDM_PLL,
- ETH_PLL
-};
-
-/* PLL configuration data */
-struct pll_init_data {
- int pll;
- int internal_osc;
- unsigned long pll_freq;
- unsigned long div_freq[10];
-};
-
-void init_plls(int num_pll, struct pll_init_data *config);
-int lpsc_status(unsigned int mod);
-void lpsc_control(int mod, unsigned long state, int lrstz);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-static inline void clk_enable(unsigned int mod)
-{
- lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
-}
-
-static inline void clk_disable(unsigned int mod)
-{
- lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
-}
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
deleted file mode 100644
index d458e0bdf0..0000000000
--- a/arch/arm/include/asm/arch-tnetv107x/hardware.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * TNETV107X: Hardware information
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/sizes.h>
-
-#define ASYNC_EMIF_NUM_CS 4
-#define ASYNC_EMIF_MODE_NOR 0
-#define ASYNC_EMIF_MODE_NAND 1
-#define ASYNC_EMIF_MODE_ONENAND 2
-#define ASYNC_EMIF_PRESERVE -1
-
-struct async_emif_config {
- unsigned mode;
- unsigned select_strobe;
- unsigned extend_wait;
- unsigned wr_setup;
- unsigned wr_strobe;
- unsigned wr_hold;
- unsigned rd_setup;
- unsigned rd_strobe;
- unsigned rd_hold;
- unsigned turn_around;
- enum {
- ASYNC_EMIF_8 = 0,
- ASYNC_EMIF_16 = 1,
- ASYNC_EMIF_32 = 2,
- } width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
-int wdt_start(unsigned long msecs);
-int wdt_stop(void);
-int wdt_kick(void);
-
-#endif
-
-/* Chip configuration unlock codes and registers */
-#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
-#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
-#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
-#define TNETV107X_KICK0_MAGIC 0x83e70b13
-#define TNETV107X_KICK1_MAGIC 0x95a4f1e0
-
-/* Module base addresses */
-#define TNETV107X_TPCC_BASE 0x01C00000
-#define TNETV107X_TPTC0_BASE 0x01C10000
-#define TNETV107X_TPTC1_BASE 0x01C10400
-#define TNETV107X_INTC_BASE 0x03000000
-#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000
-#define TNETV107X_INTD_BASE 0x08038000
-#define TNETV107X_INTD_IPC_BASE 0x08038000
-#define TNETV107X_INTD_FAST_BASE 0x08039000
-#define TNETV107X_INTD_ASYNC_BASE 0x0803A000
-#define TNETV107X_INTD_SLOW_BASE 0x0803B000
-#define TNETV107X_PKA_BASE 0x08040000
-#define TNETV107X_RNG_BASE 0x08044000
-#define TNETV107X_TIMER0_BASE 0x08086500
-#define TNETV107X_TIMER1_BASE 0x08086600
-#define TNETV107X_WDT0_ARM_BASE 0x08086700
-#define TNETV107X_WDT1_DSP_BASE 0x08086800
-#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000
-#define TNETV107X_GPIO_BASE 0x08088000
-#define TNETV107X_UART1_BASE 0x08088400
-#define TNETV107X_TOUCHSCREEN_BASE 0x08088500
-#define TNETV107X_SDIO0_BASE 0x08088700
-#define TNETV107X_SDIO1_BASE 0x08088800
-#define TNETV107X_MDIO_BASE 0x08088900
-#define TNETV107X_KEYPAD_BASE 0x08088A00
-#define TNETV107X_SSP_BASE 0x08088C00
-#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000
-#define TNETV107X_PSC_BASE 0x0808B000
-#define TNETV107X_TDM0_BASE 0x08100000
-#define TNETV107X_TDM1_BASE 0x08100100
-#define TNETV107X_MCDMA_BASE 0x08108000
-#define TNETV107X_UART0_DMA_BASE 0x08108200
-#define TNETV107X_USBSS_BASE 0x08120000
-#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000
-#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
-#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000
-#define TNETV107X_IMCOP_BASE 0x01CC0000
-#define TNETV107X_MBX_LITE_BASE 0x07000000
-#define TNETV107X_ETHSS_BASE 0x0803C000
-#define TNETV107X_CPSW_BASE 0x0803C000
-#define TNETV107X_SPF_BASE 0x0803C800
-#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000
-#define TNETV107X_VTP_CNTRL_0 0x0803D800
-#define TNETV107X_VTP_CNTRL_1 0x0803D900
-#define TNETV107X_UART2_DMA_BASE 0x08108400
-#define TNETV107X_INTERNAL_MEMORY 0x20000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
-#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000
-#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000
-
-/* LPSC module definitions */
-#define TNETV107X_LPSC_ARM 0
-#define TNETV107X_LPSC_GEM 1
-#define TNETV107X_LPSC_DDR2_PHY 2
-#define TNETV107X_LPSC_TPCC 3
-#define TNETV107X_LPSC_TPTC0 4
-#define TNETV107X_LPSC_TPTC1 5
-#define TNETV107X_LPSC_RAM 6
-#define TNETV107X_LPSC_MBX_LITE 7
-#define TNETV107X_LPSC_LCD 8
-#define TNETV107X_LPSC_ETHSS 9
-#define TNETV107X_LPSC_AEMIF 10
-#define TNETV107X_LPSC_CHIP_CFG 11
-#define TNETV107X_LPSC_TSC 12
-#define TNETV107X_LPSC_ROM 13
-#define TNETV107X_LPSC_UART2 14
-#define TNETV107X_LPSC_PKTSEC 15
-#define TNETV107X_LPSC_SECCTL 16
-#define TNETV107X_LPSC_KEYMGR 17
-#define TNETV107X_LPSC_KEYPAD 18
-#define TNETV107X_LPSC_GPIO 19
-#define TNETV107X_LPSC_MDIO 20
-#define TNETV107X_LPSC_SDIO0 21
-#define TNETV107X_LPSC_UART0 22
-#define TNETV107X_LPSC_UART1 23
-#define TNETV107X_LPSC_TIMER0 24
-#define TNETV107X_LPSC_TIMER1 25
-#define TNETV107X_LPSC_WDT_ARM 26
-#define TNETV107X_LPSC_WDT_DSP 27
-#define TNETV107X_LPSC_SSP 28
-#define TNETV107X_LPSC_TDM0 29
-#define TNETV107X_LPSC_VLYNQ 30
-#define TNETV107X_LPSC_MCDMA 31
-#define TNETV107X_LPSC_USB0 32
-#define TNETV107X_LPSC_TDM1 33
-#define TNETV107X_LPSC_DEBUGSS 34
-#define TNETV107X_LPSC_ETHSS_RGMII 35
-#define TNETV107X_LPSC_SYSTEM 36
-#define TNETV107X_LPSC_IMCOP 37
-#define TNETV107X_LPSC_SPARE 38
-#define TNETV107X_LPSC_SDIO1 39
-#define TNETV107X_LPSC_USB1 40
-#define TNETV107X_LPSC_USBSS 41
-#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
-#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
-#define TNETV107X_LPSC_MAX 44
-
-/* Interrupt controller */
-#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10)
-#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
-#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
-
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h
deleted file mode 100644
index 3f832c4147..0000000000
--- a/arch/arm/include/asm/arch-tnetv107x/mux.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * TNETV107X: Pinmux APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-struct pin_config {
- unsigned char reg_index;
- unsigned char mask_offset;
- unsigned char mode;
-};
-
-#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
- { reg, offset, mux_mode }
-
-int mux_select_pin(short index);
-int mux_select_pins(const short *pins);
-
-enum tnetv107x_pin_mux_index {
- TNETV107X_PIN_ASR_A00,
- TNETV107X_PIN_GPIO32,
- TNETV107X_PIN_ASR_A01,
- TNETV107X_PIN_GPIO33,
- TNETV107X_PIN_ASR_A02,
- TNETV107X_PIN_GPIO34,
- TNETV107X_PIN_ASR_A03,
- TNETV107X_PIN_GPIO35,
- TNETV107X_PIN_ASR_A04,
- TNETV107X_PIN_GPIO36,
- TNETV107X_PIN_ASR_A05,
- TNETV107X_PIN_GPIO37,
- TNETV107X_PIN_ASR_A06,
- TNETV107X_PIN_GPIO38,
- TNETV107X_PIN_ASR_A07,
- TNETV107X_PIN_GPIO39,
- TNETV107X_PIN_ASR_A08,
- TNETV107X_PIN_GPIO40,
- TNETV107X_PIN_ASR_A09,
- TNETV107X_PIN_GPIO41,
- TNETV107X_PIN_ASR_A10,
- TNETV107X_PIN_GPIO42,
- TNETV107X_PIN_ASR_A11,
- TNETV107X_PIN_BOOT_STRP_0,
- TNETV107X_PIN_ASR_A12,
- TNETV107X_PIN_BOOT_STRP_1,
- TNETV107X_PIN_ASR_A13,
- TNETV107X_PIN_GPIO43,
- TNETV107X_PIN_ASR_A14,
- TNETV107X_PIN_GPIO44,
- TNETV107X_PIN_ASR_A15,
- TNETV107X_PIN_GPIO45,
- TNETV107X_PIN_ASR_A16,
- TNETV107X_PIN_GPIO46,
- TNETV107X_PIN_ASR_A17,
- TNETV107X_PIN_GPIO47,
- TNETV107X_PIN_ASR_A18,
- TNETV107X_PIN_GPIO48,
- TNETV107X_PIN_SDIO1_DATA3_0,
- TNETV107X_PIN_ASR_A19,
- TNETV107X_PIN_GPIO49,
- TNETV107X_PIN_SDIO1_DATA2_0,
- TNETV107X_PIN_ASR_A20,
- TNETV107X_PIN_GPIO50,
- TNETV107X_PIN_SDIO1_DATA1_0,
- TNETV107X_PIN_ASR_A21,
- TNETV107X_PIN_GPIO51,
- TNETV107X_PIN_SDIO1_DATA0_0,
- TNETV107X_PIN_ASR_A22,
- TNETV107X_PIN_GPIO52,
- TNETV107X_PIN_SDIO1_CMD_0,
- TNETV107X_PIN_ASR_A23,
- TNETV107X_PIN_GPIO53,
- TNETV107X_PIN_SDIO1_CLK_0,
- TNETV107X_PIN_ASR_BA_1,
- TNETV107X_PIN_GPIO54,
- TNETV107X_PIN_SYS_PLL_CLK,
- TNETV107X_PIN_ASR_CS0,
- TNETV107X_PIN_ASR_CS1,
- TNETV107X_PIN_ASR_CS2,
- TNETV107X_PIN_TDM_PLL_CLK,
- TNETV107X_PIN_ASR_CS3,
- TNETV107X_PIN_ETH_PHY_CLK,
- TNETV107X_PIN_ASR_D00,
- TNETV107X_PIN_GPIO55,
- TNETV107X_PIN_ASR_D01,
- TNETV107X_PIN_GPIO56,
- TNETV107X_PIN_ASR_D02,
- TNETV107X_PIN_GPIO57,
- TNETV107X_PIN_ASR_D03,
- TNETV107X_PIN_GPIO58,
- TNETV107X_PIN_ASR_D04,
- TNETV107X_PIN_GPIO59_0,
- TNETV107X_PIN_ASR_D05,
- TNETV107X_PIN_GPIO60_0,
- TNETV107X_PIN_ASR_D06,
- TNETV107X_PIN_GPIO61_0,
- TNETV107X_PIN_ASR_D07,
- TNETV107X_PIN_GPIO62_0,
- TNETV107X_PIN_ASR_D08,
- TNETV107X_PIN_GPIO63_0,
- TNETV107X_PIN_ASR_D09,
- TNETV107X_PIN_GPIO64_0,
- TNETV107X_PIN_ASR_D10,
- TNETV107X_PIN_SDIO1_DATA3_1,
- TNETV107X_PIN_ASR_D11,
- TNETV107X_PIN_SDIO1_DATA2_1,
- TNETV107X_PIN_ASR_D12,
- TNETV107X_PIN_SDIO1_DATA1_1,
- TNETV107X_PIN_ASR_D13,
- TNETV107X_PIN_SDIO1_DATA0_1,
- TNETV107X_PIN_ASR_D14,
- TNETV107X_PIN_SDIO1_CMD_1,
- TNETV107X_PIN_ASR_D15,
- TNETV107X_PIN_SDIO1_CLK_1,
- TNETV107X_PIN_ASR_OE,
- TNETV107X_PIN_BOOT_STRP_2,
- TNETV107X_PIN_ASR_RNW,
- TNETV107X_PIN_GPIO29_0,
- TNETV107X_PIN_ASR_WAIT,
- TNETV107X_PIN_GPIO30_0,
- TNETV107X_PIN_ASR_WE,
- TNETV107X_PIN_BOOT_STRP_3,
- TNETV107X_PIN_ASR_WE_DQM0,
- TNETV107X_PIN_GPIO31,
- TNETV107X_PIN_LCD_PD17_0,
- TNETV107X_PIN_ASR_WE_DQM1,
- TNETV107X_PIN_ASR_BA0_0,
- TNETV107X_PIN_VLYNQ_CLK,
- TNETV107X_PIN_GPIO14,
- TNETV107X_PIN_LCD_PD19_0,
- TNETV107X_PIN_VLYNQ_RXD0,
- TNETV107X_PIN_GPIO15,
- TNETV107X_PIN_LCD_PD20_0,
- TNETV107X_PIN_VLYNQ_RXD1,
- TNETV107X_PIN_GPIO16,
- TNETV107X_PIN_LCD_PD21_0,
- TNETV107X_PIN_VLYNQ_TXD0,
- TNETV107X_PIN_GPIO17,
- TNETV107X_PIN_LCD_PD22_0,
- TNETV107X_PIN_VLYNQ_TXD1,
- TNETV107X_PIN_GPIO18,
- TNETV107X_PIN_LCD_PD23_0,
- TNETV107X_PIN_SDIO0_CLK,
- TNETV107X_PIN_GPIO19,
- TNETV107X_PIN_SDIO0_CMD,
- TNETV107X_PIN_GPIO20,
- TNETV107X_PIN_SDIO0_DATA0,
- TNETV107X_PIN_GPIO21,
- TNETV107X_PIN_SDIO0_DATA1,
- TNETV107X_PIN_GPIO22,
- TNETV107X_PIN_SDIO0_DATA2,
- TNETV107X_PIN_GPIO23,
- TNETV107X_PIN_SDIO0_DATA3,
- TNETV107X_PIN_GPIO24,
- TNETV107X_PIN_EMU0,
- TNETV107X_PIN_EMU1,
- TNETV107X_PIN_RTCK,
- TNETV107X_PIN_TRST_N,
- TNETV107X_PIN_TCK,
- TNETV107X_PIN_TDI,
- TNETV107X_PIN_TDO,
- TNETV107X_PIN_TMS,
- TNETV107X_PIN_TDM1_CLK,
- TNETV107X_PIN_TDM1_RX,
- TNETV107X_PIN_TDM1_TX,
- TNETV107X_PIN_TDM1_FS,
- TNETV107X_PIN_KEYPAD_R0,
- TNETV107X_PIN_KEYPAD_R1,
- TNETV107X_PIN_KEYPAD_R2,
- TNETV107X_PIN_KEYPAD_R3,
- TNETV107X_PIN_KEYPAD_R4,
- TNETV107X_PIN_KEYPAD_R5,
- TNETV107X_PIN_KEYPAD_R6,
- TNETV107X_PIN_GPIO12,
- TNETV107X_PIN_KEYPAD_R7,
- TNETV107X_PIN_GPIO10,
- TNETV107X_PIN_KEYPAD_C0,
- TNETV107X_PIN_KEYPAD_C1,
- TNETV107X_PIN_KEYPAD_C2,
- TNETV107X_PIN_KEYPAD_C3,
- TNETV107X_PIN_KEYPAD_C4,
- TNETV107X_PIN_KEYPAD_C5,
- TNETV107X_PIN_KEYPAD_C6,
- TNETV107X_PIN_GPIO13,
- TNETV107X_PIN_TEST_CLK_IN,
- TNETV107X_PIN_KEYPAD_C7,
- TNETV107X_PIN_GPIO11,
- TNETV107X_PIN_SSP0_0,
- TNETV107X_PIN_SCC_DCLK,
- TNETV107X_PIN_LCD_PD20_1,
- TNETV107X_PIN_SSP0_1,
- TNETV107X_PIN_SCC_CS_N,
- TNETV107X_PIN_LCD_PD21_1,
- TNETV107X_PIN_SSP0_2,
- TNETV107X_PIN_SCC_D,
- TNETV107X_PIN_LCD_PD22_1,
- TNETV107X_PIN_SSP0_3,
- TNETV107X_PIN_SCC_RESETN,
- TNETV107X_PIN_LCD_PD23_1,
- TNETV107X_PIN_SSP1_0,
- TNETV107X_PIN_GPIO25,
- TNETV107X_PIN_UART2_CTS,
- TNETV107X_PIN_SSP1_1,
- TNETV107X_PIN_GPIO26,
- TNETV107X_PIN_UART2_RD,
- TNETV107X_PIN_SSP1_2,
- TNETV107X_PIN_GPIO27,
- TNETV107X_PIN_UART2_RTS,
- TNETV107X_PIN_SSP1_3,
- TNETV107X_PIN_GPIO28,
- TNETV107X_PIN_UART2_TD,
- TNETV107X_PIN_UART0_CTS,
- TNETV107X_PIN_UART0_RD,
- TNETV107X_PIN_UART0_RTS,
- TNETV107X_PIN_UART0_TD,
- TNETV107X_PIN_UART1_RD,
- TNETV107X_PIN_UART1_TD,
- TNETV107X_PIN_LCD_AC_NCS,
- TNETV107X_PIN_LCD_HSYNC_RNW,
- TNETV107X_PIN_LCD_VSYNC_A0,
- TNETV107X_PIN_LCD_MCLK,
- TNETV107X_PIN_LCD_PD16_0,
- TNETV107X_PIN_LCD_PCLK_E,
- TNETV107X_PIN_LCD_PD00,
- TNETV107X_PIN_LCD_PD01,
- TNETV107X_PIN_LCD_PD02,
- TNETV107X_PIN_LCD_PD03,
- TNETV107X_PIN_LCD_PD04,
- TNETV107X_PIN_LCD_PD05,
- TNETV107X_PIN_LCD_PD06,
- TNETV107X_PIN_LCD_PD07,
- TNETV107X_PIN_LCD_PD08,
- TNETV107X_PIN_GPIO59_1,
- TNETV107X_PIN_LCD_PD09,
- TNETV107X_PIN_GPIO60_1,
- TNETV107X_PIN_LCD_PD10,
- TNETV107X_PIN_ASR_BA0_1,
- TNETV107X_PIN_GPIO61_1,
- TNETV107X_PIN_LCD_PD11,
- TNETV107X_PIN_GPIO62_1,
- TNETV107X_PIN_LCD_PD12,
- TNETV107X_PIN_GPIO63_1,
- TNETV107X_PIN_LCD_PD13,
- TNETV107X_PIN_GPIO64_1,
- TNETV107X_PIN_LCD_PD14,
- TNETV107X_PIN_GPIO29_1,
- TNETV107X_PIN_LCD_PD15,
- TNETV107X_PIN_GPIO30_1,
- TNETV107X_PIN_EINT0,
- TNETV107X_PIN_GPIO08,
- TNETV107X_PIN_EINT1,
- TNETV107X_PIN_GPIO09,
- TNETV107X_PIN_GPIO00,
- TNETV107X_PIN_LCD_PD20_2,
- TNETV107X_PIN_TDM_CLK_IN_2,
- TNETV107X_PIN_GPIO01,
- TNETV107X_PIN_LCD_PD21_2,
- TNETV107X_PIN_24M_CLK_OUT_1,
- TNETV107X_PIN_GPIO02,
- TNETV107X_PIN_LCD_PD22_2,
- TNETV107X_PIN_GPIO03,
- TNETV107X_PIN_LCD_PD23_2,
- TNETV107X_PIN_GPIO04,
- TNETV107X_PIN_LCD_PD16_1,
- TNETV107X_PIN_USB0_RXERR,
- TNETV107X_PIN_GPIO05,
- TNETV107X_PIN_LCD_PD17_1,
- TNETV107X_PIN_TDM_CLK_IN_1,
- TNETV107X_PIN_GPIO06,
- TNETV107X_PIN_LCD_PD18,
- TNETV107X_PIN_24M_CLK_OUT_2,
- TNETV107X_PIN_GPIO07,
- TNETV107X_PIN_LCD_PD19_1,
- TNETV107X_PIN_USB1_RXERR,
- TNETV107X_PIN_ETH_PLL_CLK,
- TNETV107X_PIN_MDIO,
- TNETV107X_PIN_MDC,
- TNETV107X_PIN_AIC_MUTE_STAT_N,
- TNETV107X_PIN_TDM0_CLK,
- TNETV107X_PIN_AIC_HNS_EN_N,
- TNETV107X_PIN_TDM0_FS,
- TNETV107X_PIN_AIC_HDS_EN_STAT_N,
- TNETV107X_PIN_TDM0_TX,
- TNETV107X_PIN_AIC_HNF_EN_STAT_N,
- TNETV107X_PIN_TDM0_RX,
-};
-
-#endif
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 4b7b67b643..4b9cb52965 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -65,7 +65,8 @@
/*
* Section
*/
-#define PMD_SECT_S (3 << 8)
+#define PMD_SECT_OUTER_SHARE (2 << 8)
+#define PMD_SECT_INNER_SHARE (3 << 8)
#define PMD_SECT_AF (1 << 10)
#define PMD_SECT_NG (1 << 11)
#define PMD_SECT_PXN (UL(1) << 53)
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 438f128326..bb24f33d0d 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -48,6 +48,9 @@ struct arch_global_data {
#ifdef CONFIG_OMAP
struct omap_boot_parameters omap_boot_params;
#endif
+#ifdef CONFIG_FSL_LSCH3
+ unsigned long mem2_clk;
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 7820486df0..2a5bed2e46 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -70,6 +70,7 @@ void __asm_invalidate_dcache_all(void);
void __asm_flush_dcache_range(u64 start, u64 end);
void __asm_invalidate_tlb_all(void);
void __asm_invalidate_icache_all(void);
+int __asm_flush_l3_cache(void);
void armv8_switch_to_el2(void);
void armv8_switch_to_el1(void);
diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
index b0c26e5d68..e5bcaea1ae 100644
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c
@@ -15,9 +15,6 @@
#include <common.h>
#include <linux/kbuild.h>
-#if defined(CONFIG_MB86R0x)
-#include <asm/arch/mb86r0x.h>
-#endif
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
@@ -27,8 +24,6 @@ int main(void)
{
/*
* TODO : Check if each entry in this file is really necessary.
- * - struct mb86r0x_ddr2
- * - struct mb86r0x_memc
* - struct esdramc_regs
* - struct max_regs
* - struct aips_regs
@@ -40,47 +35,6 @@ int main(void)
* code. Is it better to define the macros directly in headers?
*/
-#if defined(CONFIG_MB86R0x)
- /* ddr2 controller */
- DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
- DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
- DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
- DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
- DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
- DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
- DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
- DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
- DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
- DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
- DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
- DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
- DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
- DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
- DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
-
- /* clock reset generator */
- DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
- DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
- DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
- DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
- DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
- DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
-
- /* chip control module */
- DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
-
- /* external bus interface */
- DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
- DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
- DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
- DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
- DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
- DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
- DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
- DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
- DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
-#endif
-
#if defined(CONFIG_MX25)
/* Clock Control Module */
DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 0c1298a31e..2d6b676154 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -191,7 +191,7 @@ __weak void setup_board_tags(struct tag **in_params) {}
static void do_nonsec_virt_switch(void)
{
smp_kick_all_cpus();
- flush_dcache_all(); /* flush cache before swtiching to EL2 */
+ dcache_disable(); /* flush cache before swtiching to EL2 */
armv8_switch_to_el2();
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
armv8_switch_to_el1();
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 613f04d8b0..68277217bf 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -21,10 +21,6 @@ config TARGET_CAM_ENC_4XX
bool "CAM ENC 4xx board"
select SUPPORT_SPL
-config TARGET_HAWKBOARD
- bool "Hawkboard"
- select SUPPORT_SPL
-
config TARGET_DAVINCI_DM355EVM
bool "DM355 EVM board"
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 3a8e2b19d6..8615248377 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -24,25 +24,25 @@ config SYS_MALLOC_F_LEN
default 0x1800
config USE_PRIVATE_LIBGCC
- default y if SPL_BUILD
+ default y
config DM
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
config DM_SPI
- default y if !SPL_BUILD
+ default y
config DM_SPI_FLASH
- default y if !SPL_BUILD
+ default y
config DM_I2C
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
source "arch/arm/mach-tegra/tegra20/Kconfig"
source "arch/arm/mach-tegra/tegra30/Kconfig"