diff options
Diffstat (limited to 'arch')
68 files changed, 4009 insertions, 61 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a623ef5743..1236315168 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -633,6 +633,12 @@ config ARCH_BCM63158 select OF_CONTROL imply CMD_DM +config ARCH_BCM68360 + bool "Broadcom BCM68360 family" + select DM + select OF_CONTROL + imply CMD_DM + config ARCH_BCM6858 bool "Broadcom BCM6858 family" select DM @@ -1009,6 +1015,24 @@ config ARCH_SUNXI imply SPL_SERIAL_SUPPORT imply USB_GADGET +config ARCH_U8500 + bool "ST-Ericsson U8500 Series" + select CPU_V7A + select DM + select DM_GPIO + select DM_MMC if MMC + select DM_SERIAL + select DM_USB if USB + select OF_CONTROL + select SYSRESET + select TIMER + imply ARM_PL180_MMCI + imply DM_RTC + imply NOMADIK_MTU_TIMER + imply PL01X_SERIAL + imply RTC_PL031 + imply SYSRESET_SYSCON + config ARCH_VERSAL bool "Support Xilinx Versal Platform" select ARM64 @@ -1117,7 +1141,6 @@ config TARGET_VEXPRESS64_JUNO config TARGET_LS2080A_EMU bool "Support ls2080a_emu" select ARCH_LS2080A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select FSL_DDR_SYNC_REFRESH @@ -1130,7 +1153,6 @@ config TARGET_LS2080A_EMU config TARGET_LS2080A_SIMU bool "Support ls2080a_simu" select ARCH_LS2080A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select BOARD_LATE_INIT @@ -1143,7 +1165,6 @@ config TARGET_LS2080A_SIMU config TARGET_LS1088AQDS bool "Support ls1088aqds" select ARCH_LS1088A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -1159,7 +1180,6 @@ config TARGET_LS1088AQDS config TARGET_LS2080AQDS bool "Support ls2080aqds" select ARCH_LS2080A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -1178,7 +1198,6 @@ config TARGET_LS2080AQDS config TARGET_LS2080ARDB bool "Support ls2080ardb" select ARCH_LS2080A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -1197,7 +1216,6 @@ config TARGET_LS2080ARDB config TARGET_LS2081ARDB bool "Support ls2081ardb" select ARCH_LS2080A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select BOARD_LATE_INIT @@ -1211,7 +1229,6 @@ config TARGET_LS2081ARDB config TARGET_LX2160ARDB bool "Support lx2160ardb" select ARCH_LX2160A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -1225,7 +1242,6 @@ config TARGET_LX2160ARDB config TARGET_LX2160AQDS bool "Support lx2160aqds" select ARCH_LX2160A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -1348,7 +1364,6 @@ config TARGET_LS1028AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT - select ARCH_MISC_INIT help Support for Freescale LS1028AQDS platform The LS1028A Development System (QDS) is a high-performance @@ -1370,7 +1385,6 @@ config TARGET_LS1028ARDB config TARGET_LS1088ARDB bool "Support ls1088ardb" select ARCH_LS1088A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -1779,6 +1793,8 @@ source "arch/arm/mach-sunxi/Kconfig" source "arch/arm/mach-tegra/Kconfig" +source "arch/arm/mach-u8500/Kconfig" + source "arch/arm/mach-uniphier/Kconfig" source "arch/arm/cpu/armv7/vf610/Kconfig" @@ -1808,6 +1824,7 @@ source "board/armltd/vexpress64/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcm963158/Kconfig" +source "board/broadcom/bcm968360bg/Kconfig" source "board/broadcom/bcm968580xref/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1e60a9fdd4..e25bb0e594 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -79,6 +79,7 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_STM32) += stm32 machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_TEGRA) += tegra +machine-$(CONFIG_ARCH_U8500) += u8500 machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 57d7fd9e55..937989b278 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -29,11 +29,9 @@ menu "LS102xA architecture" config LS1_DEEP_SLEEP bool "Deep sleep" - depends on ARCH_LS1021A config MAX_CPUS int "Maximum number of CPUs permitted for LS102xA" - depends on ARCH_LS1021A default 2 help Set this number to the maximum number of possible CPUs in the SoC. @@ -98,7 +96,6 @@ config SYS_HAS_SERDES config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" - depends on ARCH_LS1021A default 8 config SYS_FSL_ERRATUM_A008407 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ed478ddd48..e2b92f0eab 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -242,6 +242,7 @@ config FSL_LSCH2 select SYS_FSL_SEC_BE config FSL_LSCH3 + select ARCH_MISC_INIT bool config NXP_LSCH3_2 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index dce915a2ea..b443894453 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1632,3 +1632,17 @@ __weak int dram_init(void) return 0; } + +#ifdef CONFIG_ARCH_MISC_INIT +__weak int serdes_misc_init(void) +{ + return 0; +} + +int arch_misc_init(void) +{ + serdes_misc_init(); + + return 0; +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 1a747a9e3d..d143864af1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -600,3 +600,62 @@ void fsl_serdes_init(void) serdes3_prtcl_map); #endif } + +int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + char scfg[16], snum[16]; + int cfgr = 0; + u32 cfg; + + cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask; + cfg >>= sd_prctl_shift; + cfg = serdes_get_number(sd, cfg); + +#if defined(SRDS_BITS_PER_LANE) + /* + * reverse lanes, lane 0 should be printed first so it must be moved to + * high order bits. + * For example bb58 should read 85bb, lane 0 being protocol 8. + * This only applies to SoCs that define SRDS_BITS_PER_LANE and have + * independent per-lane protocol configuration, at this time LS1028A and + * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all + * lanes as a single value. + */ + for (int i = 0; i < SRDS_MAX_LANES; i++) { + int tmp; + + tmp = cfg >> (i * SRDS_BITS_PER_LANE); + tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0); + tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE; + cfgr |= tmp; + } +#endif /* SRDS_BITS_PER_LANE */ + + snprintf(snum, 16, "serdes%d", sd); + snprintf(scfg, 16, "%x", cfgr); + env_set(snum, scfg); + + return 0; +} + +int serdes_misc_init(void) +{ +#ifdef CONFIG_SYS_FSL_SRDS_1 + serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR, + FSL_CHASSIS3_SRDS1_PRTCL_MASK, + FSL_CHASSIS3_SRDS1_PRTCL_SHIFT); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR, + FSL_CHASSIS3_SRDS2_PRTCL_MASK, + FSL_CHASSIS3_SRDS2_PRTCL_SHIFT); +#endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR, + FSL_CHASSIS3_SRDS3_PRTCL_MASK, + FSL_CHASSIS3_SRDS3_PRTCL_SHIFT); +#endif + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c index 313f3f1e8a..80d2910f67 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -35,6 +35,10 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} }, {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} }, {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} }, + {0x7777, {SGMII1, SGMII2, SGMII3, SGMII4} }, + {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} }, + {0xb998, {SGMII_T1, SGMII2, SGMII3, PCIE1} }, + {0xbb56, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} }, {} }; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index 8e8b45ad9b..280afbbf98 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP */ #include <common.h> #include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <asm/io.h> struct serdes_config { u8 ip_protocol; @@ -32,6 +34,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } }, {} }; + static struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ {0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } }, @@ -48,6 +51,15 @@ static struct serdes_config *serdes_cfg_tbl[] = { serdes2_cfg_tbl, }; +bool soc_has_mac1(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr = gur_in32(&gur->svr); + unsigned int version = SVR_SOC_VER(svr); + + return (version == SVR_LS1088A || version == SVR_LS1084A); +} + int serdes_get_number(int serdes, int cfg) { struct serdes_config *ptr; @@ -87,7 +99,14 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) return 0; - + /* + * LS1044A/1048A support only one XFI port + * Disable MAC1 for LS1044A/1048A + */ + if (serdes == FSL_SRDS_1 && lane == 2) { + if (!soc_has_mac1()) + return 0; + } ptr = serdes_cfg_tbl[serdes]; while (ptr->ip_protocol) { if (ptr->ip_protocol == cfg) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 2175266a30..d0e10cb007 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -647,6 +647,11 @@ void fsl_lsch2_early_init_f(void) SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | SCFG_SNPCNFGCR_SATAWRSNP); +#elif defined(CONFIG_ARCH_LS1012A) + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); #else setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP | diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5075038c6a..9303beb2f5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -353,6 +353,7 @@ dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ am57xx-beagle-x15-revb1.dtb \ am57xx-beagle-x15-revc.dtb \ + am5729-beagleboneai.dtb \ am574x-idk.dtb \ am572x-idk.dtb \ am571x-idk.dtb @@ -388,6 +389,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb +dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb + dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ stm32429i-eval.dtb \ stm32f469-disco.dtb @@ -683,6 +686,7 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-colibri.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ + imx6ull-somlabs-visionsom.dtb \ imx6ulz-14x14-evk.dtb dtb-$(CONFIG_ARCH_MX6) += \ @@ -862,6 +866,9 @@ dtb-$(CONFIG_ARCH_BCM283X) += \ dtb-$(CONFIG_ARCH_BCM63158) += \ bcm963158.dtb +dtb-$(CONFIG_ARCH_BCM68360) += \ + bcm968360bg.dtb + dtb-$(CONFIG_ARCH_BCM6858) += \ bcm968580xref.dtb @@ -869,7 +876,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb -dtb-$(CONFIG_TARGET_STM32MP1) += \ +dtb-$(CONFIG_STM32MP15x) += \ stm32mp157a-dk1.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157c-dk2.dtb \ diff --git a/arch/arm/dts/am5729-beagleboneai.dts b/arch/arm/dts/am5729-beagleboneai.dts new file mode 100644 index 0000000000..34293034e3 --- /dev/null +++ b/arch/arm/dts/am5729-beagleboneai.dts @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +#include "dra74x.dtsi" +#include "dra74x-mmc-iodelay.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/dra.h> + +/ { + model = "BeagleBoard.org BeagleBone AI"; + compatible = "beagle,am5729-beagleboneai", "ti,am5728", + "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &tps659038_rtc; + rtc1 = &rtc; + display0 = &hdmi_conn; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + vdd_adc: gpioregulator-vdd_adc { + compatible = "regulator-gpio"; + regulator-name = "vdd_adc"; + vin-supply = <&vdd_5v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + states = <1800000 0 + 3300000 1>; + }; + + vdd_5v: fixedregulator-vdd_5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&vdd_ddr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "beaglebone:green:usr0"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led1 { + label = "beaglebone:green:usr1"; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + label = "beaglebone:green:usr2"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu"; + default-state = "off"; + }; + + led3 { + label = "beaglebone:green:usr3"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "beaglebone:green:usr4"; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + default-state = "off"; + }; + }; + + hdmi_conn: connector@0 { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_encoder_out>; + }; + }; + }; + + hdmi_enc: encoder@0 { + /* "ti,tpd12s016" software compatible with "ti,tpd12s015" + * no need for individual driver + */ + compatible = "ti,tpd12s015"; + gpios = <0>, + <0>, + <&gpio7 12 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + + hdmi_encoder_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <0x1>; + + hdmi_encoder_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + emmc_pwrseq: emmc_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + }; + + brcmf_pwrseq: brcmf_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */ + <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + ti,enable-id-detection; + id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + ti,palmas-override-powerhold; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + smps12-in-supply = <&vdd_5v>; + smps3-in-supply = <&vdd_5v>; + smps45-in-supply = <&vdd_5v>; + smps6-in-supply = <&vdd_5v>; + smps7-in-supply = <&vdd_5v>; + mps3-in-supply = <&vdd_5v>; + smps8-in-supply = <&vdd_5v>; + smps9-in-supply = <&vdd_5v>; + ldo1-in-supply = <&vdd_5v>; + ldo2-in-supply = <&vdd_5v>; + ldo3-in-supply = <&vdd_5v>; + ldo4-in-supply = <&vdd_5v>; + ldo9-in-supply = <&vdd_5v>; + ldoln-in-supply = <&vdd_5v>; + ldousb-in-supply = <&vdd_5v>; + ldortc-in-supply = <&vdd_5v>; + + regulators { + vdd_mpu: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ddr: smps3 { + /* VDD_DDR EMIF1 EMIF2 */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_dspeve: smps45 { + /* VDD_DSPEVE on AM572 */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_gpu: smps6 { + /* VDD_GPU */ + regulator-name = "smps6"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_core: smps7 { + /* VDD_CORE */ + regulator-name = "smps7"; + regulator-min-microvolt = < 850000>; /*** 1.15V */ + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_iva: smps8 { + /* VDD_IVAHD */ /*** 1.06V */ + regulator-name = "smps8"; + }; + + vdd_3v3: smps9 { + /* VDD_3V3 */ + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_sd: ldo1 { + /* VDDSHV8 - VSDMMC */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_1v8: ldo2 { + /* VDDSH18V */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_phy_ldo3: ldo3 { + /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_phy_ldo4: ldo4 { + /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* LDO5-8 unused */ + + vdd_rtc: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = < 840000>; + regulator-max-microvolt = <1160000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_pll: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldortc_reg: ldortc { + /* VDDA_RTC */ + regulator-name = "ldortc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + + regen2: regen2 { + /* Needed for PMIC internal resource */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + +&mcspi3 { + status = "okay"; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; +}; + +&cpu0 { + vdd-supply = <&vdd_mpu>; + voltage-tolerance = <1>; +}; + +&uart1 { + status = "okay"; +}; + +&davinci_mdio { + reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; + + phy0: ethernet-phy@1 { + reg = <4>; + eee-broken-100tx; + eee-broken-1000t; + }; +}; + +&mac { + slaves = <1>; + status = "okay"; +}; + +&cpsw_emac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii"; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_sd>; + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vdd_1v8>; + vqmmc-supply = <&vdd_1v8>; + bus-width = <8>; + ti,non-removable; + non-removable; + mmc-pwrseq = <&emmc_pwrseq>; + + ti,needs-special-reset; + dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; + dma-names = "tx", "rx"; + + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20>; + pinctrl-3 = <&mmc2_pins_hs200>; + +}; + +&mmc4 { + /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */ + /* HS: High speed up to 50 MHz (3.3 V signaling). */ + /* SDR12: SDR up to 25 MHz (1.8 V signaling). */ + /* SDR25: SDR up to 50 MHz (1.8 V signaling). */ + /* SDR50: SDR up to 100 MHz (1.8 V signaling). */ + /* SDR104: SDR up to 208 MHz (1.8 V signaling) */ + /* DDR50: DDR up to 50 MHz (1.8 V signaling). */ + status = "okay"; + + ti,needs-special-reset; + vmmc-supply = <&vdd_3v3>; + cap-power-off-card; + keep-power-in-suspend; + bus-width = <4>; + ti,non-removable; + non-removable; + no-1-8-v; + max-frequency = <24000000>; + + #address-cells = <1>; + #size-cells = <0>; + mmc-pwrseq = <&brcmf_pwrseq>; + + brcmf: wifi@1 { + status = "okay"; + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + brcm,sd-head-align = <4>; + brcm,sd_head_align = <4>; + brcm,sd_sgentry_align = <512>; + + interrupt-parent = <&gpio3>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + status = "okay"; + dr_mode = "otg"; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&usb2 { + status = "okay"; + dr_mode = "host"; +}; + +&dss { + status = "okay"; + vdda_video-supply = <&vdd_1v8_pll>; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&vdd_1v8_phy_ldo4>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_encoder_in>; + }; + }; +}; + +&bandgap { + status = "okay"; +}; + +&cpu_alert0 { + temperature = <55000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&sata { + status = "disabled"; +}; + +&sata_phy { + status = "disabled"; +}; + +/* bluetooth */ +&uart6 { + status = "okay"; +}; + +/* cape header stuff */ +&i2c4 { + status = "okay"; + clock-frequency = <100000>; +}; + +#include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/armada-388-clearfog-u-boot.dtsi b/arch/arm/dts/armada-388-clearfog-u-boot.dtsi index 38e4f3d99a..20f5c8fb8c 100644 --- a/arch/arm/dts/armada-388-clearfog-u-boot.dtsi +++ b/arch/arm/dts/armada-388-clearfog-u-boot.dtsi @@ -23,3 +23,15 @@ &ahci1 { u-boot,dm-spl; }; + +&i2c0 { + u-boot,dm-spl; + + eeprom@52 { + u-boot,dm-spl; + }; + + eeprom@53 { + u-boot,dm-spl; + }; +}; diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts index 4ddeaa02f1..e4164f49b2 100644 --- a/arch/arm/dts/armada-388-clearfog.dts +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -259,6 +259,12 @@ compatible = "microchip,mcp3021"; reg = <0x4c>; }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; }; &i2c1 { diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi index a2627223ce..a322a28c21 100644 --- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -99,3 +99,11 @@ status = "okay"; u-boot,dm-pre-reloc; }; + +&i2c0 { + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; diff --git a/arch/arm/dts/bcm68360.dtsi b/arch/arm/dts/bcm68360.dtsi new file mode 100644 index 0000000000..7bbe207794 --- /dev/null +++ b/arch/arm/dts/bcm68360.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#include "skeleton64.dtsi" + +/ { + compatible = "brcm,bcm68360"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + spi0 = &hsspi; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + l2: l2-cache0 { + compatible = "cache"; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + u-boot,dm-pre-reloc; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_osc>; + clock-mult = <2>; + clock-div = <1>; + }; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + + wdt1: watchdog@ff800480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff800480 0x0 0x14>; + clocks = <&refclk50mhz>; + }; + + wdt2: watchdog@ff8004c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff8004c0 0x0 0x14>; + clocks = <&refclk50mhz>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; + + uart0: serial@ff800640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x0 0xff800640 0x0 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + leds: led-controller@ff800800 { + compatible = "brcm,bcm6858-leds"; + reg = <0x0 0xff800800 0x0 0xe4>; + + status = "disabled"; + }; + + gpio0: gpio-controller@0xff800500 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800500 0x0 0x4>, + <0x0 0xff800520 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio1: gpio-controller@0xff800504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800504 0x0 0x4>, + <0x0 0xff800524 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio2: gpio-controller@0xff800508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800508 0x0 0x4>, + <0x0 0xff800528 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio3: gpio-controller@0xff80050c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff80050c 0x0 0x4>, + <0x0 0xff80052c 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio4: gpio-controller@0xff800510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800510 0x0 0x4>, + <0x0 0xff800530 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio5: gpio-controller@0xff800514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800514 0x0 0x4>, + <0x0 0xff800534 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio6: gpio-controller@0xff800518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800518 0x0 0x4>, + <0x0 0xff800538 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio7: gpio-controller@0xff80051c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff80051c 0x0 0x4>, + <0x0 0xff80053c 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + hsspi: spi-controller@ff801000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xff801000 0x0 0x600>; + clocks = <&hsspi_pll>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + spi-max-frequency = <100000000>; + num-cs = <8>; + + status = "disabled"; + }; + + nand: nand-controller@ff801800 { + compatible = "brcm,nand-bcm68360", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x0 0xff801800 0x0 0x180>, + <0x0 0xff802000 0x0 0x10>, + <0x0 0xff801c00 0x0 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm968360bg.dts b/arch/arm/dts/bcm968360bg.dts new file mode 100644 index 0000000000..c060294cc9 --- /dev/null +++ b/arch/arm/dts/bcm968360bg.dts @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com> + */ + +/dts-v1/; + +#include "bcm68360.dtsi" + +/ { + model = "Broadcom bcm68360bg"; + compatible = "broadcom,bcm68360bg", "brcm,bcm68360"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio6 { + status = "okay"; +}; + +&gpio7 { + status = "okay"; +}; + +&nand { + status = "okay"; + write-protect = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + }; +}; + +&leds { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + brcm,serial-led-en-pol; + brcm,serial-led-data-ppol; + + led@0 { + reg = <0>; + label = "red:alarm"; + }; + + led@1 { + reg = <1>; + label = "green:wan"; + }; + + led@2 { + reg = <2>; + label = "green:wps"; + }; + + led@12 { + reg = <12>; + label = "orange:enet5.1"; + }; + + led@13 { + reg = <13>; + label = "green:enet5.2"; + }; + + led@14 { + reg = <14>; + label = "orange:enet5.2"; + }; + + led@15 { + reg = <15>; + label = "green:enet5.1"; + }; + + led@16 { + reg = <16>; + label = "green:usb1"; + }; + + led@17 { + reg = <17>; + label = "green:voip1"; + }; + + led@18 { + reg = <18>; + label = "green:voip2"; + }; + + led@19 { + reg = <19>; + label = "green:enet6"; + }; + + led@20 { + reg = <20>; + label = "orange:enet6"; + }; + + led@21 { + reg = <21>; + label = "green:inet"; + }; + + led@22 { + reg = <22>; + label = "green:usb2"; + }; +}; + +&hsspi { + status = "okay"; + + flash: mt25@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi index 541f4ca200..b372d06ca9 100644 --- a/arch/arm/dts/da850-lcdk-u-boot.dtsi +++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi @@ -8,9 +8,23 @@ / { aliases { i2c0 = &i2c0; + mmc0 = &mmc0; + serial2 = &serial2; + }; + + soc@1c00000 { + u-boot,dm-spl; }; nand { compatible = "ti,davinci-nand"; }; }; + +&mmc0 { + u-boot,dm-spl; +}; + +&serial2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts index 0177e3ed20..db8ae566f3 100644 --- a/arch/arm/dts/da850-lcdk.dts +++ b/arch/arm/dts/da850-lcdk.dts @@ -18,7 +18,7 @@ }; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = &serial2; }; memory@c0000000 { diff --git a/arch/arm/dts/fsl-imx8-ca35.dtsi b/arch/arm/dts/fsl-imx8-ca35.dtsi index 28bc32c8b7..9af8b1511c 100644 --- a/arch/arm/dts/fsl-imx8-ca35.dtsi +++ b/arch/arm/dts/fsl-imx8-ca35.dtsi @@ -18,6 +18,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; + #cooling-cells = <2>; }; A35_1: cpu@1 { @@ -26,6 +27,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; + #cooling-cells = <2>; }; A35_2: cpu@2 { @@ -34,6 +36,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A35_L2>; + #cooling-cells = <2>; }; A35_3: cpu@3 { @@ -42,6 +45,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A35_L2>; + #cooling-cells = <2>; }; A35_L2: l2-cache0 { diff --git a/arch/arm/dts/imx6ull-somlabs-visionsom.dts b/arch/arm/dts/imx6ull-somlabs-visionsom.dts new file mode 100644 index 0000000000..868f3f8440 --- /dev/null +++ b/arch/arm/dts/imx6ull-somlabs-visionsom.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2019 SoMLabs + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "imx6ull.dtsi" + +/ { + model = "SoMLabs VisionSOM-6ULL"; + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + usr0 { + label = "usr0"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + usr1 { + label = "usr1"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + usr2 { + label = "usr2"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + + usr3 { + label = "usr3"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; + +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + /* 32kHz low power reference clock for WiFi */ + MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099 + /* LED 0..3 */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099 + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099 + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099 + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829 + + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0 + >; + }; + + pinctrl_usb_otg2: usbotg2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0 + >; + }; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc2 { + non-removable; + disable-wp; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts index 08a682f314..8f6a935e24 100644 --- a/arch/arm/dts/imx7ulp-evk.dts +++ b/arch/arm/dts/imx7ulp-evk.dts @@ -156,7 +156,7 @@ pinctrl_backlight: backlight_grp { fsl,pins = < - IMX7ULP_PAD_PTF2__PTF2 0x20100 + IMX7ULP_PAD_PTF2__PTF2 0x20000 >; }; diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 0f5da9a563..ab40dafceb 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -251,4 +251,82 @@ interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>; }; }; + + dwc3_0: dwc3@4000000 { + compatible = "ti,am654-dwc3"; + reg = <0x0 0x4000000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x4000000 0x20000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ + + usb0: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + phys = <&usb0_phy>; + phy-names = "usb2-phy"; + snps,dis_u3_susphy_quirk; + }; + }; + + usb0_phy: phy@4100000 { + compatible = "ti,am654-usb2", "ti,omap-usb2"; + reg = <0x0 0x4100000 0x0 0x54>; + syscon-phy-power = <&scm_conf 0x4000>; + clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + ti,dis-chg-det-quirk; + }; + + dwc3_1: dwc3@4020000 { + compatible = "ti,am654-dwc3"; + reg = <0x0 0x4020000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x4020000 0x20000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 152 2>; + assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + + usb1: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + phys = <&usb1_phy>; + phy-names = "usb2-phy"; + }; + }; + + usb1_phy: phy@4110000 { + compatible = "ti,am654-usb2", "ti,omap-usb2"; + reg = <0x0 0x4110000 0x0 0x54>; + syscon-phy-power = <&scm_conf 0x4020>; + clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + ti,dis-chg-det-quirk; + }; }; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index bea80c5d00..a349edcfa5 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -25,7 +25,8 @@ compatible = "ti,am654-sdhci-5.1"; reg = <0x0 0x4FA0000 0x0 0x1000>, <0x0 0x4FB0000 0x0 0x400>; - clocks = <&k3_clks 48 1>; + clocks =<&k3_clks 48 0>, <&k3_clks 48 1>; + clock-names = "clk_ahb", "clk_xin"; power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; max-frequency = <25000000>; ti,otap-del-sel = <0x2>; @@ -360,3 +361,7 @@ &wkup_i2c0 { u-boot,dm-spl; }; + +&usb1 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index 573ead0b4d..7ebbf17862 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -58,6 +58,12 @@ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ >; }; + + usb1_pins_default: usb1_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ + >; + }; }; &wkup_pmx0 { @@ -89,3 +95,25 @@ #gpio-cells = <2>; }; }; + +&dwc3_1 { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; + dr_mode = "otg"; +}; + +&dwc3_0 { + status = "disabled"; +}; + +&usb0_phy { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 5c110ef9dd..5d5689d284 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -100,7 +100,7 @@ wkup_vtm0: wkup_vtm@42050000 { compatible = "ti,am654-vtm", "ti,am654-avs"; reg = <0x42050000 0x25c>; - power-domains = <&k3_pds 80>; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 9291e57e25..7ea4d8de36 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -282,6 +282,20 @@ u-boot,dm-spl; }; +&main_usbss0_pins_default { + u-boot,dm-spl; +}; + +&usbss0 { + u-boot,dm-spl; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "peripheral"; + u-boot,dm-spl; +}; + &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; @@ -311,3 +325,15 @@ reg-names = "gmii-sel"; }; }; + +&main_mmc1_pins_default { + u-boot,dm-spl; +}; + +&wkup_i2c0_pins_default { + u-boot,dm-spl; +}; + +&wkup_i2c0 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts index c978cabd13..f33a6d5bcf 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-common-proc-board.dts @@ -65,15 +65,83 @@ status = "disabled"; }; +&main_pmx0 { + main_mmc1_pins_default: main_mmc1_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ + J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ + J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ + J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ + J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ + J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ + J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ + J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ + >; + }; +}; + &main_sdhci0 { /* eMMC */ - voltage-ranges = <1800 1800>; non-removable; ti,driver-strength-ohm = <50>; }; &main_sdhci1 { - /* SD/MMC */ - voltage-ranges = <1800 1800 3300 3300>; + /* SD card */ + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; }; + +&main_pmx0 { + main_usbss0_pins_default: main_usbss0_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ + >; + }; + + main_usbss1_pins_default: main_usbss1_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ + >; + }; +}; + +&wkup_pmx0 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ + >; + }; +}; + +&usbss0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "super-speed"; +}; + +&usbss1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss1_pins_default>; + ti,usb2-only; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "high-speed"; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; +}; diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 3a0763209f..5083a0c3ae 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -340,6 +340,76 @@ resets = <&k3_reset 15 1>; }; + usbss0: cdns_usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4104000 0x00 0x100>; + dma-coherent; + power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; + clock-names = "usb2_refclk", "lpm_clk"; + assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + phy@4108000 { + compatible = "ti,j721e-usb2-phy"; + reg = <0x00 0x4108000 0x00 0x400>; + }; + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + usbss1: cdns_usb@4114000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4114000 0x00 0x100>; + dma-coherent; + power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; + clock-names = "usb2_refclk", "lpm_clk"; + assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + phy@4118000 { + compatible = "ti,j721e-usb2-phy"; + reg = <0x00 0x4118000 0x00 0x400>; + }; + + usb1: usb@6400000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6400000 0x00 0x10000>, + <0x00 0x6410000 0x00 0x10000>, + <0x00 0x6420000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + ufs_wrapper: ufs-wrapper@4e80000 { compatible = "ti,j721e-ufs"; reg = <0x0 0x4e80000 0x0 0x100>; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 41af48214f..28a355d49c 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -112,6 +112,27 @@ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; + + main_usbss0_pins_default: main_usbss0_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ + >; + }; + + main_mmc1_pins_default: main_mmc1_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ + J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ + J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ + J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ + J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ + J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ + J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ + J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ + >; + }; }; &wkup_uart0 { @@ -149,6 +170,8 @@ /delete-property/ power-domains; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; clock-names = "clk_xin"; clocks = <&clk_200mhz>; ti,driver-strength-ohm = <50>; diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi index 1abd9a3887..173b492cd9 100644 --- a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi @@ -17,16 +17,44 @@ }; }; +&gpio1 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio2 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio3 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio4 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio5 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio6 { + /delete-property/ u-boot,dm-spl; +}; + &i2c1 { clock-frequency = <400000>; + /delete-property/ u-boot,dm-spl; }; &i2c2 { clock-frequency = <400000>; + /delete-property/ u-boot,dm-spl; }; +/delete-node/ &bandgap; /delete-node/ &uart2; /delete-node/ &uart3; /delete-node/ &mmc2; /delete-node/ &mmc3; +/delete-node/ &thermal_zones; diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi index e5d9e4f1b1..173b492cd9 100644 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi @@ -29,6 +29,10 @@ /delete-property/ u-boot,dm-spl; }; +&gpio4 { + /delete-property/ u-boot,dm-spl; +}; + &gpio5 { /delete-property/ u-boot,dm-spl; }; @@ -39,14 +43,18 @@ &i2c1 { clock-frequency = <400000>; + /delete-property/ u-boot,dm-spl; }; &i2c2 { clock-frequency = <400000>; + /delete-property/ u-boot,dm-spl; }; +/delete-node/ &bandgap; /delete-node/ &uart2; /delete-node/ &uart3; /delete-node/ &mmc2; /delete-node/ &mmc3; +/delete-node/ &thermal_zones; diff --git a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi index 1635e42b55..581247def0 100644 --- a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi @@ -7,21 +7,53 @@ #include "omap3-u-boot.dtsi" / { + chosen { + stdout-path = &uart1; + }; + aliases { /delete-property/ serial1; /delete-property/ serial2; }; }; +&gpio1 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio2 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio3 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio4 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio5 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio6 { + /delete-property/ u-boot,dm-spl; +}; + &i2c1 { clock-frequency = <400000>; + /delete-property/ u-boot,dm-spl; }; &i2c2 { clock-frequency = <400000>; + /delete-property/ u-boot,dm-spl; }; +/delete-node/ &bandgap; /delete-node/ &uart2; /delete-node/ &uart3; /delete-node/ &mmc2; /delete-node/ &mmc3; +/delete-node/ &thermal_zones; diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi index 76f74326ae..9b709c147c 100644 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi @@ -15,6 +15,7 @@ &i2c1 { clock-frequency = <400000>; + /delete-property/ u-boot,dm-spl; }; &i2c2 { @@ -33,6 +34,10 @@ /delete-property/ u-boot,dm-spl; }; +&gpio4 { + /delete-property/ u-boot,dm-spl; +}; + &gpio5 { /delete-property/ u-boot,dm-spl; }; @@ -41,8 +46,9 @@ /delete-property/ u-boot,dm-spl; }; +/delete-node/ &bandgap; /delete-node/ &uart2; /delete-node/ &uart3; /delete-node/ &mmc2; /delete-node/ &mmc3; - +/delete-node/ &thermal_zones; diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi index c2d17fda4a..56da91a9fe 100644 --- a/arch/arm/dts/mt8518.dtsi +++ b/arch/arm/dts/mt8518.dtsi @@ -74,6 +74,19 @@ }; }; + usb0: usb@11100000 { + compatible = "mediatek,mt8518-musb"; + reg = <0x11100000 0x1000>; + reg-names = "control"; + clocks = <&topckgen CLK_TOP_USB20_48M>, + <&topckgen CLK_TOP_USBIF>, + <&topckgen CLK_TOP_USB>; + clock-names = "usbpll", "usbmcu", "usb"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "mc"; + status = "okay"; + }; + mmc0: mmc@11120000 { compatible = "mediatek,mt8516-mmc"; reg = <0x11120000 0x1000>; diff --git a/arch/arm/dts/ste-ab8500.dtsi b/arch/arm/dts/ste-ab8500.dtsi new file mode 100644 index 0000000000..14d4d8617d --- /dev/null +++ b/arch/arm/dts/ste-ab8500.dtsi @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Linaro Ltd + */ + +#include <dt-bindings/clock/ste-ab8500.h> + +/ { + /* Essential housekeeping hardware monitors */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&gpadc 0x02>, /* Battery temperature */ + <&gpadc 0x03>, /* Main charger voltage */ + <&gpadc 0x08>, /* Main battery voltage */ + <&gpadc 0x09>, /* VBUS */ + <&gpadc 0x0a>, /* Main charger current */ + <&gpadc 0x0b>, /* USB charger current */ + <&gpadc 0x0c>, /* Backup battery voltage */ + <&gpadc 0x0d>, /* Die temperature */ + <&gpadc 0x12>; /* Crystal temperature */ + }; + + soc { + prcmu@80157000 { + ab8500 { + compatible = "stericsson,ab8500"; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + ab8500_clock: clock-controller { + compatible = "stericsson,ab8500-clk"; + #clock-cells = <1>; + }; + + ab8500_gpio: ab8500-gpio { + compatible = "stericsson,ab8500-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + ab8500-rtc { + compatible = "stericsson,ab8500-rtc"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH + 18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "60S", "ALARM"; + }; + + gpadc: ab8500-gpadc { + compatible = "stericsson,ab8500-gpadc"; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH + 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "HW_CONV_END", "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* GPADC channels */ + bat_ctrl: channel@01 { + reg = <0x01>; + }; + btemp_ball: channel@02 { + reg = <0x02>; + }; + main_charger_v: channel@03 { + reg = <0x03>; + }; + acc_detect1: channel@04 { + reg = <0x04>; + }; + acc_detect2: channel@05 { + reg = <0x05>; + }; + adc_aux1: channel@06 { + reg = <0x06>; + }; + adc_aux2: channel@07 { + reg = <0x07>; + }; + main_batt_v: channel@08 { + reg = <0x08>; + }; + vbus_v: channel@09 { + reg = <0x09>; + }; + main_charger_c: channel@0a { + reg = <0x0a>; + }; + usb_charger_c: channel@0b { + reg = <0x0b>; + }; + bk_bat_v: channel@0c { + reg = <0x0c>; + }; + die_temp: channel@0d { + reg = <0x0d>; + }; + usb_id: channel@0e { + reg = <0x0e>; + }; + xtal_temp: channel@12 { + reg = <0x12>; + }; + vbat_true_meas: channel@13 { + reg = <0x13>; + }; + bat_ctrl_and_ibat: channel@1c { + reg = <0x1c>; + }; + vbat_meas_and_ibat: channel@1d { + reg = <0x1d>; + }; + vbat_true_meas_and_ibat: channel@1e { + reg = <0x1e>; + }; + bat_temp_and_ibat: channel@1f { + reg = <0x1f>; + }; + }; + + ab8500_temp { + compatible = "stericsson,abx500-temp"; + io-channels = <&gpadc 0x06>, + <&gpadc 0x07>; + io-channel-name = "aux1", "aux2"; + }; + + ab8500_battery: ab8500_battery { + stericsson,battery-type = "LIPO"; + thermistor-on-batctrl; + }; + + ab8500_fg { + compatible = "stericsson,ab8500-fg"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x08>; + io-channel-name = "main_bat_v"; + }; + + ab8500_btemp { + compatible = "stericsson,ab8500-btemp"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x02>, + <&gpadc 0x01>; + io-channel-name = "btemp_ball", + "bat_ctrl"; + }; + + ab8500_charger { + compatible = "stericsson,ab8500-charger"; + battery = <&ab8500_battery>; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + io-channels = <&gpadc 0x03>, + <&gpadc 0x0a>, + <&gpadc 0x09>, + <&gpadc 0x0b>; + io-channel-name = "main_charger_v", + "main_charger_c", + "vbus_v", + "usb_charger_c"; + }; + + ab8500_chargalg { + compatible = "stericsson,ab8500-chargalg"; + battery = <&ab8500_battery>; + }; + + ab8500_usb { + compatible = "stericsson,ab8500-usb"; + interrupts = < 90 IRQ_TYPE_LEVEL_HIGH + 96 IRQ_TYPE_LEVEL_HIGH + 14 IRQ_TYPE_LEVEL_HIGH + 15 IRQ_TYPE_LEVEL_HIGH + 79 IRQ_TYPE_LEVEL_HIGH + 74 IRQ_TYPE_LEVEL_HIGH + 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_ADP_PROBE_PLUG", + "USB_ADP_PROBE_UNPLUG"; + vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; + v-ape-supply = <&db8500_vape_reg>; + musb_1v8-supply = <&db8500_vsmps2_reg>; + clocks = <&prcmu_clk PRCMU_SYSCLK>; + clock-names = "sysclk"; + }; + + ab8500-ponkey { + compatible = "stericsson,ab8500-poweron-key"; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH + 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + + ab8500-sysctrl { + compatible = "stericsson,ab8500-sysctrl"; + }; + + ab8500-pwm { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-debugfs { + compatible = "stericsson,ab8500-debug"; + }; + + codec: ab8500-codec { + compatible = "stericsson,ab8500-codec"; + + V-AUD-supply = <&ab8500_ldo_audio_reg>; + V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; + V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; + V-DMIC-supply = <&ab8500_ldo_dmic_reg>; + + clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; + clock-names = "audioclk"; + + stericsson,earpeice-cmv = <950>; /* Units in mV. */ + }; + + ext_regulators: ab8500-ext-regulators { + compatible = "stericsson,ab8500-ext-regulator"; + + ab8500_ext1_reg: ab8500_ext1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ab8500_ext2_reg: ab8500_ext2 { + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-boot-on; + regulator-always-on; + }; + + ab8500_ext3_reg: ab8500_ext3 { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + }; + + ab8500-regulators { + compatible = "stericsson,ab8500-regulator"; + vin-supply = <&ab8500_ext3_reg>; + + // supplies to the display/camera + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + /* BUG: If turned off MMC will be affected. */ + regulator-always-on; + }; + + // supplies to the on-board eMMC + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + // supply for VAUX3; SDcard slots + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + // supply for v-intcore12; VINTCORE12 LDO + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + }; + + // supply for tvout; gpadc; TVOUT LDO + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + }; + + // supply for ab8500-vaudio; VAUDIO LDO + ab8500_ldo_audio_reg: ab8500_ldo_audio { + }; + + // supply for v-anamic1 VAMIC1 LDO + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + }; + + // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + }; + + // supply for v-dmic; VDMIC LDO + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + }; + + // supply for U8500 CSI/DSI; VANA LDO + ab8500_ldo_ana_reg: ab8500_ldo_ana { + }; + }; + }; + }; + + sound { + stericsson,audio-codec = <&codec>; + clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "sysclk", "ulpclk", "intclk"; + }; + + mcde@a0350000 { + vana-supply = <&ab8500_ldo_ana_reg>; + + dsi@a0351000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0352000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0353000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + }; + }; +}; diff --git a/arch/arm/dts/ste-ab8505.dtsi b/arch/arm/dts/ste-ab8505.dtsi new file mode 100644 index 0000000000..c72aa250bf --- /dev/null +++ b/arch/arm/dts/ste-ab8505.dtsi @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Linaro Ltd + */ + +#include <dt-bindings/clock/ste-ab8500.h> + +/ { + /* Essential housekeeping hardware monitors */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&gpadc 0x02>, /* Battery temperature */ + <&gpadc 0x08>, /* Main battery voltage */ + <&gpadc 0x09>, /* VBUS */ + <&gpadc 0x0b>, /* Charger current */ + <&gpadc 0x0c>; /* Backup battery voltage */ + }; + + soc { + prcmu@80157000 { + ab8505 { + compatible = "stericsson,ab8505"; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + ab8500_clock: clock-controller { + compatible = "stericsson,ab8500-clk"; + #clock-cells = <1>; + }; + + ab8505_gpio: ab8505-gpio { + compatible = "stericsson,ab8505-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + ab8500-rtc { + compatible = "stericsson,ab8500-rtc"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH + 18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "60S", "ALARM"; + }; + + gpadc: ab8500-gpadc { + compatible = "stericsson,ab8500-gpadc"; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH + 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "HW_CONV_END", "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_adc_reg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* GPADC channels */ + bat_ctrl: channel@01 { + reg = <0x01>; + }; + btemp_ball: channel@02 { + reg = <0x02>; + }; + acc_detect1: channel@04 { + reg = <0x04>; + }; + acc_detect2: channel@05 { + reg = <0x05>; + }; + adc_aux1: channel@06 { + reg = <0x06>; + }; + adc_aux2: channel@07 { + reg = <0x07>; + }; + main_batt_v: channel@08 { + reg = <0x08>; + }; + vbus_v: channel@09 { + reg = <0x09>; + }; + charger_c: channel@0b { + reg = <0x0b>; + }; + bk_bat_v: channel@0c { + reg = <0x0c>; + }; + usb_id: channel@0e { + reg = <0x0e>; + }; + }; + + ab8500_battery: ab8500_battery { + status = "disabled"; + thermistor-on-batctrl; + }; + + ab8500_fg { + status = "disabled"; + compatible = "stericsson,ab8500-fg"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x08>; + io-channel-name = "main_bat_v"; + }; + + ab8500_btemp { + status = "disabled"; + compatible = "stericsson,ab8500-btemp"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x02>, + <&gpadc 0x01>; + io-channel-name = "btemp_ball", + "bat_ctrl"; + }; + + ab8500_charger { + status = "disabled"; + compatible = "stericsson,ab8500-charger"; + battery = <&ab8500_battery>; + vddadc-supply = <&ab8500_ldo_adc_reg>; + io-channels = <&gpadc 0x09>, + <&gpadc 0x0b>; + io-channel-name = "vbus_v", + "usb_charger_c"; + }; + + ab8500_chargalg { + status = "disabled"; + compatible = "stericsson,ab8500-chargalg"; + battery = <&ab8500_battery>; + }; + + ab8500_usb: ab8500_usb { + compatible = "stericsson,ab8500-usb"; + interrupts = < 90 IRQ_TYPE_LEVEL_HIGH + 96 IRQ_TYPE_LEVEL_HIGH + 14 IRQ_TYPE_LEVEL_HIGH + 15 IRQ_TYPE_LEVEL_HIGH + 79 IRQ_TYPE_LEVEL_HIGH + 74 IRQ_TYPE_LEVEL_HIGH + 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_ADP_PROBE_PLUG", + "USB_ADP_PROBE_UNPLUG"; + vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; + v-ape-supply = <&db8500_vape_reg>; + musb_1v8-supply = <&db8500_vsmps2_reg>; + clocks = <&prcmu_clk PRCMU_SYSCLK>; + clock-names = "sysclk"; + }; + + ab8500-ponkey { + compatible = "stericsson,ab8500-poweron-key"; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH + 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + + ab8500-sysctrl { + compatible = "stericsson,ab8500-sysctrl"; + }; + + ab8500-pwm { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-debugfs { + compatible = "stericsson,ab8500-debug"; + }; + + codec: ab8500-codec { + compatible = "stericsson,ab8500-codec"; + + V-AUD-supply = <&ab8500_ldo_audio_reg>; + V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; + V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; + + clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; + clock-names = "audioclk"; + + stericsson,earpeice-cmv = <950>; /* Units in mV. */ + }; + + ab8505-regulators { + compatible = "stericsson,ab8505-regulator"; + + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux4_reg: ab8500_ldo_aux4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5_reg: ab8500_ldo_aux5 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2790000>; + }; + + ab8500_ldo_aux6_reg: ab8500_ldo_aux6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2790000>; + }; + + // supply for v-intcore12; VINTCORE12 LDO + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + }; + + // supply for gpadc; ADC LDO + ab8500_ldo_adc_reg: ab8500_ldo_adc { + }; + + // supply for ab8500-vaudio; VAUDIO LDO + ab8500_ldo_audio_reg: ab8500_ldo_audio { + }; + + // supply for v-anamic1 VAMIC1 LDO + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + }; + + // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + }; + + // supply for v-aux8; VAUX8 LDO + ab8500_ldo_aux8_reg: ab8500_ldo_aux8 { + }; + + // supply for U8500 CSI/DSI; VANA LDO + ab8500_ldo_ana_reg: ab8500_ldo_ana { + }; + }; + }; + }; + + sound { + stericsson,audio-codec = <&codec>; + clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "sysclk", "ulpclk", "intclk"; + }; + + mcde@a0350000 { + vana-supply = <&ab8500_ldo_ana_reg>; + + dsi@a0351000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0352000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0353000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + }; + }; +}; diff --git a/arch/arm/dts/ste-dbx5x0-u-boot.dtsi b/arch/arm/dts/ste-dbx5x0-u-boot.dtsi new file mode 100644 index 0000000000..4a99ee5a92 --- /dev/null +++ b/arch/arm/dts/ste-dbx5x0-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "skeleton.dtsi" +#include "ste-dbx5x0.dtsi" + +/ { + soc { + /* FIXME: Remove this when clk driver is implemented */ + mtu@a03c6000 { + clock-frequency = <133000000>; + }; + uart@80120000 { + clock = <38400000>; + }; + uart@80121000 { + clock = <38400000>; + }; + uart@80007000 { + clock = <38400000>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&prcmu>; + offset = <0x228>; /* PRCM_APE_SOFTRST */ + mask = <0x1>; + }; +}; diff --git a/arch/arm/dts/ste-dbx5x0.dtsi b/arch/arm/dts/ste-dbx5x0.dtsi new file mode 100644 index 0000000000..6671f74c9f --- /dev/null +++ b/arch/arm/dts/ste-dbx5x0.dtsi @@ -0,0 +1,1144 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Linaro Ltd + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mfd/dbx500-prcmu.h> +#include <dt-bindings/arm/ux500_pm_domains.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + /* This stablilizes the device enumeration */ + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "ste,dbx500-smp"; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + }; + CPU0: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x300>; + clocks = <&prcmu_clk PRCMU_ARMSS>; + clock-names = "cpu"; + clock-latency = <20000>; + #cooling-cells = <2>; + }; + CPU1: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x301>; + }; + }; + + thermal-zones { + /* + * Thermal zone for the SoC, using the thermal sensor in the + * PRCMU for temperature and the cpufreq driver for passive + * cooling. + */ + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + /* + * This sensor fires interrupts to update the thermal + * zone, so no polling is needed. + */ + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu_alert: cpu-alert { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu-crit { + temperature = <85000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + trip = <&cpu_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <100>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "stericsson,db8500", "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + ptm@801ae000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x801ae000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + cpu = <&CPU0>; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + ptm@801af000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x801af000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + cpu = <&CPU1>; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; + + funnel@801a6000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x801a6000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "atclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + tpiu@80190000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x80190000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + etb@801a4000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x801a4000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + + scu@a0410000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; + }; + + /* + * The backup RAM is used for retention during sleep + * and various things like spin tables + */ + backupram@80150000 { + compatible = "ste,dbx500-backupram"; + reg = <0x80150000 0x2000>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xa0412000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + pm_domains: pm_domains0 { + compatible = "stericsson,ux500-pm-domains"; + #power-domain-cells = <1>; + }; + + clocks { + compatible = "stericsson,u8500-clks"; + /* + * Registers for the CLKRST block on peripheral + * groups 1, 2, 3, 5, 6, + */ + reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, + <0x8000f000 0x1000>, <0xa03ff000 0x1000>, + <0xa03cf000 0x1000>; + + prcmu_clk: prcmu-clock { + #clock-cells = <1>; + }; + + prcc_pclk: prcc-periph-clock { + #clock-cells = <2>; + }; + + prcc_kclk: prcc-kernel-clock { + #clock-cells = <2>; + }; + + rtc_clk: rtc32k-clock { + #clock-cells = <0>; + }; + + smp_twd_clk: smp-twd-clock { + #clock-cells = <0>; + }; + }; + + mtu@a03c6000 { + /* Nomadik System Timer */ + compatible = "st,nomadik-mtu"; + reg = <0xa03c6000 0x1000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; + clock-names = "timclk", "apb_pclk"; + }; + + timer@a0410600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xa0410600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; + + clocks = <&smp_twd_clk>; + }; + + watchdog@a0410620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xa0410620 0x20>; + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&smp_twd_clk>; + }; + + rtc@80154000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x80154000 0x1000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&rtc_clk>; + clock-names = "apb_pclk"; + }; + + gpio0: gpio@8012e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8012e000 0x80>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + clocks = <&prcc_pclk 1 9>; + }; + + gpio1: gpio@8012e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8012e080 0x80>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <1>; + gpio-ranges = <&pinctrl 0 32 5>; + clocks = <&prcc_pclk 1 9>; + }; + + gpio2: gpio@8000e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e000 0x80>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio3: gpio@8000e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e080 0x80>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <3>; + gpio-ranges = <&pinctrl 0 96 2>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio4: gpio@8000e100 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e100 0x80>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <4>; + gpio-ranges = <&pinctrl 0 128 32>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio5: gpio@8000e180 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e180 0x80>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <5>; + gpio-ranges = <&pinctrl 0 160 12>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio6: gpio@8011e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8011e000 0x80>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <6>; + gpio-ranges = <&pinctrl 0 192 32>; + clocks = <&prcc_pclk 2 11>; + }; + + gpio7: gpio@8011e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8011e080 0x80>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <7>; + gpio-ranges = <&pinctrl 0 224 7>; + clocks = <&prcc_pclk 2 11>; + }; + + gpio8: gpio@a03fe000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0xa03fe000 0x80>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <8>; + gpio-ranges = <&pinctrl 0 256 12>; + clocks = <&prcc_pclk 5 1>; + }; + + pinctrl: pinctrl { + compatible = "stericsson,db8500-pinctrl"; + nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, + <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, + <&gpio8>; + prcm = <&prcmu>; + }; + + usb_per5@a03e0000 { + compatible = "stericsson,db8500-musb"; + reg = <0xa03e0000 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + + dr_mode = "otg"; + + dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ + <&dma 38 0 0x0>, /* Logical - MemToDev */ + <&dma 37 0 0x2>, /* Logical - DevToMem */ + <&dma 37 0 0x0>, /* Logical - MemToDev */ + <&dma 36 0 0x2>, /* Logical - DevToMem */ + <&dma 36 0 0x0>, /* Logical - MemToDev */ + <&dma 19 0 0x2>, /* Logical - DevToMem */ + <&dma 19 0 0x0>, /* Logical - MemToDev */ + <&dma 18 0 0x2>, /* Logical - DevToMem */ + <&dma 18 0 0x0>, /* Logical - MemToDev */ + <&dma 17 0 0x2>, /* Logical - DevToMem */ + <&dma 17 0 0x0>, /* Logical - MemToDev */ + <&dma 16 0 0x2>, /* Logical - DevToMem */ + <&dma 16 0 0x0>, /* Logical - MemToDev */ + <&dma 39 0 0x2>, /* Logical - DevToMem */ + <&dma 39 0 0x0>; /* Logical - MemToDev */ + + dma-names = "iep_1_9", "oep_1_9", + "iep_2_10", "oep_2_10", + "iep_3_11", "oep_3_11", + "iep_4_12", "oep_4_12", + "iep_5_13", "oep_5_13", + "iep_6_14", "oep_6_14", + "iep_7_15", "oep_7_15", + "iep_8", "oep_8"; + + clocks = <&prcc_pclk 5 0>; + }; + + dma: dma-controller@801C0000 { + compatible = "stericsson,db8500-dma40", "stericsson,dma40"; + reg = <0x801C0000 0x1000 0x40010000 0x800>; + reg-names = "base", "lcpa"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + + #dma-cells = <3>; + memcpy-channels = <56 57 58 59 60>; + + clocks = <&prcmu_clk PRCMU_DMACLK>; + }; + + prcmu: prcmu@80157000 { + compatible = "stericsson,db8500-prcmu", "syscon"; + reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; + reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + prcmu-timer-4@80157450 { + compatible = "stericsson,db8500-prcmu-timer-4"; + reg = <0x80157450 0xC>; + }; + + thermal: thermal@801573c0 { + compatible = "stericsson,db8500-thermal"; + reg = <0x801573c0 0x40>; + interrupt-parent = <&prcmu>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; + #thermal-sensor-cells = <0>; + }; + + db8500-prcmu-regulators { + compatible = "stericsson,db8500-prcmu-regulator"; + + // DB8500_REGULATOR_VAPE + db8500_vape_reg: db8500_vape { + regulator-always-on; + }; + + // DB8500_REGULATOR_VARM + db8500_varm_reg: db8500_varm { + }; + + // DB8500_REGULATOR_VMODEM + db8500_vmodem_reg: db8500_vmodem { + }; + + // DB8500_REGULATOR_VPLL + db8500_vpll_reg: db8500_vpll { + }; + + // DB8500_REGULATOR_VSMPS1 + db8500_vsmps1_reg: db8500_vsmps1 { + }; + + // DB8500_REGULATOR_VSMPS2 + db8500_vsmps2_reg: db8500_vsmps2 { + }; + + // DB8500_REGULATOR_VSMPS3 + db8500_vsmps3_reg: db8500_vsmps3 { + }; + + // DB8500_REGULATOR_VRF1 + db8500_vrf1_reg: db8500_vrf1 { + }; + + // DB8500_REGULATOR_SWITCH_SVAMMDSP + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + }; + + // DB8500_REGULATOR_SWITCH_SVAMMDSPRET + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + }; + + // DB8500_REGULATOR_SWITCH_SVAPIPE + db8500_sva_pipe_reg: db8500_sva_pipe { + }; + + // DB8500_REGULATOR_SWITCH_SIAMMDSP + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + }; + + // DB8500_REGULATOR_SWITCH_SIAMMDSPRET + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + }; + + // DB8500_REGULATOR_SWITCH_SIAPIPE + db8500_sia_pipe_reg: db8500_sia_pipe { + }; + + // DB8500_REGULATOR_SWITCH_SGA + db8500_sga_reg: db8500_sga { + vin-supply = <&db8500_vape_reg>; + }; + + // DB8500_REGULATOR_SWITCH_B2R2_MCDE + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + vin-supply = <&db8500_vape_reg>; + }; + + // DB8500_REGULATOR_SWITCH_ESRAM12 + db8500_esram12_reg: db8500_esram12 { + }; + + // DB8500_REGULATOR_SWITCH_ESRAM12RET + db8500_esram12_ret_reg: db8500_esram12_ret { + }; + + // DB8500_REGULATOR_SWITCH_ESRAM34 + db8500_esram34_reg: db8500_esram34 { + }; + + // DB8500_REGULATOR_SWITCH_ESRAM34RET + db8500_esram34_ret_reg: db8500_esram34_ret { + }; + }; + }; + + i2c0: i2c@80004000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80004000 0x1000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + i2c1: i2c@80122000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80122000 0x1000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + i2c2: i2c@80128000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80128000 0x1000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + i2c3: i2c@80110000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80110000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + i2c4: i2c@8012a000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x8012a000 0x1000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + ssp0: spi@80002000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80002000 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ + <&dma 8 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + ssp1: spi@80003000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80003000 0x1000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ + <&dma 9 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi0: spi@8011a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x8011a000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ + <&dma 0 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi1: spi@80112000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80112000 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ + <&dma 35 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi2: spi@80111000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80111000 0x1000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ + <&dma 33 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi3: spi@80129000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80129000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ + <&dma 40 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + serial0: uart@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ + <&dma 13 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; + clock-names = "uart", "apb_pclk"; + + status = "disabled"; + }; + + serial1: uart@80121000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80121000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ + <&dma 12 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; + clock-names = "uart", "apb_pclk"; + + status = "disabled"; + }; + + serial2: uart@80007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80007000 0x1000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ + <&dma 11 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; + clock-names = "uart", "apb_pclk"; + + status = "disabled"; + }; + + sdi0_per1@80126000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80126000 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ + <&dma 29 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi1_per2@80118000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80118000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ + <&dma 32 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi2_per3@80005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80005000 0x1000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ + <&dma 28 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi3_per2@80119000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80119000 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ + <&dma 41 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi4_per2@80114000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ + <&dma 42 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi5_per3@80008000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80008000 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ + <&dma 43 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sound { + compatible = "stericsson,snd-soc-mop500"; + stericsson,cpu-dai = <&msp1 &msp3>; + }; + + msp0: msp@80123000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80123000 0x1000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + v-ape-supply = <&db8500_vape_reg>; + + dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; + clock-names = "msp", "apb_pclk"; + + status = "disabled"; + }; + + msp1: msp@80124000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80124000 0x1000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + v-ape-supply = <&db8500_vape_reg>; + + /* This DMA channel only exist on DB8500 v1 */ + dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "tx"; + + clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; + clock-names = "msp", "apb_pclk"; + + status = "disabled"; + }; + + // HDMI sound + msp2: msp@80117000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80117000 0x1000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + v-ape-supply = <&db8500_vape_reg>; + + dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev + HighPrio - Fixed */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; + clock-names = "msp", "apb_pclk"; + + status = "disabled"; + }; + + msp3: msp@80125000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80125000 0x1000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + v-ape-supply = <&db8500_vape_reg>; + + /* This DMA channel only exist on DB8500 v2 */ + dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ + dma-names = "rx"; + + clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; + clock-names = "msp", "apb_pclk"; + + status = "disabled"; + }; + + external-bus@50000000 { + compatible = "simple-bus"; + reg = <0x50000000 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x4000000>; + status = "disabled"; + }; + + gpu@a0300000 { + /* + * This block is referred to as "Smart Graphics Adapter SGA500" + * in documentation but is in practice a pretty straight-forward + * MALI-400 GPU block. + */ + compatible = "stericsson,db8500-mali", "arm,mali-400"; + reg = <0xa0300000 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "combined"; + clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; + clock-names = "bus", "core"; + mali-supply = <&db8500_sga_reg>; + power-domains = <&pm_domains DOMAIN_VAPE>; + }; + + mcde@a0350000 { + compatible = "ste,mcde"; + reg = <0xa0350000 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + epod-supply = <&db8500_b2r2_mcde_reg>; + clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ + <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ + <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ + clock-names = "mcde", "lcd", "hdmi"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + dsi0: dsi@a0351000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0351000 0x1000>; + clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi1: dsi@a0352000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0352000 0x1000>; + clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi2: dsi@a0353000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0353000 0x1000>; + /* This DSI port only has the Low Power / Energy Save clock */ + clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; + clock-names = "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cryp@a03cb000 { + compatible = "stericsson,ux500-cryp"; + reg = <0xa03cb000 0x1000>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + + v-ape-supply = <&db8500_vape_reg>; + clocks = <&prcc_pclk 6 1>; + }; + + hash@a03c2000 { + compatible = "stericsson,ux500-hash"; + reg = <0xa03c2000 0x1000>; + + v-ape-supply = <&db8500_vape_reg>; + clocks = <&prcc_pclk 6 2>; + }; + }; +}; diff --git a/arch/arm/dts/ste-ux500-samsung-stemmy.dts b/arch/arm/dts/ste-ux500-samsung-stemmy.dts new file mode 100644 index 0000000000..7e7f4c823a --- /dev/null +++ b/arch/arm/dts/ste-ux500-samsung-stemmy.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "ste-dbx5x0-u-boot.dtsi" +#include "ste-ab8500.dtsi" + +/ { + compatible = "samsung,stemmy", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + soc { + /* Debugging console UART */ + uart@80007000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 6c670cf9a3..41aea75213 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -1404,11 +1404,13 @@ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", + "eth-ck", "ethstp", "syscfg-clk"; clocks = <&rcc ETHMAC>, <&rcc ETHTX>, <&rcc ETHRX>, + <&rcc ETHCK_K>, <&rcc ETHSTP>, <&rcc SYSCFG>; st,syscon = <&syscfg 0x4>; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a83c70ece2..ddd9390df4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -123,6 +123,7 @@ #define CONFIG_SYS_PAGE_SIZE 0x10000 #define SRDS_MAX_LANES 4 +#define SRDS_BITS_PER_LANE 4 /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 @@ -252,6 +253,7 @@ #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) #define SRDS_MAX_LANES 4 +#define SRDS_BITS_PER_LANE 4 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 3c82e9921e..9a420dc30b 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -946,6 +946,10 @@ #define SNVS_LPCR_DPEN (0x20) #define SNVS_LPCR_SRTC_ENV (0x1) +#define SRC_BASE_ADDR CMC1_RBASE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index fc5b8f634d..d20703739f 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -7,7 +7,11 @@ #ifndef __ASM_ARM_DMA_MAPPING_H #define __ASM_ARM_DMA_MAPPING_H +#include <common.h> +#include <asm/cache.h> +#include <cpu_func.h> #include <linux/dma-direction.h> +#include <malloc.h> #define dma_mapping_error(x, y) 0 @@ -25,12 +29,27 @@ static inline void dma_free_coherent(void *addr) static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, enum dma_data_direction dir) { - return (unsigned long)vaddr; + unsigned long addr = (unsigned long)vaddr; + + len = ALIGN(len, ARCH_DMA_MINALIGN); + + if (dir == DMA_FROM_DEVICE) + invalidate_dcache_range(addr, addr + len); + else + flush_dcache_range(addr, addr + len); + + return addr; } static inline void dma_unmap_single(volatile void *vaddr, size_t len, - unsigned long paddr) + enum dma_data_direction dir) { + unsigned long addr = (unsigned long)vaddr; + + len = ALIGN(len, ARCH_DMA_MINALIGN); + + if (dir != DMA_TO_DEVICE) + invalidate_dcache_range(addr, addr + len); } #endif /* __ASM_ARM_DMA_MAPPING_H */ diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 6ff5f42424..acb7ea9a3e 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,9 +1,10 @@ #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ - !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \ - !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \ - !defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \ - !defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A) && \ - !defined(CONFIG_ARCH_ASPEED) + !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \ + !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ + !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ + !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ + !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ + !defined(CONFIG_ARCH_U8500) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> diff --git a/arch/arm/include/asm/handoff.h b/arch/arm/include/asm/handoff.h new file mode 100644 index 0000000000..0790d2ab1e --- /dev/null +++ b/arch/arm/include/asm/handoff.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Architecture-specific SPL handoff information for ARM + * + * Copyright 2019 Amarula Solutions, BV + * Written by Michael Trimarchi <michael@amarulasolutions.com> + */ + +#ifndef __asm_handoff_h +#define __asm_handoff_h + +/** + * struct arch_spl_handoff - architecture-specific handoff info + * + * @usable_ram_top: Value returned by board_get_usable_ram_top() in SPL + */ +struct arch_spl_handoff { + ulong usable_ram_top; +}; + +#endif diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index ca4b4c05ab..c423ac0058 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -47,7 +47,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(100000000U, 300, 9, 3, 0), }; -int fracpll_configure(enum pll_clocks pll, u32 freq) +static int fracpll_configure(enum pll_clocks pll, u32 freq) { int i; u32 tmp, div_val; @@ -268,7 +268,7 @@ u32 imx_get_uartclk(void) return 24000000U; } -u32 decode_intpll(enum clk_root_src intpll) +static u32 decode_intpll(enum clk_root_src intpll) { u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask; u32 main_div, pre_div, post_div, div; @@ -415,7 +415,7 @@ u32 decode_intpll(enum clk_root_src intpll) return lldiv(freq, pre_div * (1 << post_div) * div); } -u32 decode_fracpll(enum clk_root_src frac_pll) +static u32 decode_fracpll(enum clk_root_src frac_pll) { u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1; u32 main_div, pre_div, post_div, k; @@ -480,7 +480,7 @@ u32 decode_fracpll(enum clk_root_src frac_pll) 65536 * pre_div * (1 << post_div)); } -u32 get_root_src_clk(enum clk_root_src root_src) +static u32 get_root_src_clk(enum clk_root_src root_src) { switch (root_src) { case OSC_24M_CLK: @@ -524,7 +524,7 @@ u32 get_root_src_clk(enum clk_root_src root_src) return 0; } -u32 get_root_clk(enum clk_root_index clock_id) +static u32 get_root_clk(enum clk_root_index clock_id) { enum clk_root_src root_src; u32 post_podf, pre_podf, root_src_clk; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index f1a1021f10..9d91f9ab44 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -540,6 +540,18 @@ config TARGET_SKSIMX6 bool "sks-imx6" select SUPPORT_SPL +config TARGET_SOMLABS_VISIONSOM_6ULL + bool "visionsom-6ull" + select MX6ULL + select BOARD_LATE_INIT + select DM + select DM_ETH + select DM_GPIO + select DM_MMC + select DM_SERIAL + select DM_THERMAL + imply CMD_DM + config TARGET_TBS2910 bool "TBS2910 Matrix ARM mini PC" @@ -694,6 +706,7 @@ source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/sks-kinkel/sksimx6/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" +source "board/somlabs/visionsom-6ull/Kconfig" source "board/technexion/pico-imx6/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 7f8fdc7005..46484813d2 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -118,6 +118,7 @@ void init_wdog(void) disable_wdog(WDG2_RBASE); } +#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) #if defined(CONFIG_LDO_ENABLED_MODE) static void init_ldo_mode(void) { @@ -175,6 +176,7 @@ void s_init(void) #endif return; } +#endif #ifndef CONFIG_ULP_WATCHDOG void reset_cpu(ulong addr) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 5583241943..2e111bbf27 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -119,7 +119,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART config K3_SYSFW_IMAGE_SIZE_MAX int "Amount of memory dynamically allocated for loading SYSFW blob" depends on K3_LOAD_SYSFW - default 276000 + default 277000 help Amount of memory (in bytes) reserved through dynamic allocation at runtime for loading the combined System Firmware and configuration image diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index a78ffbb674..8d107b870b 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * K3: Architecture initialization + * AM6: SoC specific initialization * * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> @@ -19,6 +19,26 @@ #include <linux/soc/ti/ti_sci_protocol.h> #ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_K3_LOAD_SYSFW +#ifdef CONFIG_TI_SECURE_DEVICE +struct fwl_data main_cbass_fwls[] = { + { "MMCSD1_CFG", 2057, 1 }, + { "MMCSD0_CFG", 2058, 1 }, + { "USB3SS0_SLV0", 2176, 2 }, + { "PCIE0_SLV", 2336, 8 }, + { "PCIE1_SLV", 2337, 8 }, + { "PCIE0_CFG", 2688, 1 }, + { "PCIE1_CFG", 2689, 1 }, +}, mcu_cbass_fwls[] = { + { "MCU_ARMSS0_CORE0_SLV", 1024, 1 }, + { "MCU_ARMSS0_CORE1_SLV", 1028, 1 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_CPSW0", 1220, 1 }, +}; +#endif +#endif + static void mmr_unlock(u32 base, u32 partition) { /* Translate the base address */ @@ -109,6 +129,12 @@ void board_init_f(ulong dummy) * output. */ k3_sysfw_loader(preloader_console_init); + + /* Disable ROM configured firewalls right after loading sysfw */ +#ifdef CONFIG_TI_SECURE_DEVICE + remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls)); + remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls)); +#endif #else /* Prepare console output */ preloader_console_init(); diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 4e35a13156..2f82edb970 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -175,8 +175,8 @@ int fdt_disable_node(void *blob, char *node_path) offs = fdt_path_offset(blob, node_path); if (offs < 0) { - debug("Node %s not found.\n", node_path); - return 0; + printf("Node %s not found.\n", node_path); + return offs; } ret = fdt_setprop_string(blob, offs, "status", "disabled"); if (ret < 0) { @@ -270,3 +270,33 @@ void disable_linefill_optimization(void) asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); } #endif + +void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) +{ + struct ti_sci_msg_fwl_region region; + struct ti_sci_fwl_ops *fwl_ops; + struct ti_sci_handle *ti_sci; + size_t i, j; + + ti_sci = get_ti_sci_handle(); + fwl_ops = &ti_sci->ops.fwl_ops; + for (i = 0; i < fwl_data_size; i++) { + for (j = 0; j < fwl_data[i].regions; j++) { + region.fwl_id = fwl_data[i].fwl_id; + region.region = j; + region.n_permission_regs = 3; + + fwl_ops->get_fwl_region(ti_sci, ®ion); + + if (region.control != 0) { + pr_debug("Attempting to disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data[i].name); + region.control = 0; + + if (fwl_ops->set_fwl_region(ti_sci, ®ion)) + pr_err("Could not disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data[i].name); + } + } + } +} diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 35d1609cdc..d8b34fe060 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -14,6 +14,13 @@ #define REV_PG1_0 0 #define REV_PG2_0 1 +struct fwl_data { + const char *name; + u16 fwl_id; + u16 regions; +}; + void setup_k3_mpu_regions(void); int early_console_init(void); void disable_linefill_optimization(void); +void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index 8d429772b5..ead136ed63 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -46,4 +46,7 @@ #define CTRLMMR_LOCK_KICK1 0x0100c #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a +/* MCU SCRATCHPAD usage */ +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE + #endif /* __ASM_ARCH_J721E_HARDWARE_H */ diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 4758739266..f7f7398081 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -20,6 +20,47 @@ #include <dm/pinctrl.h> #ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_K3_LOAD_SYSFW +#ifdef CONFIG_TI_SECURE_DEVICE +struct fwl_data cbass_hc_cfg0_fwls[] = { + { "PCIE0_CFG", 2560, 8 }, + { "PCIE1_CFG", 2561, 8 }, + { "USB3SS0_CORE", 2568, 4 }, + { "USB3SS1_CORE", 2570, 4 }, + { "EMMC8SS0_CFG", 2576, 4 }, + { "UFS_HCI0_CFG", 2580, 4 }, + { "SERDES0", 2584, 1 }, + { "SERDES1", 2585, 1 }, +}, cbass_hc0_fwls[] = { + { "PCIE0_HP", 2528, 24 }, + { "PCIE0_LP", 2529, 24 }, + { "PCIE1_HP", 2530, 24 }, + { "PCIE1_LP", 2531, 24 }, +}, cbass_rc_cfg0_fwls[] = { + { "EMMCSD4SS0_CFG", 2380, 4 }, +}, cbass_rc0_fwls[] = { + { "GPMC0", 2310, 8 }, +}, infra_cbass0_fwls[] = { + { "PLL_MMR0", 8, 26 }, + { "CTRL_MMR0", 9, 16 }, +}, mcu_cbass0_fwls[] = { + { "MCU_R5FSS0_CORE0", 1024, 4 }, + { "MCU_R5FSS0_CORE0_CFG", 1025, 2 }, + { "MCU_R5FSS0_CORE1", 1028, 4 }, + { "MCU_FSS0_CFG", 1032, 12 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_PSROM49152X32", 1048, 1 }, + { "MCU_MSRAM128KX64", 1050, 8 }, + { "MCU_CTRL_MMR0", 1200, 8 }, + { "MCU_PLL_MMR0", 1201, 3 }, + { "MCU_CPSW0", 1220, 2 }, +}, wkup_cbass0_fwls[] = { + { "WKUP_CTRL_MMR0", 131, 16 }, +}; +#endif +#endif + static void mmr_unlock(u32 base, u32 partition) { /* Translate the base address */ @@ -114,11 +155,25 @@ void board_init_f(ulong dummy) * output. */ k3_sysfw_loader(preloader_console_init); + + /* Disable ROM configured firewalls right after loading sysfw */ +#ifdef CONFIG_TI_SECURE_DEVICE + remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls)); + remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls)); + remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls)); + remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls)); + remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls)); + remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls)); + remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls)); +#endif #else /* Prepare console output */ preloader_console_init(); #endif + /* Perform EEPROM-based board detection */ + do_board_detect(); + #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs), &dev); diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 6934e88a96..0d77d98359 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <cpu_func.h> #include <dm.h> #include <hang.h> #include <linux/soc/ti/ti_sci_protocol.h> @@ -23,8 +24,14 @@ void board_fit_image_post_process(void **p_image, size_t *p_size) int ret; image_addr = (uintptr_t)*p_image; + image_size = *p_size; debug("Authenticating image at address 0x%016llx\n", image_addr); + debug("Authenticating image of size %d bytes\n", image_size); + + flush_dcache_range((unsigned long)image_addr, + ALIGN((unsigned long)image_addr + image_size, + ARCH_DMA_MINALIGN)); /* Authenticate image */ ret = proc_ops->proc_auth_boot_image(ti_sci, &image_addr, &image_size); @@ -33,6 +40,11 @@ void board_fit_image_post_process(void **p_image, size_t *p_size) hang(); } + if (image_size) + invalidate_dcache_range((unsigned long)image_addr, + ALIGN((unsigned long)image_addr + + image_size, ARCH_DMA_MINALIGN)); + /* * The image_size returned may be 0 when the authentication process has * moved the image. When this happens no further processing on the diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index fdd39685b7..bc5eaa5a76 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -91,6 +91,7 @@ choice config TARGET_CLEARFOG bool "Support ClearFog" select 88F6820 + select BOARD_LATE_INIT config TARGET_HELIOS4 bool "Support Helios4" diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index 32cdf63e3d..f2cd496607 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -77,7 +77,7 @@ const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = { {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ {25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */ {30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */ - {100, 3, 1, -1, -1, -1, -1}, /* OPP TB */ + {100, 2, 1, -1, -1, -1, -1}, /* OPP TB */ {125, 2, 1, -1, -1, -1, -1} /* OPP NT */ }, { /* 25 MHz */ diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index c4a41db92a..fa4e27063c 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -418,6 +418,7 @@ void enable_basic_clocks(void) (*prcm)->cm_l3init_hsmmc2_clkctrl, (*prcm)->cm_l4per_gptimer2_clkctrl, (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart1_clkctrl, (*prcm)->cm_l4per_uart3_clkctrl, (*prcm)->cm_l4per_i2c1_clkctrl, #ifdef CONFIG_DRIVER_TI_CPSW diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index ae28f6e206..137178aa45 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -33,8 +33,8 @@ config SYS_MALLOC_LEN config ENV_SIZE default 0x2000 -config TARGET_STM32MP1 - bool "Support stm32mp1xx" +config STM32MP15x + bool "Support STMicroelectronics STM32MP15x Soc" select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED select CPU_V7A select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED @@ -45,19 +45,35 @@ config TARGET_STM32MP1 select STM32_RESET select STM32_SERIAL select SYS_ARCH_TIMER + imply SYSRESET_PSCI if STM32MP1_TRUSTED + imply SYSRESET_SYSCON if !STM32MP1_TRUSTED + help + support of STMicroelectronics SOC STM32MP15x family + STM32MP157, STM32MP153 or STM32MP151 + STMicroelectronics MPU with core ARMv7 + dual core A7 for STM32MP157/3, monocore for STM32MP151 + target all the STMicroelectronics board with SOC STM32MP1 family + +choice + prompt "STM32MP15x board select" + optional + +config TARGET_ST_STM32MP15x + bool "STMicroelectronics STM32MP15x boards" + select STM32MP15x imply BOOTCOUNT_LIMIT imply CMD_BOOTCOUNT imply CMD_CLS if CMD_BMP imply DISABLE_CONSOLE imply PRE_CONSOLE_BUFFER imply SILENT_CONSOLE - imply SYSRESET_PSCI if STM32MP1_TRUSTED - imply SYSRESET_SYSCON if !STM32MP1_TRUSTED help - target STMicroelectronics SOC STM32MP1 family - STM32MP157, STM32MP153 or STM32MP151 - STMicroelectronics MPU with core ARMv7 - dual core A7 for STM32MP157/3, monocore for STM32MP151 + target the STMicroelectronics board with SOC STM32MP15x + managed by board/st/stm32mp1: + Evalulation board (EV1) or Discovery board (DK1 and DK2). + The difference between board are managed with devicetree + +endchoice config STM32MP1_TRUSTED bool "Support trusted boot with TF-A" @@ -80,12 +96,7 @@ config STM32MP1_OPTEE OP-TEE monitor provides ST SMC to access to secure resources config SYS_TEXT_BASE - prompt "U-Boot base address" default 0xC0100000 - help - configure the U-Boot base address - when DDR driver is used: - DDR + 1MB (0xC0100000) config NR_DRAM_BANKS default 1 diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 6a71465494..de7891b5c4 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -456,7 +456,7 @@ static void setup_boot_mode(void) * If there is no MAC address in the environment, then it will be initialized * (silently) from the value in the OTP. */ -static int setup_mac_address(void) +__weak int setup_mac_address(void) { #if defined(CONFIG_NET) int ret; diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 99eefabf6e..47e57922d1 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -30,3 +30,5 @@ u32 get_cpu_package(void); /* return boot mode */ u32 get_bootmode(void); + +int setup_mac_address(void); diff --git a/arch/arm/mach-u8500/Kconfig b/arch/arm/mach-u8500/Kconfig new file mode 100644 index 0000000000..7478deb25f --- /dev/null +++ b/arch/arm/mach-u8500/Kconfig @@ -0,0 +1,27 @@ +if ARCH_U8500 + +config SYS_SOC + default "u8500" + +choice + prompt "U8500 board selection" + +config TARGET_STEMMY + bool "Samsung (stemmy) board" + help + The Samsung "stemmy" board supports Samsung smartphones released with + the ST-Ericsson NovaThor U8500 SoC, e.g. + + - Samsung Galaxy S III mini (GT-I8190) "golden" + - Samsung Galaxy S Advance (GT-I9070) "janice" + - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" + + and likely others as well (untested). + + See board/ste/stemmy/README for details. + +endchoice + +source "board/ste/stemmy/Kconfig" + +endif diff --git a/arch/arm/mach-u8500/Makefile b/arch/arm/mach-u8500/Makefile new file mode 100644 index 0000000000..0a53cbd9ac --- /dev/null +++ b/arch/arm/mach-u8500/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-y += cache.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c new file mode 100644 index 0000000000..3d96d09f31 --- /dev/null +++ b/arch/arm/mach-u8500/cache.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Stephan Gerhold <stephan@gerhold.net> + */ + +#include <common.h> +#include <cpu_func.h> +#include <asm/armv7.h> +#include <asm/pl310.h> + +#define PL310_WAY_MASK 0xff + +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#ifdef CONFIG_SYS_L2_PL310 +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + + /* + * Linux expects the L2 cache to be turned off by the bootloader. + * Otherwise, it fails very early (shortly after decompressing the kernel). + * + * On U8500, the L2 cache can be only turned on/off from the secure world. + * Instead, prevent usage of the L2 cache by locking all ways. + * The kernel needs to unlock them to make the L2 cache work again. + */ + writel(PL310_WAY_MASK, &pl310->pl310_lockdown_dbase); + writel(PL310_WAY_MASK, &pl310->pl310_lockdown_ibase); +} +#endif diff --git a/arch/arm/mach-u8500/cpuinfo.c b/arch/arm/mach-u8500/cpuinfo.c new file mode 100644 index 0000000000..20f5ff3398 --- /dev/null +++ b/arch/arm/mach-u8500/cpuinfo.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Stephan Gerhold <stephan@gerhold.net> + */ + +#include <common.h> +#include <asm/io.h> + +#define U8500_BOOTROM_BASE 0x90000000 +#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4) + +int print_cpuinfo(void) +{ + /* Convert ASIC ID to display string, e.g. 0x8520A0 => DB8520 V1.0 */ + u32 asicid = readl(U8500_ASIC_ID_LOC_V2); + u32 cpu = (asicid >> 8) & 0xffff; + u32 rev = asicid & 0xff; + + /* 0xA0 => 0x10 (V1.0) */ + if (rev >= 0xa0) + rev -= 0x90; + + printf("CPU: ST-Ericsson DB%x V%d.%d\n", cpu, rev >> 4, rev & 0xf); + return 0; +} diff --git a/arch/nds32/include/asm/dma-mapping.h b/arch/nds32/include/asm/dma-mapping.h index e6808dc840..c8876ceadd 100644 --- a/arch/nds32/include/asm/dma-mapping.h +++ b/arch/nds32/include/asm/dma-mapping.h @@ -6,7 +6,11 @@ #ifndef __ASM_NDS_DMA_MAPPING_H #define __ASM_NDS_DMA_MAPPING_H +#include <common.h> +#include <asm/cache.h> +#include <cpu_func.h> #include <linux/dma-direction.h> +#include <malloc.h> static void *dma_alloc_coherent(size_t len, unsigned long *handle) { @@ -17,12 +21,27 @@ static void *dma_alloc_coherent(size_t len, unsigned long *handle) static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, enum dma_data_direction dir) { - return (unsigned long)vaddr; + unsigned long addr = (unsigned long)vaddr; + + len = ALIGN(len, ARCH_DMA_MINALIGN); + + if (dir == DMA_FROM_DEVICE) + invalidate_dcache_range(addr, addr + len); + else + flush_dcache_range(addr, addr + len); + + return addr; } static inline void dma_unmap_single(volatile void *vaddr, size_t len, - unsigned long paddr) + enum dma_data_direction dir) { + unsigned long addr = (unsigned long)vaddr; + + len = ALIGN(len, ARCH_DMA_MINALIGN); + + if (dir != DMA_TO_DEVICE) + invalidate_dcache_range(addr, addr + len); } #endif /* __ASM_NDS_DMA_MAPPING_H */ diff --git a/arch/riscv/include/asm/dma-mapping.h b/arch/riscv/include/asm/dma-mapping.h index 3d930c90ec..6cc3946959 100644 --- a/arch/riscv/include/asm/dma-mapping.h +++ b/arch/riscv/include/asm/dma-mapping.h @@ -9,7 +9,11 @@ #ifndef __ASM_RISCV_DMA_MAPPING_H #define __ASM_RISCV_DMA_MAPPING_H +#include <common.h> +#include <asm/cache.h> +#include <cpu_func.h> #include <linux/dma-direction.h> +#include <malloc.h> #define dma_mapping_error(x, y) 0 @@ -27,12 +31,27 @@ static inline void dma_free_coherent(void *addr) static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, enum dma_data_direction dir) { - return (unsigned long)vaddr; + unsigned long addr = (unsigned long)vaddr; + + len = ALIGN(len, ARCH_DMA_MINALIGN); + + if (dir == DMA_FROM_DEVICE) + invalidate_dcache_range(addr, addr + len); + else + flush_dcache_range(addr, addr + len); + + return addr; } static inline void dma_unmap_single(volatile void *vaddr, size_t len, - unsigned long paddr) + enum dma_data_direction dir) { + unsigned long addr = (unsigned long)vaddr; + + len = ALIGN(len, ARCH_DMA_MINALIGN); + + if (dir != DMA_TO_DEVICE) + invalidate_dcache_range(addr, addr + len); } #endif /* __ASM_RISCV_DMA_MAPPING_H */ diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h index b353ff0bef..900b99b8a6 100644 --- a/arch/x86/include/asm/dma-mapping.h +++ b/arch/x86/include/asm/dma-mapping.h @@ -7,7 +7,11 @@ #ifndef __ASM_X86_DMA_MAPPING_H #define __ASM_X86_DMA_MAPPING_H +#include <common.h> +#include <asm/cache.h> +#include <cpu_func.h> #include <linux/dma-direction.h> +#include <malloc.h> #define dma_mapping_error(x, y) 0 @@ -25,12 +29,27 @@ static inline void dma_free_coherent(void *addr) static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, enum dma_data_direction dir) { - return (unsigned long)vaddr; + unsigned long addr = (unsigned long)vaddr; + + len = ALIGN(len, ARCH_DMA_MINALIGN); + + if (dir == DMA_FROM_DEVICE) + invalidate_dcache_range(addr, addr + len); + else + flush_dcache_range(addr, addr + len); + + return addr; } static inline void dma_unmap_single(volatile void *vaddr, size_t len, - unsigned long paddr) + enum dma_data_direction dir) { + unsigned long addr = (unsigned long)vaddr; + + len = ALIGN(len, ARCH_DMA_MINALIGN); + + if (dir != DMA_TO_DEVICE) + invalidate_dcache_range(addr, addr + len); } #endif /* __ASM_X86_DMA_MAPPING_H */ |