diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/config.mk | 6 | ||||
| -rw-r--r-- | arch/mips/Kconfig | 10 | ||||
| -rw-r--r-- | arch/mips/Makefile | 1 | ||||
| -rw-r--r-- | arch/mips/config.mk | 2 | ||||
| -rw-r--r-- | arch/mips/cpu/cpu.c | 2 | ||||
| -rw-r--r-- | arch/mips/cpu/start.S | 19 | ||||
| -rw-r--r-- | arch/mips/dts/Makefile | 3 | ||||
| -rw-r--r-- | arch/mips/dts/brcm,bcm63268.dtsi | 143 | ||||
| -rw-r--r-- | arch/mips/dts/brcm,bcm6328.dtsi | 127 | ||||
| -rw-r--r-- | arch/mips/dts/brcm,bcm6358.dtsi | 140 | ||||
| -rw-r--r-- | arch/mips/dts/comtrend,ar-5387un.dts | 57 | ||||
| -rw-r--r-- | arch/mips/dts/comtrend,vr-3032u.dts | 70 | ||||
| -rw-r--r-- | arch/mips/dts/huawei,hg556a.dts | 104 | ||||
| -rw-r--r-- | arch/mips/dts/sfr,nb4-ser.dts | 93 | ||||
| -rw-r--r-- | arch/mips/mach-bmips/Kconfig | 88 | ||||
| -rw-r--r-- | arch/mips/mach-bmips/Makefile | 5 | ||||
| -rw-r--r-- | arch/mips/mach-bmips/dram.c | 37 | ||||
| -rw-r--r-- | arch/mips/mach-bmips/include/ioremap.h | 45 |
18 files changed, 952 insertions, 0 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 2143633fe4..a5eebb95e5 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -30,6 +30,12 @@ PLATFORM_RELFLAGS += $(LLVM_RELFLAGS) PLATFORM_CPPFLAGS += -D__ARM__ +ifdef CONFIG_ARM64 +PLATFORM_ELFFLAGS += -B aarch64 -O elf64-littleaarch64 +else +PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm +endif + # Choose between ARM/Thumb instruction sets ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d97930e577..c97ea4156b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -75,6 +75,15 @@ config ARCH_ATH79 select OF_CONTROL select DM +config ARCH_BMIPS + bool "Support BMIPS SoCs" + select OF_CONTROL + select DM + select CLK + select CPU + select RAM + select SYSRESET + config MACH_PIC32 bool "Support Microchip PIC32" select OF_CONTROL @@ -123,6 +132,7 @@ source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" if MIPS diff --git a/arch/mips/Makefile b/arch/mips/Makefile index efe7e44236..c30d4ef39d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,6 +15,7 @@ libs-y += arch/mips/lib/ machine-$(CONFIG_SOC_AU1X00) += au1x00 machine-$(CONFIG_ARCH_ATH79) += ath79 +machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index dcd346002c..2c72c1553d 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -36,6 +36,8 @@ OBJCOPYFLAGS += -O $(64bit-bfd) endif PLATFORM_CPPFLAGS += -D__MIPS__ +PLATFORM_ELFENTRY = "__start" +PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS) # # From Linux arch/mips/Makefile diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c index 1b919ed822..55e6498b65 100644 --- a/arch/mips/cpu/cpu.c +++ b/arch/mips/cpu/cpu.c @@ -12,6 +12,7 @@ #include <asm/mipsregs.h> #include <asm/reboot.h> +#ifndef CONFIG_SYSRESET void __weak _machine_restart(void) { fprintf(stderr, "*** reset failed ***\n"); @@ -26,6 +27,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#endif void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) { diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6740fdf9ed..d01ee9f9bd 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -151,8 +151,13 @@ reset: mfc0 t0, CP0_GLOBALNUMBER #endif +#ifdef CONFIG_ARCH_BMIPS +1: mfc0 t0, CP0_DIAGNOSTIC, 3 + and t0, t0, (1 << 31) +#else 1: mfc0 t0, CP0_EBASE and t0, t0, EBASE_CPUNUM +#endif /* Hang if this isn't the first CPU in the system */ 2: beqz t0, 4f @@ -237,6 +242,13 @@ wr_done: #ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM /* Set up initial stack and global data */ setup_stack_gd + +# ifdef CONFIG_DEBUG_UART + /* Earliest point to set up debug uart */ + PTR_LA t9, debug_uart_init + jalr t9 + nop +# endif #endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT @@ -263,6 +275,13 @@ wr_done: #ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM /* Set up initial stack and global data */ setup_stack_gd + +# ifdef CONFIG_DEBUG_UART + /* Earliest point to set up debug uart */ + PTR_LA t9, debug_uart_init + jalr t9 + nop +# endif #endif move a0, zero # a0 <-- boot_flags = 0 diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 30fcc2b91e..4c02c48c11 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -8,6 +8,9 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb +dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb +dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb +dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi new file mode 100644 index 0000000000..3d0f8e0ea1 --- /dev/null +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/bcm63268-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm63268-power-domain.h> +#include <dt-bindings/reset/bcm63268-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63268"; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + + timer_clk: timer-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x100000ac 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + gpio1: gpio-controller@100000c0 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c0 0x4>, <0x100000c8 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <20>; + + status = "disabled"; + }; + + gpio0: gpio-controller@100000c4 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c4 0x4>, <0x100000cc 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000180 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000180 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@100001a0 { + compatible = "brcm,bcm6345-uart"; + reg = <0x100001a0 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + periph_pwr: power-controller@1000184c { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x1000184c 0x4>; + #power-domain-cells = <1>; + }; + + leds: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi new file mode 100644 index 0000000000..4adc83fcb4 --- /dev/null +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/bcm6328-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm6328-power-domain.h> +#include <dt-bindings/reset/bcm6328-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6328"; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + pll_cntl: syscon@10000068 { + compatible = "syscon"; + reg = <0x10000068 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + gpio: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + leds: led-controller@10000800 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10000800 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + periph_pwr: power-controller@10001848 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x10001848 0x4>; + #power-domain-cells = <1>; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi new file mode 100644 index 0000000000..df75988c82 --- /dev/null +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/bcm6358-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/bcm6358-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6358"; + + cpus { + reg = <0xfffe0000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0xfffe0004 0x4>; + #clock-cells = <1>; + }; + }; + + pflash: nor@1e000000 { + compatible = "cfi-flash"; + reg = <0x1e000000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@fffe0008 { + compatible = "syscon"; + reg = <0xfffe0008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@fffe0034 { + compatible = "brcm,bcm6345-reset"; + reg = <0xfffe0034 0x4>; + #reset-cells = <1>; + }; + + gpio1: gpio-controller@fffe0080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + + status = "disabled"; + }; + + gpio0: gpio-controller@fffe0084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + leds: led-controller@fffe00d0 { + compatible = "brcm,bcm6358-leds"; + reg = <0xfffe00d0 0x8>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart0: serial@fffe0100 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@fffe0120 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + memory-controller@fffe1200 { + compatible = "brcm,bcm6358-mc"; + reg = <0xfffe1200 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts new file mode 100644 index 0000000000..73f2b49b76 --- /dev/null +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6328.dtsi" + +/ { + model = "Comtrend AR-5387un"; + compatible = "comtrend,ar5387-un", "brcm,bcm6328"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&leds { + status = "okay"; + + led@1 { + reg = <1>; + label = "AR-5387un:red:inet"; + }; + + led@4 { + reg = <4>; + label = "AR-5387un:red:power"; + }; + + led@7 { + reg = <7>; + label = "AR-5387un:green:inet"; + }; + + led@8 { + reg = <8>; + label = "AR-5387un:green:power"; + }; + + led@11 { + reg = <11>; + active-low; + label = "AR-5387un:green:dsl"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts new file mode 100644 index 0000000000..54e738c821 --- /dev/null +++ b/arch/mips/dts/comtrend,vr-3032u.dts @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm63268.dtsi" + +/ { + model = "Comtrend VR-3032u"; + compatible = "comtrend,vr-3032u", "brcm,bcm63268"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&leds { + status = "okay"; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + + led@2 { + reg = <2>; + active-low; + label = "VR-3032u:red:inet"; + }; + + led@3 { + reg = <3>; + active-low; + label = "VR-3032u:green:dsl"; + }; + + led@4 { + reg = <4>; + active-low; + label = "VR-3032u:green:usb"; + }; + + led@7 { + reg = <7>; + active-low; + label = "VR-3032u:green:wps"; + }; + + led@8 { + reg = <8>; + active-low; + label = "VR-3032u:green:inet"; + }; + + led@20 { + reg = <20>; + active-low; + label = "VR-3032u:green:power"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts new file mode 100644 index 0000000000..31c7d7ed5c --- /dev/null +++ b/arch/mips/dts/huawei,hg556a.dts @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6358.dtsi" + +/ { + model = "Huawei EchoLife HG556a"; + compatible = "huawei,hg556a", "brcm,bcm6358"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + message_red { + label = "HG556a:red:message"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + hspa_red { + label = "HG556a:red:hspa"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + dsl_red { + label = "HG556a:red:dsl"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + power_red { + label = "HG556a:red:power"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + + all_red { + label = "HG556a:red:all"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + + lan1_green { + label = "HG556a:green:lan1"; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + + lan1_red { + label = "HG556a:red:lan1"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + lan2_green { + label = "HG556a:green:lan2"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + lan2_red { + label = "HG556a:red:lan2"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + lan3_green { + label = "HG556a:green:lan3"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + lan3_red { + label = "HG556a:red:lan3"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + + lan4_green { + label = "HG556a:green:lan4"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + + lan4_red { + label = "HG556a:red:lan4"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts new file mode 100644 index 0000000000..f2092e9f99 --- /dev/null +++ b/arch/mips/dts/sfr,nb4-ser.dts @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6358.dtsi" + +/ { + model = "SFR NeufBox 4 (Sercomm) Board"; + compatible = "sfr,nb4-ser", "brcm,bcm6358"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + traffic_white { + label = "NB4-SER:white:traffic"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + service_blue { + label = "NB4-SER:blue:service"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + }; + + wifi_white { + label = "NB4-SER:white:wifi"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + service_red { + label = "NB4-SER:red:service"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + + service_green { + label = "NB4-SER:green:service"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,clk-div = <1>; + + led@0 { + reg = <0>; + active-low; + label = "NB4-SER:white:alarm"; + }; + + led@2 { + reg = <2>; + active-low; + label = "NB4-SER:white:tv"; + }; + + led@3 { + reg = <3>; + active-low; + label = "NB4-SER:white:tel"; + }; + + led@4 { + reg = <4>; + active-low; + label = "NB4-SER:white:adsl"; + }; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig new file mode 100644 index 0000000000..d1684486a8 --- /dev/null +++ b/arch/mips/mach-bmips/Kconfig @@ -0,0 +1,88 @@ +menu "Broadcom MIPS platforms" + depends on ARCH_BMIPS + +config SYS_SOC + default "bcm6328" if SOC_BMIPS_BCM6328 + default "bcm6358" if SOC_BMIPS_BCM6358 + default "bcm63268" if SOC_BMIPS_BCM63268 + +choice + prompt "Broadcom MIPS SoC select" + +config SOC_BMIPS_BCM6328 + bool "BMIPS BCM6328 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6328 family including BCM63281 and BCM63283. + +config SOC_BMIPS_BCM6358 + bool "BMIPS BCM6358 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6358 family including BCM6358 and BCM6359. + +config SOC_BMIPS_BCM63268 + bool "BMIPS BCM63268 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM63268 family including BCM63168, BCM63169, + BCM63268 and BCM63269. + +endchoice + +choice + prompt "Board select" + +config BOARD_COMTREND_AR5387UN + bool "Comtrend AR-5387un" + depends on SOC_BMIPS_BCM6328 + select BMIPS_SUPPORTS_BOOT_RAM + +config BOARD_COMTREND_VR3032U + bool "Comtrend VR-3032u board" + depends on SOC_BMIPS_BCM63268 + select BMIPS_SUPPORTS_BOOT_RAM + +config BOARD_HUAWEI_HG556A + bool "Huawei EchoLife HG556a" + depends on SOC_BMIPS_BCM6358 + select BMIPS_SUPPORTS_BOOT_RAM + +endchoice + +choice + prompt "Boot mode" + +config BMIPS_BOOT_RAM + bool "RAM boot" + depends on BMIPS_SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a RAM address. It can be used + for booting from CFE via TFTP using an ELF image, but it can also be + booted from RAM by other bootloaders using a BIN image. + +endchoice + +config BMIPS_SUPPORTS_BOOT_RAM + bool + +source "board/comtrend/ar5387un/Kconfig" +source "board/comtrend/vr3032u/Kconfig" +source "board/huawei/hg556a/Kconfig" + +endmenu diff --git a/arch/mips/mach-bmips/Makefile b/arch/mips/mach-bmips/Makefile new file mode 100644 index 0000000000..f432accb82 --- /dev/null +++ b/arch/mips/mach-bmips/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += dram.o diff --git a/arch/mips/mach-bmips/dram.c b/arch/mips/mach-bmips/dram.c new file mode 100644 index 0000000000..b19b28a910 --- /dev/null +++ b/arch/mips/mach-bmips/dram.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2016 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ram.h> +#include <dm.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int err; + + err = uclass_get_device(UCLASS_RAM, 0, &dev); + if (err) { + debug("DRAM init failed: %d\n", err); + return 0; + } + + err = ram_get_info(dev, &ram); + if (err) { + debug("Cannot get DRAM size: %d\n", err); + return 0; + } + + debug("SDRAM base=%zx, size=%x\n", ram.base, ram.size); + + gd->ram_size = ram.size; + + return 0; +} diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h new file mode 100644 index 0000000000..404690e4db --- /dev/null +++ b/arch/mips/mach-bmips/include/ioremap.h @@ -0,0 +1,45 @@ +/* + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_BMIPS_IOREMAP_H +#define __ASM_MACH_BMIPS_IOREMAP_H + +#include <linux/types.h> + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, + phys_addr_t size) +{ + return phys_addr; +} + +static inline int is_bmips_internal_registers(phys_addr_t offset) +{ +#if defined(CONFIG_SOC_BMIPS_BCM6358) + if (offset >= 0xfffe0000) + return 1; +#endif + + return 0; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (is_bmips_internal_registers(offset)) + return (void __iomem *)offset; + + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_bmips_internal_registers((unsigned long)addr); +} + +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT + +#endif /* __ASM_MACH_BMIPS_IOREMAP_H */ |