diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/r8a7792-blanche-u-boot.dts | 4 | ||||
| -rw-r--r-- | arch/arm/dts/r8a7792.dtsi | 17 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/spl_a10.c | 32 |
6 files changed, 60 insertions, 0 deletions
diff --git a/arch/arm/dts/r8a7792-blanche-u-boot.dts b/arch/arm/dts/r8a7792-blanche-u-boot.dts index 3555663d64..30b27040f5 100644 --- a/arch/arm/dts/r8a7792-blanche-u-boot.dts +++ b/arch/arm/dts/r8a7792-blanche-u-boot.dts @@ -8,6 +8,10 @@ #include "r8a7792-blanche.dts" #include "r8a7792-u-boot.dtsi" +&iic3 { + status = "okay"; +}; + &scif0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi index 8e9eb4b704..6fd80e3541 100644 --- a/arch/arm/dts/r8a7792.dtsi +++ b/arch/arm/dts/r8a7792.dtsi @@ -444,6 +444,23 @@ status = "disabled"; }; + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7792", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 1908be4b8b..debeb8b239 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -37,3 +37,6 @@ u-boot,dm-pre-reloc; }; +&qspi { + status = "okay"; +}; diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index 929c413e03..b947cc0729 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -47,4 +47,6 @@ #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 #define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500 +#define SOCFPGA_PHYS_OCRAM_SIZE 0x40000 + #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index 2725e9fcc3..da966fb458 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h @@ -59,4 +59,6 @@ #define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 #define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_PHYS_OCRAM_SIZE 0x10000 + #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index d9ef851054..b10be33268 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -33,6 +33,38 @@ DECLARE_GLOBAL_DATA_PTR; +#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */ +#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + SOCFPGA_PHYS_OCRAM_SIZE - \ + BOOTROM_SHARED_MEM_SIZE) +#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438) +static u32 rst_mgr_status __section(.data); + +/* + * Bootrom will clear the status register in reset manager and stores the + * reset status value in shared memory. Bootrom stores shared data at last + * 2KB of onchip RAM. + * This function save reset status provided by BootROM to rst_mgr_status. + * More information about reset status register value can be found in reset + * manager register description. + * When running in debugger without Bootrom, r0 to r3 are random values. + * So, skip save the value when r0 is not BootROM shared data address. + * + * r0 - Contains the pointer to the shared memory block. The shared + * memory block is located in the top 2 KB of on-chip RAM. + * r1 - contains the length of the shared memory. + * r2 - unused and set to 0x0. + * r3 - points to the version block. + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + if (r0 == BOOTROM_SHARED_MEM_ADDR) + rst_mgr_status = readl(RST_STATUS_SHARED_ADDR); + + save_boot_params_ret(); +} + u32 spl_boot_device(void) { const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO); |