diff options
Diffstat (limited to 'arch')
23 files changed, 1283 insertions, 168 deletions
diff --git a/arch/arm/dts/armada-38x-controlcenterdc.dts b/arch/arm/dts/armada-38x-controlcenterdc.dts index 896f8ae66d..2cc996876a 100644 --- a/arch/arm/dts/armada-38x-controlcenterdc.dts +++ b/arch/arm/dts/armada-38x-controlcenterdc.dts @@ -92,14 +92,14 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q016a"; + compatible = "n25q016a", "spi-flash"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <108000000>; }; spi-flash@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128a11"; + compatible = "n25q128a11", "spi-flash"; reg = <1>; /* Chip select 1 */ spi-max-frequency = <108000000>; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi index 738ed689ff..4ee2e79514 100644 --- a/arch/arm/dts/meson-gx.dtsi +++ b/arch/arm/dts/meson-gx.dtsi @@ -211,32 +211,39 @@ #size-cells = <2>; ranges; - cbus: cbus@c1100000 { + cbus: bus@c1100000 { compatible = "simple-bus"; reg = <0x0 0xc1100000 0x0 0x100000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; + gpio_intc: interrupt-controller@9880 { + compatible = "amlogic,meson-gpio-intc"; + reg = <0x0 0x9880 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + status = "disabled"; + }; + reset: reset-controller@4404 { compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; - reg = <0x0 0x04404 0x0 0x20>; + reg = <0x0 0x04404 0x0 0x9c>; #reset-cells = <1>; }; uart_A: serial@84c0 { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x84c0 0x0 0x14>; + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x84c0 0x0 0x18>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; uart_B: serial@84dc { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x84dc 0x0 0x14>; + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x84dc 0x0 0x18>; interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; @@ -279,10 +286,9 @@ }; uart_C: serial@8700 { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x8700 0x0 0x14>; + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x8700 0x0 0x18>; interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; @@ -360,33 +366,53 @@ }; }; - aobus: aobus@c8100000 { + aobus: bus@c8100000 { compatible = "simple-bus"; reg = <0x0 0xc8100000 0x0 0x100000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; - clkc_AO: clock-controller@040 { - compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc"; - reg = <0x0 0x00040 0x0 0x4>; - #clock-cells = <1>; - #reset-cells = <1>; + sysctrl_AO: sys-ctrl@0 { + compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; + reg = <0x0 0x0 0x0 0x100>; + + pwrc_vpu: power-controller-vpu { + compatible = "amlogic,meson-gx-pwrc-vpu"; + #power-domain-cells = <0>; + amlogic,hhi-sysctrl = <&sysctrl>; + }; + + clkc_AO: clock-controller { + compatible = "amlogic,meson-gx-aoclkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + + cec_AO: cec@100 { + compatible = "amlogic,meson-gx-ao-cec"; + reg = <0x0 0x00100 0x0 0x14>; + interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; + }; + + sec_AO: ao-secure@140 { + compatible = "amlogic,meson-gx-ao-secure", "syscon"; + reg = <0x0 0x140 0x0 0x140>; + amlogic,has-chip-id; }; uart_AO: serial@4c0 { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x004c0 0x0 0x14>; + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + reg = <0x0 0x004c0 0x0 0x18>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; uart_AO_B: serial@4e0 { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x004e0 0x0 0x14>; + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + reg = <0x0 0x004e0 0x0 0x18>; interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; @@ -427,19 +453,24 @@ }; }; - hiubus: hiubus@c883c000 { + hiubus: bus@c883c000 { compatible = "simple-bus"; reg = <0x0 0xc883c000 0x0 0x2000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; + sysctrl: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; + reg = <0 0 0 0x400>; + }; + mailbox: mailbox@404 { compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; reg = <0 0x404 0 0x4c>; - interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, - <0 209 IRQ_TYPE_EDGE_RISING>, - <0 210 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; #mbox-cells = <1>; }; }; @@ -448,7 +479,7 @@ compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; - interrupts = <0 8 1>; + interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; interrupt-names = "macirq"; status = "disabled"; }; diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts index d147c853ab..ee4ada61c5 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -50,7 +50,7 @@ / { compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; model = "Hardkernel ODROID-C2"; - + aliases { serial0 = &uart_AO; }; @@ -135,6 +135,24 @@ compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; }; ðmac { @@ -156,7 +174,11 @@ #size-cells = <0>; eth_phy0: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_15 */ + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; eee-broken-1000t; }; }; @@ -177,6 +199,18 @@ }; }; +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + &i2c_A { status = "okay"; pinctrl-0 = <&i2c_a_pins>; @@ -194,7 +228,9 @@ "USB HUB nRESET", "USB OTG Power En", "J7 Header Pin2", "IR In", "J7 Header Pin4", "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7", - "HDMI CEC", "SYS LED"; + "HDMI CEC", "SYS LED", + /* GPIO_TEST_N */ + ""; }; &pinctrl_periphs { @@ -233,11 +269,9 @@ "J2 Header Pin12", "J2 Header Pin13", "J2 Header Pin8", "J2 Header Pin10", "", "", "", "", "", - "J2 Header Pin11", "", "J2 Header Pin7", + "J2 Header Pin11", "", "J2 Header Pin7", "", /* Bank GPIOCLK */ - "", "", "", "", - /* GPIO_TEST_N */ - ""; + "", "", "", ""; }; &saradc { @@ -253,7 +287,8 @@ &sd_emmc_b { status = "okay"; pinctrl-0 = <&sdcard_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <4>; cap-sd-highspeed; @@ -270,11 +305,11 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <8>; - cap-sd-highspeed; max-frequency = <200000000>; non-removable; disable-wp; @@ -300,6 +335,7 @@ &usb1_phy { status = "okay"; + phy-supply = <&usb_otg_pwr>; }; &usb0 { diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi index 17d3efdf14..3290a4dc35 100644 --- a/arch/arm/dts/meson-gxbb.dtsi +++ b/arch/arm/dts/meson-gxbb.dtsi @@ -307,6 +307,15 @@ }; }; +&cec_AO { + clocks = <&clkc_AO CLKID_AO_CEC_32K>; + clock-names = "core"; +}; + +&clkc_AO { + compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; +}; + ðmac { clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, @@ -314,6 +323,12 @@ clock-names = "stmmaceth", "clkin0", "clkin1"; }; +&gpio_intc { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson-gxbb-gpio-intc"; + status = "okay"; +}; + &hdmi_tx { compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; resets = <&reset RESET_HDMITX_CAPB3>, @@ -370,19 +385,36 @@ reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 14 120>; + gpio-ranges = <&pinctrl_periphs 0 0 119>; }; emmc_pins: emmc { mux { groups = "emmc_nand_d07", "emmc_cmd", - "emmc_clk", - "emmc_ds"; + "emmc_clk"; + function = "emmc"; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_ds"; function = "emmc"; }; }; + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "BOOT_8"; + bias-pull-down; + }; + }; + nor_pins: nor { mux { groups = "nor_d", @@ -421,6 +453,17 @@ }; }; + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "CARD_2"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "CARD_2"; + bias-pull-down; + }; + }; + sdio_pins: sdio { mux { groups = "sdio_d0", @@ -433,6 +476,17 @@ }; }; + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "GPIOX_4"; + bias-pull-down; + }; + }; + sdio_irq_pins: sdio_irq { mux { groups = "sdio_irq"; @@ -640,33 +694,74 @@ }; }; +&pwrc_vpu { + resets = <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_VCBUS>, + <&reset RESET_BT656>, + <&reset RESET_DVIN_RESET>, + <&reset RESET_RDMA>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC>, + <&reset RESET_VDI6>, + <&reset RESET_VENCL>, + <&reset RESET_VID_LOCK>; + clocks = <&clkc CLKID_VPU>, + <&clkc CLKID_VAPB>; + clock-names = "vpu", "vapb"; + /* + * VPU clocking is provided by two identical clock paths + * VPU_0 and VPU_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + * Same for VAPB but with a final gate after the glitch free mux. + */ + assigned-clocks = <&clkc CLKID_VPU_0_SEL>, + <&clkc CLKID_VPU_0>, + <&clkc CLKID_VPU>, /* Glitch free mux */ + <&clkc CLKID_VAPB_0_SEL>, + <&clkc CLKID_VAPB_0>, + <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc CLKID_VPU_0>, + <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VAPB_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <666666666>, + <0>, /* Do Nothing */ + <0>, /* Do Nothing */ + <250000000>, + <0>; /* Do Nothing */ +}; + &saradc { compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; clocks = <&xtal>, <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>, <&clkc CLKID_SAR_ADC_CLK>, <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; }; &sd_emmc_a { clocks = <&clkc CLKID_SD_EMMC_A>, - <&xtal>, + <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_b { clocks = <&clkc CLKID_SD_EMMC_B>, - <&xtal>, + <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_c { clocks = <&clkc CLKID_SD_EMMC_C>, - <&xtal>, + <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; @@ -682,6 +777,32 @@ clocks = <&clkc CLKID_SPI>; }; +&uart_A { + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_AO { + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_AO_B { + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_B { + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_C { + clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + &vpu { compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; + power-domains = <&pwrc_vpu>; }; diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts index 84cbebb534..c3515599ed 100644 --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts @@ -66,6 +66,13 @@ }; }; +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; @@ -104,6 +111,62 @@ linux,rc-map-name = "rc-geekbox"; }; +&pinctrl_aobus { + gpio-line-names = "UART TX", + "UART RX", + "Power Key In", + "J9 Header Pin35", + "J9 Header Pin16", + "J9 Header Pin15", + "J9 Header Pin33", + "IR In", + "HDMI CEC", + "SYS LED", + /* GPIO_TEST_N */ + ""; +}; + +&pinctrl_periphs { + gpio-line-names = /* Bank GPIOZ */ + "", "", "", "", "", "", "", + "", "", "", "", "", "", "", + "Power OFF", + "VCCK Enable", + /* Bank GPIOH */ + "HDMI HPD", "HDMI SDA", "HDMI SCL", + "HDMI_5V_EN", "SPDIF", + "J9 Header Pin37", + "J9 Header Pin30", + "J9 Header Pin29", + "J9 Header Pin32", + "J9 Header Pin31", + /* Bank BOOT */ + "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", + "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", + "eMMC Clk", "eMMC Reset", "eMMC CMD", + "", "BOOT_MODE", "", "", "eMMC Data Strobe", + /* Bank CARD */ + "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", + "SDCard D3", "SDCard D2", "SDCard Det", + /* Bank GPIODV */ + "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", + "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", + "VCCK Regulator", "VDDEE Regulator", + /* Bank GPIOX */ + "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", + "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", + "WIFI Power Enable", "WIFI WAKE HOST", + "Bluetooth PCM DOUT", "Bluetooth PCM DIN", + "Bluetooth PCM SYNC", "Bluetooth PCM CLK", + "Bluetooth UART TX", "Bluetooth UART RX", + "Bluetooth UART CTS", "Bluetooth UART RTS", + "WIFI 32K", "Bluetooth Enable", + "Bluetooth WAKE HOST", + /* Bank GPIOCLK */ + "", "J9 Header Pin39"; +}; + &pwm_AO_ab { status = "okay"; pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts index dc2acf4d16..9139761c79 100644 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts @@ -71,6 +71,18 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + hdmi_5v: regulator-hdmi-5v { + compatible = "regulator-fixed"; + + regulator-name = "HDMI_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + vcc_3v3: regulator-vcc_3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; @@ -90,6 +102,16 @@ states = <3300000 0>, <1800000 1>; + + regulator-settling-time-up-us = <200>; + regulator-settling-time-down-us = <50000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; vddio_boot: regulator-vddio_boot { @@ -100,6 +122,13 @@ }; }; +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + &cvbs_vdac_port { cvbs_vdac_out: endpoint { remote-endpoint = <&cvbs_connector_in>; @@ -110,6 +139,11 @@ status = "okay"; }; +&internal_phy { + pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; + pinctrl-names = "default"; +}; + &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>; @@ -128,14 +162,80 @@ }; }; +&pinctrl_aobus { + gpio-line-names = "UART TX", + "UART RX", + "Blue LED", + "SDCard Voltage Switch", + "7J1 Header Pin5", + "7J1 Header Pin3", + "7J1 Header Pin12", + "IR In", + "9J3 Switch HDMI CEC/7J1 Header Pin11", + "7J1 Header Pin13", + /* GPIO_TEST_N */ + "7J1 Header Pin15"; +}; + +&pinctrl_periphs { + gpio-line-names = /* Bank GPIOZ */ + "", "", "", "", "", "", "", + "", "", "", "", "", "", "", + "Eth Link LED", "Eth Activity LED", + /* Bank GPIOH */ + "HDMI HPD", "HDMI SDA", "HDMI SCL", + "HDMI_5V_EN", "9J1 Header Pin2", + "Analog Audio Mute", + "2J3 Header Pin6", + "2J3 Header Pin5", + "2J3 Header Pin4", + "2J3 Header Pin3", + /* Bank BOOT */ + "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", + "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", + "eMMC Clk", "eMMC Reset", "eMMC CMD", + "ALT BOOT MODE", "", "", "", "eMMC Data Strobe", + /* Bank CARD */ + "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", + "SDCard D3", "SDCard D2", "SDCard Det", + /* Bank GPIODV */ + "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", + "Green LED", "VCCK Enable", + "7J1 Header Pin27", "7J1 Header Pin28", + "VCCK Regulator", "VDDEE Regulator", + /* Bank GPIOX */ + "7J1 Header Pin22", "7J1 Header Pin26", + "7J1 Header Pin36", "7J1 Header Pin38", + "7J1 Header Pin40", "7J1 Header Pin37", + "7J1 Header Pin33", "7J1 Header Pin35", + "7J1 Header Pin19", "7J1 Header Pin21", + "7J1 Header Pin24", "7J1 Header Pin23", + "7J1 Header Pin8", "7J1 Header Pin10", + "7J1 Header Pin16", "7J1 Header Pin18", + "7J1 Header Pin32", "7J1 Header Pin29", + "7J1 Header Pin31", + /* Bank GPIOCLK */ + "7J1 Header Pin7", ""; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + /* SD card */ &sd_emmc_b { status = "okay"; pinctrl-0 = <&sdcard_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; max-frequency = <100000000>; disable-wp; @@ -149,11 +249,13 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <8>; cap-mmc-highspeed; + mmc-ddr-3_3v; max-frequency = <50000000>; non-removable; disable-wp; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dts b/arch/arm/dts/meson-gxl-s905x-p212.dts index 6ab17c1eee..6e2bf85829 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dts +++ b/arch/arm/dts/meson-gxl-s905x-p212.dts @@ -71,6 +71,13 @@ }; }; +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + &cvbs_vdac_port { cvbs_vdac_out: endpoint { remote-endpoint = <&cvbs_connector_in>; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi index 0385fb9861..2db1377819 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -27,6 +27,18 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + hdmi_5v: regulator-hdmi-5v { + compatible = "regulator-fixed"; + + regulator-name = "HDMI_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; @@ -94,7 +106,8 @@ &sd_emmc_a { status = "okay"; pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; #address-cells = <1>; #size-cells = <0>; @@ -115,7 +128,8 @@ &sd_emmc_b { status = "okay"; pinctrl-0 = <&sdcard_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <4>; cap-sd-highspeed; @@ -132,11 +146,11 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <8>; - cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <200000000>; non-removable; diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi index 8d4f3160a0..c8514110b9 100644 --- a/arch/arm/dts/meson-gxl.dtsi +++ b/arch/arm/dts/meson-gxl.dtsi @@ -43,11 +43,20 @@ #include "meson-gx.dtsi" #include <dt-bindings/clock/gxbb-clkc.h> +#include <dt-bindings/clock/gxbb-aoclkc.h> #include <dt-bindings/gpio/meson-gxl-gpio.h> #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> / { compatible = "amlogic,meson-gxl"; + + reserved-memory { + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved_alt: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + }; }; ðmac { @@ -207,6 +216,21 @@ }; }; +&cec_AO { + clocks = <&clkc_AO CLKID_AO_CEC_32K>; + clock-names = "core"; +}; + +&clkc_AO { + compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; +}; + +&gpio_intc { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson-gxl-gpio-intc"; + status = "okay"; +}; + &hdmi_tx { compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; resets = <&reset RESET_HDMITX_CAPB3>, @@ -258,19 +282,36 @@ reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 10 101>; + gpio-ranges = <&pinctrl_periphs 0 0 100>; }; emmc_pins: emmc { mux { groups = "emmc_nand_d07", "emmc_cmd", - "emmc_clk", - "emmc_ds"; + "emmc_clk"; function = "emmc"; }; }; + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_ds"; + function = "emmc"; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "BOOT_8"; + bias-pull-down; + }; + }; + nor_pins: nor { mux { groups = "nor_d", @@ -309,6 +350,17 @@ }; }; + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "CARD_2"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "CARD_2"; + bias-pull-down; + }; + }; + sdio_pins: sdio { mux { groups = "sdio_d0", @@ -321,6 +373,17 @@ }; }; + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "GPIOX_4"; + bias-pull-down; + }; + }; + sdio_irq_pins: sdio_irq { mux { groups = "sdio_irq"; @@ -568,6 +631,7 @@ internal_phy: ethernet-phy@8 { compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <8>; max-speed = <100>; }; @@ -581,33 +645,74 @@ }; }; +&pwrc_vpu { + resets = <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_VCBUS>, + <&reset RESET_BT656>, + <&reset RESET_DVIN_RESET>, + <&reset RESET_RDMA>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC>, + <&reset RESET_VDI6>, + <&reset RESET_VENCL>, + <&reset RESET_VID_LOCK>; + clocks = <&clkc CLKID_VPU>, + <&clkc CLKID_VAPB>; + clock-names = "vpu", "vapb"; + /* + * VPU clocking is provided by two identical clock paths + * VPU_0 and VPU_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + * Same for VAPB but with a final gate after the glitch free mux. + */ + assigned-clocks = <&clkc CLKID_VPU_0_SEL>, + <&clkc CLKID_VPU_0>, + <&clkc CLKID_VPU>, /* Glitch free mux */ + <&clkc CLKID_VAPB_0_SEL>, + <&clkc CLKID_VAPB_0>, + <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc CLKID_VPU_0>, + <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VAPB_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <666666666>, + <0>, /* Do Nothing */ + <0>, /* Do Nothing */ + <250000000>, + <0>; /* Do Nothing */ +}; + &saradc { compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; clocks = <&xtal>, <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>, <&clkc CLKID_SAR_ADC_CLK>, <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; }; &sd_emmc_a { clocks = <&clkc CLKID_SD_EMMC_A>, - <&xtal>, + <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_b { clocks = <&clkc CLKID_SD_EMMC_B>, - <&xtal>, + <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_c { clocks = <&clkc CLKID_SD_EMMC_C>, - <&xtal>, + <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; @@ -623,6 +728,32 @@ clocks = <&clkc CLKID_SPI>; }; +&uart_A { + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_AO { + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_AO_B { + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_B { + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_C { + clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + &vpu { compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; + power-domains = <&pwrc_vpu>; }; diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi index b84899a1ea..2b894162e9 100644 --- a/arch/arm/dts/stm32mp157.dtsi +++ b/arch/arm/dts/stm32mp157.dtsi @@ -123,6 +123,48 @@ }; }; + pwr: pwr@50001000 { + compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd"; + reg = <0x50001000 0x400>; + system-power-controller; + interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>; + st,sysrcc = <&rcc>; + clocks = <&rcc_clk PLL2_R>; + clock-names = "phyclk"; + + pwr-regulators@c { + compatible = "st,stm32mp1,pwr-reg"; + st,tzcr = <&rcc 0x0 0x1>; + + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + vrefbuf: vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc_clk VREF>; + status = "disabled"; + }; + pinctrl: pin-controller { compatible = "st,stm32mp157-pinctrl"; #address-cells = <1>; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 129cd02418..2334707422 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -10,6 +10,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/stm32-pinfunc.h> +#include <dt-bindings/mfd/st,stpmu1.h> / { model = "STMicroelectronics STM32MP157C pmic eval daughter"; @@ -23,6 +24,19 @@ memory { reg = <0xC0000000 0x40000000>; }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1 2900000 0x0>; + }; }; &gpioa { @@ -166,6 +180,262 @@ interrupt-controller; #interrupt-cells = <2>; status = "okay"; + + st,main_control_register = <0x04>; + st,vin_control_register = <0xc0>; + st,usb_control_register = <0x30>; + + regulators { + compatible = "st,stpmu1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <2>; + regulator-over-current-protection; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1200000>; + regulator-mode = <8>; + }; + regulator-state-mem { + regulator-off-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <2>; + regulator-over-current-protection; + + regulator-state-standby { + regulator-suspend-microvolt = <1350000>; + regulator-on-in-suspend; + regulator-mode = <8>; + }; + regulator-state-mem { + regulator-suspend-microvolt = <1350000>; + regulator-on-in-suspend; + regulator-mode = <8>; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask_reset; + regulator-initial-mode = <8>; + regulator-over-current-protection; + + regulator-state-standby { + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + regulator-mode = <8>; + }; + regulator-state-mem { + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + regulator-mode = <8>; + }; + regulator-state-disk { + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + regulator-mode = <8>; + }; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-over-current-protection; + regulator-initial-mode = <8>; + + regulator-state-standby { + regulator-suspend-microvolt = <3300000>; + regulator-unchanged-in-suspend; + regulator-mode = <8>; + }; + regulator-state-mem { + regulator-off-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO1 0>; + interrupt-parent = <&pmic>; + + regulator-state-standby { + regulator-suspend-microvolt = <2900000>; + regulator-unchanged-in-suspend; + }; + regulator-state-mem { + regulator-off-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = <IT_CURLIM_LDO2 0>; + interrupt-parent = <&pmic>; + + regulator-state-standby { + regulator-suspend-microvolt = <2800000>; + regulator-unchanged-in-suspend; + }; + regulator-state-mem { + regulator-off-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <0000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-over-current-protection; + + regulator-state-standby { + regulator-off-in-suspend; + }; + regulator-state-mem { + regulator-off-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + interrupt-parent = <&pmic>; + + regulator-state-standby { + regulator-unchanged-in-suspend; + }; + regulator-state-mem { + regulator-off-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + interrupt-parent = <&pmic>; + regulator-boot-on; + + regulator-state-standby { + regulator-suspend-microvolt = <2900000>; + regulator-unchanged-in-suspend; + }; + regulator-state-mem { + regulator-off-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO6 0>; + interrupt-parent = <&pmic>; + + regulator-state-standby { + regulator-suspend-microvolt = <1800000>; + regulator-unchanged-in-suspend; + }; + regulator-state-mem { + regulator-off-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + + regulator-state-standby { + regulator-on-in-suspend; + }; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + interrupt-parent = <&pmic>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + interrupt-parent = <&pmic>; + regulator-active-discharge; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + interrupt-parent = <&pmic>; + regulator-active-discharge; + }; + }; }; }; @@ -177,6 +447,8 @@ st,negedge; st,pin-ckin; bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h new file mode 100644 index 0000000000..03fb6b03de --- /dev/null +++ b/arch/arm/include/asm/arch-meson/gx.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> + */ + +#ifndef __GX_H__ +#define __GX_H__ + +#define GX_FIRMWARE_MEM_SIZE 0x1000000 + +#define GX_AOBUS_BASE 0xc8100000 +#define GX_PERIPHS_BASE 0xc8834400 +#define GX_HIU_BASE 0xc883c000 +#define GX_ETH_BASE 0xc9410000 + +/* Always-On Peripherals registers */ +#define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2)) + +#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90) +#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93) +#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) +#define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) + +#define GX_AO_MEM_SIZE_MASK 0xFFFF0000 +#define GX_AO_MEM_SIZE_SHIFT 16 +#define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2)) + +/* GPIO registers 0 to 6 */ +#define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) +#define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0) +#define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1) +#define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2) + +#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50) +#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51) +#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56) +#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57) + +#define GX_ETH_REG_0_PHY_INTF BIT(0) +#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define GX_ETH_REG_0_PHY_CLK_EN BIT(10) +#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define GX_ETH_REG_0_CLK_EN BIT(12) + +/* HIU registers */ +#define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2)) + +#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +/* Clock gates */ +#define GX_GCLK_MPEG_0 GX_HIU_ADDR(0x50) +#define GX_GCLK_MPEG_1 GX_HIU_ADDR(0x51) +#define GX_GCLK_MPEG_2 GX_HIU_ADDR(0x52) +#define GX_GCLK_MPEG_OTHER GX_HIU_ADDR(0x53) +#define GX_GCLK_MPEG_AO GX_HIU_ADDR(0x54) + +#define GX_GCLK_MPEG_0_I2C BIT(9) +#define GX_GCLK_MPEG_1_ETH BIT(3) + +#endif /* __GX_H__ */ diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h deleted file mode 100644 index c7713b27b9..0000000000 --- a/arch/arm/include/asm/arch-meson/gxbb.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> - */ - -#ifndef __GXBB_H__ -#define __GXBB_H__ - -#define GXBB_FIRMWARE_MEM_SIZE 0x1000000 - -#define GXBB_AOBUS_BASE 0xc8100000 -#define GXBB_PERIPHS_BASE 0xc8834400 -#define GXBB_HIU_BASE 0xc883c000 -#define GXBB_ETH_BASE 0xc9410000 - -/* Always-On Peripherals registers */ -#define GXBB_AO_ADDR(off) (GXBB_AOBUS_BASE + ((off) << 2)) - -#define GXBB_AO_SEC_GP_CFG0 GXBB_AO_ADDR(0x90) -#define GXBB_AO_SEC_GP_CFG3 GXBB_AO_ADDR(0x93) -#define GXBB_AO_SEC_GP_CFG4 GXBB_AO_ADDR(0x94) -#define GXBB_AO_SEC_GP_CFG5 GXBB_AO_ADDR(0x95) - -#define GXBB_AO_MEM_SIZE_MASK 0xFFFF0000 -#define GXBB_AO_MEM_SIZE_SHIFT 16 -#define GXBB_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 -#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16 -#define GXBB_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF - -/* Peripherals registers */ -#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2)) - -/* GPIO registers 0 to 6 */ -#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) -#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0) -#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1) -#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2) - -#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50) -#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51) -#define GXBB_ETH_REG_2 GXBB_PERIPHS_ADDR(0x56) -#define GXBB_ETH_REG_3 GXBB_PERIPHS_ADDR(0x57) - -#define GXBB_ETH_REG_0_PHY_INTF BIT(0) -#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10) -#define GXBB_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define GXBB_ETH_REG_0_CLK_EN BIT(12) - -/* HIU registers */ -#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2)) - -#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - -/* Clock gates */ -#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50) -#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51) -#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52) -#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53) -#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54) - -#define GXBB_GCLK_MPEG_0_I2C BIT(9) -#define GXBB_GCLK_MPEG_1_ETH BIT(3) - -#endif /* __GXBB_H__ */ diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h index 81e0e9f332..7a03d6d3c7 100644 --- a/arch/arm/mach-at91/include/mach/atmel_pio4.h +++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h @@ -47,6 +47,10 @@ struct atmel_pio4_port { #define ATMEL_PIO_IFSCEN_MASK BIT(13) #define ATMEL_PIO_OPD_MASK BIT(14) #define ATMEL_PIO_SCHMITT_MASK BIT(15) +#define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16) +#define ATMEL_PIO_DRVSTR_LO (1 << 16) +#define ATMEL_PIO_DRVSTR_ME (2 << 16) +#define ATMEL_PIO_DRVSTR_HI (3 << 16) #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) @@ -68,14 +72,14 @@ struct atmel_pio4_port { #define AT91_PIO_PORTC 0x2 #define AT91_PIO_PORTD 0x3 -int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup); -int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup); -int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup); -int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup); -int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup); -int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup); -int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup); -int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config); +int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config); +int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config); +int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config); +int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config); +int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config); +int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config); +int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config); int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value); int atmel_pio4_get_pio_input(u32 port, u32 pin); diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c index 89e75fb65b..1ef7e5a6d1 100644 --- a/arch/arm/mach-meson/board.c +++ b/arch/arm/mach-meson/board.c @@ -6,7 +6,7 @@ #include <common.h> #include <linux/libfdt.h> #include <linux/err.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <asm/arch/sm.h> #include <asm/armv8/mmu.h> #include <asm/unaligned.h> @@ -39,8 +39,8 @@ int dram_init(void) phys_size_t get_effective_memsize(void) { /* Size is reported in MiB, convert it in bytes */ - return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK) - >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M; + return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK) + >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M; } static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) @@ -71,27 +71,27 @@ void meson_gx_init_reserved_memory(void *fdt) * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL */ - reg = readl(GXBB_AO_SEC_GP_CFG3); + reg = readl(GX_AO_SEC_GP_CFG3); - bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK) - >> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; - bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK) + >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; - bl31_start = readl(GXBB_AO_SEC_GP_CFG5); - bl32_start = readl(GXBB_AO_SEC_GP_CFG4); + bl31_start = readl(GX_AO_SEC_GP_CFG5); + bl32_start = readl(GX_AO_SEC_GP_CFG4); /* - * Early Meson GXBB Firmware revisions did not provide the reserved + * Early Meson GX Firmware revisions did not provide the reserved * memory zones in the registers, keep fixed memory zone handling. */ - if (IS_ENABLED(CONFIG_MESON_GXBB) && + if (IS_ENABLED(CONFIG_MESON_GX) && !reg && !bl31_start && !bl32_start) { bl31_start = 0x10000000; bl31_size = 0x200000; } /* Add first 16MiB reserved zone */ - meson_board_add_reserved_memory(fdt, 0, GXBB_FIRMWARE_MEM_SIZE); + meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE); /* Add BL31 reserved zone */ if (bl31_start && bl31_size) @@ -107,7 +107,7 @@ void reset_cpu(ulong addr) psci_system_reset(); } -static struct mm_region gxbb_mem_map[] = { +static struct mm_region gx_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -127,4 +127,4 @@ static struct mm_region gxbb_mem_map[] = { } }; -struct mm_region *mem_map = gxbb_mem_map; +struct mm_region *mem_map = gx_mem_map; diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c index e340212c2a..061f19a0e3 100644 --- a/arch/arm/mach-meson/eth.c +++ b/arch/arm/mach-meson/eth.c @@ -7,7 +7,7 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <asm/arch/eth.h> #include <phy.h> @@ -22,23 +22,23 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: /* Set RGMII mode */ - setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | - GXBB_ETH_REG_0_TX_PHASE(1) | - GXBB_ETH_REG_0_TX_RATIO(4) | - GXBB_ETH_REG_0_PHY_CLK_EN | - GXBB_ETH_REG_0_CLK_EN); + setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | + GX_ETH_REG_0_TX_PHASE(1) | + GX_ETH_REG_0_TX_RATIO(4) | + GX_ETH_REG_0_PHY_CLK_EN | + GX_ETH_REG_0_CLK_EN); break; case PHY_INTERFACE_MODE_RMII: /* Set RMII mode */ - out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK | - GXBB_ETH_REG_0_CLK_EN); + out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | + GX_ETH_REG_0_CLK_EN); /* Use GXL RMII Internal PHY */ if (IS_ENABLED(CONFIG_MESON_GXL) && (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) { - writel(0x10110181, GXBB_ETH_REG_2); - writel(0xe40908ff, GXBB_ETH_REG_3); + writel(0x10110181, GX_ETH_REG_2); + writel(0xe40908ff, GX_ETH_REG_3); } break; @@ -49,6 +49,6 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) } /* Enable power and clock gate */ - setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); - clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); + setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH); + clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); } diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c index 9829bae657..0bba5e4a07 100644 --- a/arch/arm/mach-meson/sm.c +++ b/arch/arm/mach-meson/sm.c @@ -6,7 +6,7 @@ */ #include <common.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <linux/kernel.h> #define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020 diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 92a6f799d4..dc7b37f164 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -29,6 +29,8 @@ static void omap_set_fastboot_cpu(void) switch (cpu_rev) { case DRA762_ES1_0: + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: cpu = "DRA762"; break; case DRA752_ES1_0: diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index a9b523d96f..08ee642d90 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -9,3 +9,4 @@ obj-y += syscon.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_ARMV7_PSCI) += psci.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index afcab299cf..a8142013b0 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -28,6 +28,7 @@ enum { STM32MP_SYSCON_UNKNOWN, STM32MP_SYSCON_STGEN, + STM32MP_SYSCON_PWR, }; /* diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/pwr_regulator.c new file mode 100644 index 0000000000..9484645dbd --- /dev/null +++ b/arch/arm/mach-stm32mp/pwr_regulator.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <regmap.h> +#include <syscon.h> +#include <power/pmic.h> +#include <power/regulator.h> + +#define STM32MP_PWR_CR3 0xc +#define STM32MP_PWR_CR3_USB33DEN BIT(24) +#define STM32MP_PWR_CR3_USB33RDY BIT(26) +#define STM32MP_PWR_CR3_REG18DEN BIT(28) +#define STM32MP_PWR_CR3_REG18RDY BIT(29) +#define STM32MP_PWR_CR3_REG11DEN BIT(30) +#define STM32MP_PWR_CR3_REG11RDY BIT(31) + +struct stm32mp_pwr_reg_info { + u32 enable; + u32 ready; + char *name; +}; + +struct stm32mp_pwr_priv { + struct regmap *regmap; +}; + +static int stm32mp_pwr_write(struct udevice *dev, uint reg, + const uint8_t *buff, int len) +{ + struct stm32mp_pwr_priv *priv = dev_get_priv(dev); + u32 val = *(u32 *)buff; + + if (len != 4) + return -EINVAL; + + return regmap_write(priv->regmap, STM32MP_PWR_CR3, val); +} + +static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff, + int len) +{ + struct stm32mp_pwr_priv *priv = dev_get_priv(dev); + + if (len != 4) + return -EINVAL; + + return regmap_read(priv->regmap, STM32MP_PWR_CR3, (u32 *)buff); +} + +static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev) +{ + struct stm32mp_pwr_priv *priv = dev_get_priv(dev); + struct regmap *regmap; + + regmap = syscon_get_regmap_by_driver_data(STM32MP_SYSCON_PWR); + if (IS_ERR(regmap)) { + pr_err("%s: unable to find regmap (%ld)\n", __func__, + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + priv->regmap = regmap; + + return 0; +} + +static const struct pmic_child_info pwr_children_info[] = { + { .prefix = "reg", .driver = "stm32mp_pwr_regulator"}, + { .prefix = "usb", .driver = "stm32mp_pwr_regulator"}, + { }, +}; + +static int stm32mp_pwr_bind(struct udevice *dev) +{ + int children; + + children = pmic_bind_children(dev, dev->node, pwr_children_info); + if (!children) + dev_dbg(dev, "no child found\n"); + + return 0; +} + +static struct dm_pmic_ops stm32mp_pwr_ops = { + .read = stm32mp_pwr_read, + .write = stm32mp_pwr_write, +}; + +static const struct udevice_id stm32mp_pwr_ids[] = { + { .compatible = "st,stm32mp1,pwr-reg" }, + { } +}; + +U_BOOT_DRIVER(stm32mp_pwr_pmic) = { + .name = "stm32mp_pwr_pmic", + .id = UCLASS_PMIC, + .of_match = stm32mp_pwr_ids, + .bind = stm32mp_pwr_bind, + .ops = &stm32mp_pwr_ops, + .ofdata_to_platdata = stm32mp_pwr_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct stm32mp_pwr_priv), +}; + +static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = { + .enable = STM32MP_PWR_CR3_REG11DEN, + .ready = STM32MP_PWR_CR3_REG11RDY, + .name = "reg11" +}; + +static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg18 = { + .enable = STM32MP_PWR_CR3_REG18DEN, + .ready = STM32MP_PWR_CR3_REG18RDY, + .name = "reg18" +}; + +static const struct stm32mp_pwr_reg_info stm32mp_pwr_usb33 = { + .enable = STM32MP_PWR_CR3_USB33DEN, + .ready = STM32MP_PWR_CR3_USB33RDY, + .name = "usb33" +}; + +static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = { + &stm32mp_pwr_reg11, + &stm32mp_pwr_reg18, + &stm32mp_pwr_usb33, + NULL +}; + +static int stm32mp_pwr_regulator_probe(struct udevice *dev) +{ + const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos; + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + + while (*p) { + int rc; + + rc = dev_read_stringlist_search(dev, "regulator-name", + (*p)->name); + if (rc >= 0) { + dev_dbg(dev, "found regulator %s\n", (*p)->name); + break; + } else if (rc != -ENODATA) { + return rc; + } + p++; + } + if (!*p) { + int i = 0; + const char *s; + + dev_dbg(dev, "regulator "); + while (dev_read_string_index(dev, "regulator-name", + i++, &s) >= 0) + dev_dbg(dev, "%s'%s' ", (i > 1) ? ", " : "", s); + dev_dbg(dev, "%s not supported\n", (i > 2) ? "are" : "is"); + return -EINVAL; + } + + uc_pdata->type = REGULATOR_TYPE_FIXED; + dev->priv = (void *)*p; + + return 0; +} + +static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + if (uc_pdata->min_uV != uV) { + dev_dbg(dev, "Invalid uV=%d for: %s\n", uV, uc_pdata->name); + return -EINVAL; + } + + return 0; +} + +static int stm32mp_pwr_regulator_get_value(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + if (uc_pdata->min_uV != uc_pdata->max_uV) { + dev_dbg(dev, "Invalid constraints for: %s\n", uc_pdata->name); + return -EINVAL; + } + + return uc_pdata->min_uV; +} + +static int stm32mp_pwr_regulator_get_enable(struct udevice *dev) +{ + const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev); + int rc; + u32 reg; + + rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + + dev_dbg(dev, "%s id %s\n", p->name, (reg & p->enable) ? "on" : "off"); + + return (reg & p->enable) != 0; +} + +static int stm32mp_pwr_regulator_set_enable(struct udevice *dev, bool enable) +{ + const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev); + int rc; + u32 reg; + u32 time_start; + + dev_dbg(dev, "Turning %s %s\n", enable ? "on" : "off", p->name); + + rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + + /* if regulator is already in the wanted state, nothing to do */ + if (!!(reg & p->enable) == enable) + return 0; + + reg &= ~p->enable; + if (enable) + reg |= p->enable; + + rc = pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + + if (!enable) + return 0; + + /* waiting ready for enable */ + time_start = get_timer(0); + while (1) { + rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + if (reg & p->ready) + break; + if (get_timer(time_start) > CONFIG_SYS_HZ) { + dev_dbg(dev, "%s: timeout\n", p->name); + return -ETIMEDOUT; + } + } + return 0; +} + +static const struct dm_regulator_ops stm32mp_pwr_regulator_ops = { + .set_value = stm32mp_pwr_regulator_set_value, + .get_value = stm32mp_pwr_regulator_get_value, + .get_enable = stm32mp_pwr_regulator_get_enable, + .set_enable = stm32mp_pwr_regulator_set_enable, +}; + +U_BOOT_DRIVER(stm32mp_pwr_regulator) = { + .name = "stm32mp_pwr_regulator", + .id = UCLASS_REGULATOR, + .ops = &stm32mp_pwr_regulator_ops, + .probe = stm32mp_pwr_regulator_probe, +}; diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index 66b94f592f..eb7f435f10 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -11,6 +11,8 @@ static const struct udevice_id stm32mp_syscon_ids[] = { { .compatible = "st,stm32-stgen", .data = STM32MP_SYSCON_STGEN }, + { .compatible = "st,stm32mp1-pwr", + .data = STM32MP_SYSCON_PWR }, { } }; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 3c25cb79ef..683b1970e0 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -254,6 +254,18 @@ gpios = <&gpio_a 2 0>; label = "sandbox:green"; }; + + default_on { + gpios = <&gpio_a 5 0>; + label = "sandbox:default_on"; + default-state = "on"; + }; + + default_off { + gpios = <&gpio_a 6 0>; + label = "sandbox:default_off"; + default-state = "off"; + }; }; mbox: mbox { |