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-rw-r--r--arch/x86/Kconfig10
-rw-r--r--arch/x86/lib/fsp/fsp_dram.c6
-rw-r--r--arch/x86/lib/zimage.c5
3 files changed, 20 insertions, 1 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index cbbaa4f2ce..e8968a7182 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -369,4 +369,14 @@ config PCIE_ECAM_BASE
assigned to PCI devices - i.e. the memory and prefetch regions, as
passed to pci_set_region().
+config PCIE_ECAM_SIZE
+ hex
+ default 0x10000000
+ help
+ This is the size of memory-mapped address of PCI configuration space,
+ which is only available through the Enhanced Configuration Access
+ Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
+ so a default 0x10000000 size covers all of the 256 buses which is the
+ maximum number of PCI buses as defined by the PCI specification.
+
endmenu
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 4c0a7c82ca..28552fa15a 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -77,5 +77,11 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
num_entries++;
}
+ /* Mark PCIe ECAM address range as reserved */
+ entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
+ entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
+ entries[num_entries].type = E820_RESERVED;
+ num_entries++;
+
return num_entries;
}
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 144471c5bb..a1ec57e8d3 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -61,8 +61,11 @@ __weak unsigned install_e820_map(unsigned max_entries,
entries[2].addr = ISA_END_ADDRESS;
entries[2].size = gd->ram_size - ISA_END_ADDRESS;
entries[2].type = E820_RAM;
+ entries[3].addr = CONFIG_PCIE_ECAM_BASE;
+ entries[3].size = CONFIG_PCIE_ECAM_SIZE;
+ entries[3].type = E820_RESERVED;
- return 3;
+ return 4;
}
static void build_command_line(char *command_line, int auto_boot)