diff options
Diffstat (limited to 'arch')
201 files changed, 8065 insertions, 2153 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 1709d40e97..ec120139cb 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -55,6 +55,7 @@ config MIPS select HAVE_PRIVATE_LIBGCC select HAVE_GENERIC_BOARD select SYS_GENERIC_BOARD + select SUPPORT_OF_CONTROL config NDS32 bool "NDS32 architecture" diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 26a5934189..90ee7e0fe4 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -50,18 +50,20 @@ ENTRY(_start) 1: #endif - /* Setup stack- and frame-pointers */ + /* Establish C runtime stack and frame */ mov %sp, CONFIG_SYS_INIT_SP_ADDR mov %fp, %sp - /* Allocate and zero GD, update SP */ + /* Allocate reserved area from current top of stack */ mov %r0, %sp - bl board_init_f_mem - - /* Update stack- and frame-pointers */ + bl board_init_f_alloc_reserve + /* Set stack below reserved area, adjust frame pointer accordingly */ mov %sp, %r0 mov %fp, %sp + /* Initialize reserved area - note: r0 already contains address */ + bl board_init_f_init_reserve + /* Zero the one and only argument of "board_init_f" */ mov_s %r0, 0 j board_init_f diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9bd6cf1d80..876a620cf1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -117,7 +117,14 @@ config ARCH_MVEBU select OF_CONTROL select OF_SEPARATE select DM + select DM_ETH select DM_SERIAL + select DM_SPI + select DM_SPI_FLASH + select SPL_DM + select SPL_DM_SEQ_ALIAS + select SPL_OF_CONTROL + select SPL_SIMPLE_BUS config TARGET_DEVKIT3250 bool "Support devkit3250" @@ -695,8 +702,8 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) -config TARGET_STM32F429_DISCOVERY - bool "Support STM32F429 Discovery" +config STM32 + bool "Support STM32" select CPU_V7M select DM select DM_SERIAL @@ -709,6 +716,10 @@ config ARCH_ROCKCHIP select CPU_V7 select DM +config TARGET_THUNDERX_88XX + bool "Support ThunderX 88xx" + select OF_CONTROL + endchoice source "arch/arm/mach-at91/Kconfig" @@ -751,6 +762,8 @@ source "arch/arm/mach-s5pc1xx/Kconfig" source "arch/arm/mach-socfpga/Kconfig" +source "arch/arm/mach-stm32/Kconfig" + source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-uniphier/Kconfig" @@ -769,8 +782,6 @@ source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" -source "board/Marvell/db-88f6820-gp/Kconfig" -source "board/Marvell/db-mv784mp-gp/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" @@ -779,6 +790,7 @@ source "board/bluegiga/apx4devkit/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" +source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" @@ -809,7 +821,6 @@ source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" -source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/phytec/pcm051/Kconfig" @@ -827,7 +838,6 @@ source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" -source "board/st/stm32f429-discovery/Kconfig" source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" source "board/syteco/zmx25/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 18283d1d35..cd7d8803f3 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -49,13 +49,14 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood -machine-$(CONFIG_ARMADA_XP) += mvebu +machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip +machine-$(CONFIG_STM32) += stm32 machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_ZYNQ) += zynq diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index b1c3f8f4ad..b6db23e981 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -5,12 +5,14 @@ */ #include <common.h> -#include <asm/arch/cpu.h> +#include <dm.h> +#include <ns16550.h> +#include <dm/platform_data/lpc32xx_hsuart.h> + #include <asm/arch/clk.h> #include <asm/arch/uart.h> #include <asm/arch/mux.h> #include <asm/io.h> -#include <dm.h> static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; @@ -41,6 +43,37 @@ void lpc32xx_uart_init(unsigned int uart_id) &clk->u3clk + (uart_id - 3)); } +#if !CONFIG_IS_ENABLED(OF_CONTROL) +static const struct ns16550_platdata lpc32xx_uart[] = { + { UART3_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { UART4_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { UART5_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { UART6_BASE, 2, CONFIG_SYS_NS16550_CLK }, +}; + +#if defined(CONFIG_LPC32XX_HSUART) +static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = { + { HS_UART1_BASE, }, + { HS_UART2_BASE, }, + { HS_UART7_BASE, }, +}; +#endif + +U_BOOT_DEVICES(lpc32xx_uarts) = { +#if defined(CONFIG_LPC32XX_HSUART) + { "lpc32xx_hsuart", &lpc32xx_hsuart[0], }, + { "lpc32xx_hsuart", &lpc32xx_hsuart[1], }, +#endif + { "ns16550_serial", &lpc32xx_uart[0], }, + { "ns16550_serial", &lpc32xx_uart[1], }, + { "ns16550_serial", &lpc32xx_uart[2], }, + { "ns16550_serial", &lpc32xx_uart[3], }, +#if defined(CONFIG_LPC32XX_HSUART) + { "lpc32xx_hsuart", &lpc32xx_hsuart[2], }, +#endif +}; +#endif + void lpc32xx_dma_init(void) { /* Enable DMA interface */ diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c index 602d993e39..52ea7342df 100644 --- a/arch/arm/cpu/armv7/omap-common/utils.c +++ b/arch/arm/cpu/armv7/omap-common/utils.c @@ -108,6 +108,6 @@ void omap_die_id_display(void) omap_die_id(die_id); - printf("OMAP die ID: %08x%08x%08x%08x", die_id[0], die_id[1], die_id[2], - die_id[3]); + printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[0], die_id[1], + die_id[2], die_id[3]); } diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 4501884e1c..1da5455c9a 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -77,6 +77,16 @@ int clock_twi_onoff(int port, int state) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + if (port == 5) { + if (state) + prcm_apb0_enable( + PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); + else + prcm_apb0_disable( + PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); + return 0; + } + /* set the apb clock gate for twi */ if (state) setbits_le32(&ccm->apb2_gate, diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c index 19b4938dc9..e1d091fd57 100644 --- a/arch/arm/cpu/armv7/sunxi/prcm.c +++ b/arch/arm/cpu/armv7/sunxi/prcm.c @@ -33,3 +33,15 @@ void prcm_apb0_enable(u32 flags) /* deassert reset for module */ setbits_le32(&prcm->apb0_reset, flags); } + +void prcm_apb0_disable(u32 flags) +{ + struct sunxi_prcm_reg *prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* assert reset for module */ + clrbits_le32(&prcm->apb0_reset, flags); + + /* close the clock for module */ + clrbits_le32(&prcm->apb0_gate, flags); +} diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index 93a19566f5..aff60e8102 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -7,6 +7,3 @@ extra-y := start.o obj-y += cpu.o - -obj-$(CONFIG_STM32F1) += stm32f1/ -obj-$(CONFIG_STM32F4) += stm32f4/ diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 48c041bb9b..1c85aa924d 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -14,6 +14,7 @@ obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o +obj-y += fwcall.o obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 53bac3b449..71f0020c7f 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,6 +12,69 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_SYS_FULL_VA +static void set_ptl1_entry(u64 index, u64 ptl2_entry) +{ + u64 *pgd = (u64 *)gd->arch.tlb_addr; + u64 value; + + value = ptl2_entry | PTL1_TYPE_TABLE; + pgd[index] = value; +} + +static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_attrs) +{ + u64 *pmd = (u64 *)ptl1; + u64 value; + + value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF; + value |= memory_attrs; + pmd[bfn] = value; +} + +static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP; + +#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES +#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES + +static void setup_pgtables(void) +{ + int l1_e, l2_e; + unsigned long pmd = 0; + unsigned long address; + + /* Setup the PMD pointers */ + for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) { + gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr + + PTL1_ENTRIES * sizeof(u64); + gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e; + gd->arch.pmd_addr[l1_e] = ALIGN(gd->arch.pmd_addr[l1_e], + 0x10000UL); + } + + /* Setup the page tables */ + for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) { + if (mem_map[pmd].base == + (uintptr_t)l1_e << PTL2_BITS) { + set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]); + + for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) { + address = mem_map[pmd].base + + (uintptr_t)l2_e * BLOCK_SIZE; + set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e, + address, mem_map[pmd].attrs); + } + + pmd++; + } else { + set_ptl1_entry(l1_e, 0); + } + } +} + +#else + inline void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, u64 attribute) { @@ -30,14 +93,24 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) value = (u64)table_addr | PMD_TYPE_TABLE; page_table[index] = value; } +#endif /* to activate the MMU we need to set up virtual memory */ __weak void mmu_setup(void) { +#ifndef CONFIG_SYS_FULL_VA bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; +#endif int el; +#ifdef CONFIG_SYS_FULL_VA + unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK; + + /* Set up page tables only on BSP */ + if (coreid == BSP_COREID) + setup_pgtables(); +#else /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, @@ -55,6 +128,7 @@ __weak void mmu_setup(void) } } +#endif /* load TTBR0 */ el = current_el(); if (el == 1) { @@ -154,6 +228,7 @@ u64 *__weak arch_get_page_table(void) { return NULL; } +#ifndef CONFIG_SYS_FULL_VA void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { @@ -179,6 +254,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, flush_dcache_range(start, end); asm volatile("dsb sy"); } +#endif + #else /* CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c new file mode 100644 index 0000000000..9efcc5ada9 --- /dev/null +++ b/arch/arm/cpu/armv8/fwcall.c @@ -0,0 +1,75 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <asm-offsets.h> +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/system.h> + +/* + * Issue the hypervisor call + * + * x0~x7: input arguments + * x0~x3: output arguments + */ +void hvc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "ldr x7, %7\n" + "hvc #0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]), "m" (args->regs[7]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17"); +} + +/* + * void smc_call(arg0, arg1...arg7) + * + * issue the secure monitor call + * + * x0~x7: input arguments + * x0~x3: output arguments + */ + +void smc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "smc #0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17"); +} diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index da45d984d0..2ee60d60f1 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -43,6 +43,9 @@ _bss_end_ofs: .quad __bss_end - _start reset: +#ifdef CONFIG_SYS_RESET_SCTRL + bl reset_sctrl +#endif /* * Could be EL3/EL2/EL1, Initial State: * Little Endian, MMU Disabled, i/dCache Disabled @@ -99,6 +102,39 @@ master_cpu: bl _main +#ifdef CONFIG_SYS_RESET_SCTRL +reset_sctrl: + switch_el x1, 3f, 2f, 1f +3: + mrs x0, sctlr_el3 + b 0f +2: + mrs x0, sctlr_el2 + b 0f +1: + mrs x0, sctlr_el1 + +0: + ldr x1, =0xfdfffffa + and x0, x0, x1 + + switch_el x1, 6f, 5f, 4f +6: + msr sctlr_el3, x0 + b 7f +5: + msr sctlr_el2, x0 + b 7f +4: + msr sctlr_el1, x0 + +7: + dsb sy + isb + b __asm_invalidate_tlb_all + ret +#endif + /*-----------------------------------------------------------------------*/ WEAK(apply_core_errata) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0bcd316375..e4f8aaef55 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -48,8 +48,11 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-388-clearfog.dtb \ armada-388-gp.dtb \ - armada-xp-gp.dtb + armada-xp-gp.dtb \ + armada-xp-maxbcm.dtb \ + armada-xp-synology-ds414.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ @@ -74,6 +77,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-ep108.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb +dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index 3fffe1eec3..c95d1d3b35 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -25,6 +25,7 @@ serial0 = &uart0; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; + spi0 = &qspi; }; cpus { @@ -908,7 +909,9 @@ qspi: qspi@47900000 { compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>; + reg = <0x47900000 0x100>, + <0x30000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts index 3f9d808091..89feaf3eb7 100644 --- a/arch/arm/dts/am437x-sk-evm.dts +++ b/arch/arm/dts/am437x-sk-evm.dts @@ -567,7 +567,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "mx66l51235l"; + compatible = "mx66l51235l","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-cpol; diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi index a718866ba5..0b2a78d393 100644 --- a/arch/arm/dts/armada-370-xp.dtsi +++ b/arch/arm/dts/armada-370-xp.dtsi @@ -141,6 +141,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + u-boot,dm-pre-reloc; rtc@10300 { compatible = "marvell,orion-rtc"; diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts new file mode 100644 index 0000000000..b2dfd56435 --- /dev/null +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -0,0 +1,509 @@ +/* + * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828) + * + * Copyright (C) 2015 Russell King + * + * This board is in development; the contents of this file work with + * the A1 rev 2.0 of the board, which does not represent final + * production board. Things will change, don't expect this file to + * remain compatible info the future. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-388.dtsi" + +/ { + model = "SolidRun Clearfog A1"; + compatible = "solidrun,clearfog-a1", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + ethernet2 = ð1; + ethernet3 = ð2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; + + internal-regs { + ethernet@30000 { + mac-address = [00 50 43 02 02 02]; + phy-mode = "sgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@34000 { + mac-address = [00 50 43 02 02 03]; + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; + }; + + ethernet@70000 { + mac-address = [00 50 43 02 02 01]; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy_dedicated>; + phy-mode = "rgmii-id"; + status = "okay"; + }; + + i2c@11000 { + /* Is there anything on this? */ + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * PCA9655 GPIO expander, up to 1MHz clock. + * 0-CON3 CLKREQ# + * 1-CON3 PERST# + * 2-CON2 PERST# + * 3-CON3 W_DISABLE + * 4-CON2 CLKREQ# + * 5-USB3 overcurrent + * 6-USB3 power + * 7-CON2 W_DISABLE + * 8-JP4 P1 + * 9-JP4 P4 + * 10-JP4 P5 + * 11-m.2 DEVSLP + * 12-SFP_LOS + * 13-SFP_TX_FAULT + * 14-SFP_TX_DISABLE + * 15-SFP_MOD_DEF0 + */ + expander0: gpio-expander@20 { + /* + * This is how it should be: + * compatible = "onnn,pca9655", + * "nxp,pca9555"; + * but you can't do this because of + * the way I2C works. + */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + + pcie1_0_clkreq { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie1.0-clkreq"; + }; + pcie1_0_w_disable { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie1.0-w-disable"; + }; + pcie2_0_clkreq { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie2.0-clkreq"; + }; + pcie2_0_w_disable { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie2.0-w-disable"; + }; + usb3_ilimit { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + input; + line-name = "usb3-current-limit"; + }; + usb3_power { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb3-power"; + }; + m2_devslp { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "m.2 devslp"; + }; + }; + + /* The MCP3021 is 100kHz clock only */ + mikrobus_adc: mcp3021@4c { + compatible = "microchip,mcp3021"; + reg = <0x4c>; + }; + + /* Also something at 0x64 */ + }; + + i2c@11100 { + /* + * Routed to SFP, mikrobus, and PCIe. + * SFP limits this to 100kHz, and requires + * an AT24C01A/02/04 with address pins tied + * low, which takes addresses 0x50 and 0x51. + * Mikrobus doesn't specify beyond an I2C + * bus being present. + * PCIe uses ARP to assign addresses, or + * 0x63-0x64. + */ + clock-frequency = <100000>; + pinctrl-0 = <&clearfog_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + mdio@72004 { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + phy_dedicated: ethernet-phy@0 { + /* + * Annoyingly, the marvell phy driver + * configures the LED register, rather + * than preserving reset-loaded setting. + * We undo that rubbish here. + */ + marvell,reg-init = <3 16 0 0x101e>; + reg = <0>; + }; + }; + + pinctrl@18000 { + clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { + marvell,pins = "mpp46"; + marvell,function = "ref"; + }; + clearfog_dsa0_pins: clearfog-dsa0-pins { + marvell,pins = "mpp23", "mpp41"; + marvell,function = "gpio"; + }; + clearfog_i2c1_pins: i2c1-pins { + /* SFP, PCIe, mSATA, mikrobus */ + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + clearfog_sdhci_pins: clearfog-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + clearfog_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp55"; + marvell,function = "spi1"; + }; + mikro_pins: mikro-pins { + /* int: mpp22 rst: mpp29 */ + marvell,pins = "mpp22", "mpp29"; + marvell,function = "gpio"; + }; + mikro_spi_pins: mikro-spi-pins { + marvell,pins = "mpp43"; + marvell,function = "spi1"; + }; + mikro_uart_pins: mikro-uart-pins { + marvell,pins = "mpp24", "mpp25"; + marvell,function = "ua1"; + }; + rear_button_pins: rear-button-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + }; + + rtc@a3800 { + /* + * If the rtc doesn't work, run "date reset" + * twice in u-boot. + */ + status = "okay"; + }; + + sata@a8000 { + /* pinctrl? */ + status = "okay"; + }; + + sata@e0000 { + /* pinctrl? */ + status = "okay"; + }; + + sdhci@d8000 { + bus-width = <4>; + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <&clearfog_sdhci_pins + &clearfog_sdhci_cd_pins>; + pinctrl-names = "default"; + status = "okay"; + vmmc = <®_3p3v>; + wp-inverted; + }; + + serial@12000 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + serial@12100 { + /* mikrobus uart */ + pinctrl-0 = <&mikro_uart_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + spi@10680 { + /* + * We don't seem to have the W25Q32 on the + * A1 Rev 2.0 boards, so disable SPI. + * CS0: W25Q32 (doesn't appear to be present) + * CS1: + * CS2: mikrobus + */ + pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; + pinctrl-names = "default"; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; + status = "disabled"; + }; + }; + + usb3@f8000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * the mini-PCIe connectors on the board. + */ + pcie@2,0 { + /* Port 1, Lane 0. CONN3, nearest power. */ + reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + pcie@3,0 { + /* Port 2, Lane 0. CONN2, nearest CPU. */ + reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; + moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; + sfp,ethernet = <ð2>; + tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; + }; + + dsa@0 { + compatible = "marvell,dsa"; + dsa,ethernet = <ð1>; + dsa,mii-bus = <&mdio>; + pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; + pinctrl-names = "default"; + #address-cells = <2>; + #size-cells = <0>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4 0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "lan5"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + + port@6 { + /* 88E1512 external phy */ + reg = <6>; + label = "lan6"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&rear_button_pins>; + pinctrl-names = "default"; + + button_0 { + /* The rear SW3 button */ + label = "Rear Button"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = <BTN_0>; + }; + }; +}; + +/* ++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 +MPP18: gpio ? (pca9655 int?) +MPP19: gpio ? (clkreq?) +MPP20: gpio ? (sd0 detect) +MPP21: sd0:cmd x sd0 +MPP22: gpio x mikro int +MPP23: gpio x switch irq ++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333 +MPP24: ua1:rxd x mikro rx +MPP25: ua1:txd x mikro tx +MPP26: i2c1:sck x mikro sck +MPP27: i2c1:sda x mikro sda +MPP28: sd0:clk x sd0 +MPP29: gpio x mikro rst +MPP30: ge1:txd2 ? (config) +MPP31: ge1:txd3 ? (config) ++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002 +MPP32: ge1:txctl ? (unused) +MPP33: gpio ? (pic_com0) +MPP34: gpio x rear button (pic_com1) +MPP35: gpio ? (pic_com2) +MPP36: gpio ? (unused) +MPP37: sd0:d3 x sd0 +MPP38: sd0:d0 x sd0 +MPP39: sd0:d1 x sd0 ++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004 +MPP40: sd0:d2 x sd0 +MPP41: gpio x switch reset +MPP42: gpio ? sw1-1 +MPP43: spi1:cs2 x mikro cs +MPP44: sata3:prsnt ? (unused) +MPP45: ref:clk_out0 ? +MPP46: ref:clk_out1 x switch clk +MPP47: 4 ? (unused) ++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333 +MPP48: tdm:pclk +MPP49: tdm:fsync +MPP50: tdm:drx +MPP51: tdm:dtx +MPP52: tdm:int +MPP53: tdm:rst +MPP54: gpio ? (pwm) +MPP55: spi1:cs1 x slic ++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444 +MPP56: spi1:mosi x mikro mosi +MPP57: spi1:sck x mikro sck +MPP58: spi1:miso x mikro miso +MPP59: spi1:cs0 x w25q32 +*/ diff --git a/arch/arm/dts/armada-388-gp.dts b/arch/arm/dts/armada-388-gp.dts index fd4f6fd8a2..7bc878f5a9 100644 --- a/arch/arm/dts/armada-388-gp.dts +++ b/arch/arm/dts/armada-388-gp.dts @@ -51,6 +51,12 @@ stdout-path = "serial0:115200n8"; }; + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + spi0 = &spi0; + }; + memory { device_type = "memory"; reg = <0x00000000 0x80000000>; /* 2 GB */ @@ -65,8 +71,10 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; status = "okay"; + u-boot,dm-pre-reloc; spi-flash@0 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; @@ -122,6 +130,7 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; + u-boot,dm-pre-reloc; }; /* GE1 CON15 */ diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index 04ecfe6e2b..dc8a1a66c1 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -70,6 +70,7 @@ soc { compatible = "marvell,armada380-mbus", "simple-bus"; + u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <1>; controller = <&mbusc>; @@ -134,6 +135,7 @@ internal-regs { compatible = "simple-bus"; + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-gp.dts index bf724ca96a..27799d1254 100644 --- a/arch/arm/dts/armada-xp-gp.dts +++ b/arch/arm/dts/armada-xp-gp.dts @@ -68,6 +68,10 @@ stdout-path = "serial0:115200n8"; }; + aliases { + spi0 = &spi0; + }; + memory { device_type = "memory"; /* @@ -148,6 +152,7 @@ internal-regs { serial@12000 { status = "okay"; + u-boot,dm-pre-reloc; }; serial@12100 { status = "okay"; @@ -223,8 +228,10 @@ spi0: spi@10600 { status = "okay"; + u-boot,dm-pre-reloc; spi-flash@0 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/dts/armada-xp-maxbcm.dts b/arch/arm/dts/armada-xp-maxbcm.dts new file mode 100644 index 0000000000..d7d7f65c85 --- /dev/null +++ b/arch/arm/dts/armada-xp-maxbcm.dts @@ -0,0 +1,249 @@ +/* + * Device Tree file for Marvell Armada XP maxbcm board + * + * Copyright (C) 2013-2014 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78460.dtsi" + +/ { + model = "Marvell Armada XP MAXBCM"; + compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + /* + * 8 GB of plug-in RAM modules by default.The amount + * of memory available can be changed by the + * bootloader according the size of the module + * actually plugged. However, memory between + * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is + * the address range used for I/O (internal registers, + * MBus windows). + */ + reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, + <0x00000001 0x00000000 0x00000001 0x00000000>; + }; + + cpus { + pm_pic { + ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, + <&gpio0 17 GPIO_ACTIVE_LOW>, + <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + serial@12000 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + serial@12100 { + status = "okay"; + }; + serial@12200 { + status = "okay"; + }; + serial@12300 { + status = "okay"; + }; + pinctrl { + pinctrl-0 = <&pic_pins>; + pinctrl-names = "default"; + pic_pins: pic-pins-0 { + marvell,pins = "mpp16", "mpp17", + "mpp18"; + marvell,function = "gpio"; + }; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; + }; + + /* Front-side USB slot */ + usb@50000 { + status = "okay"; + }; + + /* Back-side USB slot */ + usb@51000 { + status = "okay"; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-xp-synology-ds414.dts b/arch/arm/dts/armada-xp-synology-ds414.dts new file mode 100644 index 0000000000..0a60ddfa41 --- /dev/null +++ b/arch/arm/dts/armada-xp-synology-ds414.dts @@ -0,0 +1,337 @@ +/* + * Device Tree file for Synology DS414 + * + * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the old 0xd0000000). + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot + * bootloaders provided by Marvell. It is used in recent versions of + * DSM software provided by Synology. Nonetheless, some earlier boards + * were delivered with an older version of u-boot that left internal + * registers mapped at 0xd0000000. If you have such a device you will + * not be able to directly boot a kernel based on this Device Tree. In + * that case, the preferred solution is to update your bootloader (e.g. + * by upgrading to latest version of DSM, or building a new one and + * installing it from u-boot prompt) or adjust the Devive Tree + * (s/0xf1000000/0xd0000000/ in 'ranges' below). + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Synology DS414"; + compatible = "synology,ds414", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + + /* RTC is provided by Seiko S-35390A below */ + rtc@10300 { + status = "disabled"; + }; + + spi0: spi@10600 { + status = "okay"; + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000d0000>; /* 832KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000d0000 0x002d0000>; /* 2880KB */ + }; + + partition@003a0000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x003a0000 0x00430000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; + }; + + i2c@11000 { + clock-frequency = <400000>; + status = "okay"; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + /* Connected to a header on device's PCB. This + * provides the main console for the device. + * + * Warning: the device may not boot with a 3.3V + * USB-serial converter connected when the power + * button is pressed. The converter needs to be + * connected a few seconds after pressing the + * power button. This is possibly due to UART0_TXD + * pin being sampled at reset (bit 0 of SAR). + */ + serial@12000 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + + /* Connected to a Microchip PIC16F883 for power control */ + serial@12100 { + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&coreclk 0>; + }; + + /* Front USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin + &sata3_pwr_pin &sata4_pwr_pin>; + pinctrl-names = "default"; + + sata1_regulator: sata1-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + sata2_regulator: sata2-regulator { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + sata3_regulator: sata3-regulator { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "SATA3 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <6000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + + sata4_regulator: sata4-regulator { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "SATA4 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <8000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + sata1_pwr_pin: sata1-pwr-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + sata2_pwr_pin: sata2-pwr-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata3_pwr_pin: sata3-pwr-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + sata4_pwr_pin: sata4-pwr-pin { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + syno_id_bit0_pin: syno-id-bit0-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + syno_id_bit1_pin: syno-id-bit1-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + syno_id_bit2_pin: syno-id-bit2-pin { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + fan1_alarm_pin: fan1-alarm-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + fan2_alarm_pin: fan2-alarm-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi index 3de9b761cc..3fac39e41d 100644 --- a/arch/arm/dts/armada-xp.dtsi +++ b/arch/arm/dts/armada-xp.dtsi @@ -63,6 +63,7 @@ soc { compatible = "marvell,armadaxp-mbus", "simple-bus"; + u-boot,dm-pre-reloc; bootrom { compatible = "marvell,bootrom"; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index e4daa991e9..797d411d6f 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -487,7 +487,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index feb3708dc6..e7fecf7656 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -41,6 +41,7 @@ ethernet1 = &cpsw_emac1; d_can0 = &dcan1; d_can1 = &dcan2; + spi0 = &qspi; }; timer { @@ -1113,8 +1114,11 @@ qspi: qspi@4b300000 { compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>; - reg-names = "qspi_base"; + reg = <0x4b300000 0x100>, + <0x5c000000 0x4000000>, + <0x4a002558 0x4>; + reg-names = "qspi_base", "qspi_mmap", + "qspi_ctrlmod"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index efb544c6bb..a62550f0e0 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -604,7 +604,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/thunderx-88xx.dts b/arch/arm/dts/thunderx-88xx.dts new file mode 100644 index 0000000000..08f267879f --- /dev/null +++ b/arch/arm/dts/thunderx-88xx.dts @@ -0,0 +1,31 @@ +/* + * Cavium Thunder DTS file - Thunder board description + * + * Copyright (C) 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + */ + +/dts-v1/; + +/include/ "thunderx-88xx.dtsi" + +/ { + model = "Cavium ThunderX CN88XX board"; + compatible = "cavium,thunder-88xx"; + + aliases { + serial0 = &uaa0; + serial1 = &uaa1; + }; + + chosen { + stdout-path = &uaa0; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x80000000>; + }; +}; diff --git a/arch/arm/dts/thunderx-88xx.dtsi b/arch/arm/dts/thunderx-88xx.dtsi new file mode 100644 index 0000000000..6e9230b035 --- /dev/null +++ b/arch/arm/dts/thunderx-88xx.dtsi @@ -0,0 +1,363 @@ +/* + * Cavium Thunder DTS file - Thunder SoC description + * + * Copyright (C) 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + */ + +/ { + compatible = "cavium,thunder-88xx"; + interrupt-parent = <&gic0>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@000 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + }; + cpu@001 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "psci"; + }; + cpu@002 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "psci"; + }; + cpu@003 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "psci"; + }; + cpu@004 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x004>; + enable-method = "psci"; + }; + cpu@005 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x005>; + enable-method = "psci"; + }; + cpu@006 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x006>; + enable-method = "psci"; + }; + cpu@007 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x007>; + enable-method = "psci"; + }; + cpu@008 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x008>; + enable-method = "psci"; + }; + cpu@009 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x009>; + enable-method = "psci"; + }; + cpu@00a { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00a>; + enable-method = "psci"; + }; + cpu@00b { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00b>; + enable-method = "psci"; + }; + cpu@00c { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00c>; + enable-method = "psci"; + }; + cpu@00d { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00d>; + enable-method = "psci"; + }; + cpu@00e { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00e>; + enable-method = "psci"; + }; + cpu@00f { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00f>; + enable-method = "psci"; + }; + cpu@100 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + cpu@101 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + cpu@102 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + cpu@103 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + cpu@104 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x104>; + enable-method = "psci"; + }; + cpu@105 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x105>; + enable-method = "psci"; + }; + cpu@106 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x106>; + enable-method = "psci"; + }; + cpu@107 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x107>; + enable-method = "psci"; + }; + cpu@108 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x108>; + enable-method = "psci"; + }; + cpu@109 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x109>; + enable-method = "psci"; + }; + cpu@10a { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10a>; + enable-method = "psci"; + }; + cpu@10b { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10b>; + enable-method = "psci"; + }; + cpu@10c { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10c>; + enable-method = "psci"; + }; + cpu@10d { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10d>; + enable-method = "psci"; + }; + cpu@10e { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10e>; + enable-method = "psci"; + }; + cpu@10f { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10f>; + enable-method = "psci"; + }; + cpu@200 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + cpu@201 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + }; + cpu@202 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x202>; + enable-method = "psci"; + }; + cpu@203 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x203>; + enable-method = "psci"; + }; + cpu@204 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x204>; + enable-method = "psci"; + }; + cpu@205 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x205>; + enable-method = "psci"; + }; + cpu@206 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x206>; + enable-method = "psci"; + }; + cpu@207 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x207>; + enable-method = "psci"; + }; + cpu@208 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x208>; + enable-method = "psci"; + }; + cpu@209 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x209>; + enable-method = "psci"; + }; + cpu@20a { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20a>; + enable-method = "psci"; + }; + cpu@20b { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20b>; + enable-method = "psci"; + }; + cpu@20c { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20c>; + enable-method = "psci"; + }; + cpu@20d { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20d>; + enable-method = "psci"; + }; + cpu@20e { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20e>; + enable-method = "psci"; + }; + cpu@20f { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20f>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + + gic0: interrupt-controller@8010,00000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ + <0x8010 0x80000000 0x0 0x600000>; /* GICR */ + interrupts = <1 9 0xf04>; + }; + + uaa0: serial@87e0,24000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x24000000 0x0 0x1000>; + interrupts = <1 21 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + uboot,skip-init; + }; + + uaa1: serial@87e0,25000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x25000000 0x0 0x1000>; + interrupts = <1 22 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + uboot,skip-init; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index d76514e4cb..3b7f6bdb72 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -16,35 +16,21 @@ #define CONFIG_NR_DRAM_BANKS_MAX 2 /* UART configuration */ -#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) -#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ +#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ (CONFIG_SYS_LPC32XX_UART == 7) +#if !defined(CONFIG_LPC32XX_HSUART) #define CONFIG_LPC32XX_HSUART -#else -#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" #endif - -#if defined(CONFIG_SYS_NS16550_SERIAL) - -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_NS16550_COM1 UART3_BASE -#define CONFIG_SYS_NS16550_COM2 UART4_BASE -#define CONFIG_SYS_NS16550_COM3 UART5_BASE -#define CONFIG_SYS_NS16550_COM4 UART6_BASE #endif -#if defined(CONFIG_LPC32XX_HSUART) -#if CONFIG_SYS_LPC32XX_UART == 1 -#define HS_UART_BASE HS_UART1_BASE -#elif CONFIG_SYS_LPC32XX_UART == 2 -#define HS_UART_BASE HS_UART2_BASE -#else /* CONFIG_SYS_LPC32XX_UART == 7 */ -#define HS_UART_BASE HS_UART7_BASE +#if !defined(CONFIG_SYS_NS16550_CLK) +#define CONFIG_SYS_NS16550_CLK 13000000 #endif + +#if !defined(CONFIG_LPC32XX_HSUART) +#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) +#else +#define CONFIG_CONS_INDEX CONFIG_SYS_LPC32XX_UART #endif #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h index 984c8b9f7f..48ba622ed1 100644 --- a/arch/arm/include/asm/arch-omap4/ehci.h +++ b/arch/arm/include/asm/arch-omap4/ehci.h @@ -6,17 +6,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com * Author: Govindraj R <govindraj.raja@ti.com> * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 of - * the License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _OMAP4_EHCI_H_ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h index 9d447abb96..28f483c459 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h @@ -2,18 +2,7 @@ * Copyright (C) 2011 Renesas Solutions Corp. * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_R8A7740_H__ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740.h b/arch/arm/include/asm/arch-rmobile/r8a7740.h index 8f179505d0..989da337fe 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7740.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7740.h @@ -1,19 +1,7 @@ /* * Copyright (C) 2012 Renesas Solutions Corp. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ARCH_R8A7740_H diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 63b161ab03..0cdefdcdf4 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -134,6 +134,7 @@ #define SUNXI_RTC_BASE 0x01f00000 #define SUNXI_PRCM_BASE 0x01f01400 #define SUN6I_CPUCFG_BASE 0x01f01c00 +#define SUNXI_R_TWI_BASE 0x01f02400 #define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 #define SUN6I_P2WI_BASE 0x01f03400 diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index a2a9a38dbe..649f6cd840 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -199,6 +199,8 @@ enum sunxi_gpio_number { #define SUN6I_GPL1_R_P2WI_SDA 3 #define SUN8I_GPL_R_RSB 2 +#define SUN8I_H3_GPL_R_TWI 2 +#define SUN8I_A23_GPL_R_TWI 3 #define SUN8I_GPL_R_UART 2 #define SUN9I_GPN_R_RSB 3 diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 561cd2be16..4dfd313f1a 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -23,6 +23,9 @@ #ifdef CONFIG_I2C4_ENABLE #define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE #endif +#ifdef CONFIG_R_I2C_ENABLE +#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE +#endif /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ #define CONFIG_SYS_TCLK 24000000 diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 82ed541e91..556c1af600 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -236,5 +236,7 @@ struct sunxi_prcm_reg { }; void prcm_apb0_enable(u32 flags); +void prcm_apb0_disable(u32 flags); + #endif /* __ASSEMBLY__ */ #endif /* _PRCM_H */ diff --git a/arch/arm/include/asm/arch-tegra/funcmux.h b/arch/arm/include/asm/arch-tegra/funcmux.h index f101e5ef6a..d9bcf605c7 100644 --- a/arch/arm/include/asm/arch-tegra/funcmux.h +++ b/arch/arm/include/asm/arch-tegra/funcmux.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra high-level function multiplexing */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index eeeb247d5d..341df74d77 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -3,23 +3,7 @@ * * Copyright 2010-2011 NVIDIA Corporation * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA_I2C_H_ diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index 3f910f5ae8..d4511817fa 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra114 clock PLL tables */ diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h index 9bee397787..4d58bf1842 100644 --- a/arch/arm/include/asm/arch-tegra114/clock.h +++ b/arch/arm/include/asm/arch-tegra114/clock.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra114 clock control functions */ diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/include/asm/arch-tegra114/flow.h index c7eb051c77..2e4045fc72 100644 --- a/arch/arm/include/asm/arch-tegra114/flow.h +++ b/arch/arm/include/asm/arch-tegra114/flow.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_FLOW_H_ diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h index 7f48f2510f..9c62cc39d5 100644 --- a/arch/arm/include/asm/arch-tegra114/funcmux.h +++ b/arch/arm/include/asm/arch-tegra114/funcmux.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra114 high-level function multiplexing */ diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h index 41ce677807..21fa4f2d42 100644 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_GP_PADCTRL_H_ diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h index 21853b6eb5..d6eaa1bd40 100644 --- a/arch/arm/include/asm/arch-tegra114/gpio.h +++ b/arch/arm/include/asm/arch-tegra114/gpio.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_GPIO_H_ diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h index c6e2381011..3104a1b855 100644 --- a/arch/arm/include/asm/arch-tegra114/pmu.h +++ b/arch/arm/include/asm/arch-tegra114/pmu.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_PMU_H_ diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h index c05e2c3281..38220aac8e 100644 --- a/arch/arm/include/asm/arch-tegra114/sysctr.h +++ b/arch/arm/include/asm/arch-tegra114/sysctr.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_SYSCTR_H_ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index c3d061ec58..f8407d178b 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA114_H_ diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h index 37998a4d60..d97b2c87c6 100644 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA124_MC_H_ diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h index f7c7af80fa..16b4b96330 100644 --- a/arch/arm/include/asm/arch-tegra30/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra30 clock PLL tables */ diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h index 410c352899..46cd7d8e01 100644 --- a/arch/arm/include/asm/arch-tegra30/clock.h +++ b/arch/arm/include/asm/arch-tegra30/clock.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra30 clock control functions */ diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/include/asm/arch-tegra30/flow.h index f5966a8074..73cb0eecdc 100644 --- a/arch/arm/include/asm/arch-tegra30/flow.h +++ b/arch/arm/include/asm/arch-tegra30/flow.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_FLOW_H_ diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h index 24b2bca03a..ae6236273f 100644 --- a/arch/arm/include/asm/arch-tegra30/funcmux.h +++ b/arch/arm/include/asm/arch-tegra30/funcmux.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra30 high-level function multiplexing */ diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h index 23d184f2dd..1c5017686c 100644 --- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_GP_PADCTRL_H_ diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h index f1c89f5a86..d2c6c78e08 100644 --- a/arch/arm/include/asm/arch-tegra30/gpio.h +++ b/arch/arm/include/asm/arch-tegra30/gpio.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_GPIO_H_ diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h index 52bea29bbc..f01c37ed67 100644 --- a/arch/arm/include/asm/arch-tegra30/pmu.h +++ b/arch/arm/include/asm/arch-tegra30/pmu.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_PMU_H_ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index 93671793a9..280245e98e 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _TEGRA30_H_ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 2e2a3a8226..897f010207 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -21,7 +21,13 @@ * The following definitions are related each other, shoud be * calculated specifically. */ + +#ifndef CONFIG_SYS_FULL_VA #define VA_BITS (42) /* 42 bits virtual address */ +#else +#define VA_BITS CONFIG_SYS_VA_BITS +#define PTL2_BITS CONFIG_SYS_PTL2_BITS +#endif /* PAGE_SHIFT determines the page size */ #undef PAGE_SIZE @@ -30,11 +36,18 @@ #define PAGE_MASK (~(PAGE_SIZE-1)) /* - * section address mask and size definitions. + * block/section address mask and size definitions. */ +#ifndef CONFIG_SYS_FULL_VA #define SECTION_SHIFT 29 #define SECTION_SIZE (UL(1) << SECTION_SHIFT) #define SECTION_MASK (~(SECTION_SIZE-1)) +#else +#define BLOCK_SHIFT CONFIG_SYS_BLOCK_SHIFT +#define BLOCK_SIZE (UL(1) << BLOCK_SHIFT) +#define BLOCK_MASK (~(BLOCK_SIZE-1)) +#endif + /***************************************************************/ /* @@ -46,15 +59,54 @@ #define MT_NORMAL_NC 3 #define MT_NORMAL 4 -#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \ - (0x04 << (MT_DEVICE_NGNRE*8)) | \ - (0x0c << (MT_DEVICE_GRE*8)) | \ - (0x44 << (MT_NORMAL_NC*8)) | \ - (UL(0xff) << (MT_NORMAL*8))) +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ + (0x04 << (MT_DEVICE_NGNRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (UL(0xff) << (MT_NORMAL * 8))) /* * Hardware page table definitions. * + */ + +#ifdef CONFIG_SYS_FULL_VA +/* + * Level 1 descriptor (PGD). + */ + +#define PTL1_TYPE_MASK (3 << 0) +#define PTL1_TYPE_TABLE (3 << 0) + +#define PTL1_TABLE_PXN (1UL << 59) +#define PTL1_TABLE_XN (1UL << 60) +#define PTL1_TABLE_AP (1UL << 61) +#define PTL1_TABLE_NS (1UL << 63) + + +/* + * Level 2 descriptor (PMD). + */ + +#define PTL2_TYPE_MASK (3 << 0) +#define PTL2_TYPE_FAULT (0 << 0) +#define PTL2_TYPE_TABLE (3 << 0) +#define PTL2_TYPE_BLOCK (1 << 0) + +/* + * Block + */ +#define PTL2_MEMTYPE(x) ((x) << 2) +#define PTL2_BLOCK_NON_SHARE (0 << 8) +#define PTL2_BLOCK_OUTER_SHARE (2 << 8) +#define PTL2_BLOCK_INNER_SHARE (3 << 8) +#define PTL2_BLOCK_AF (1 << 10) +#define PTL2_BLOCK_NG (1 << 11) +#define PTL2_BLOCK_PXN (UL(1) << 53) +#define PTL2_BLOCK_UXN (UL(1) << 54) + +#else +/* * Level 2 descriptor (PMD). */ #define PMD_TYPE_MASK (3 << 0) @@ -74,6 +126,8 @@ #define PMD_SECT_PXN (UL(1) << 53) #define PMD_SECT_UXN (UL(1) << 54) +#endif + /* * AttrIndx[2:0] */ @@ -100,9 +154,16 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) + +#ifndef CONFIG_SYS_FULL_VA #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ +#else +#define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS +#define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS +#define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS +#endif /* PTWs cacheable, inner/outer WBWA and inner shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ @@ -116,6 +177,7 @@ #define TCR_EL3_RSVD (1 << 31 | 1 << 23) #ifndef __ASSEMBLY__ +#ifndef CONFIG_SYS_FULL_VA void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, @@ -123,6 +185,7 @@ void set_pgtable_section(u64 *page_table, u64 index, void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr); +#endif static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); @@ -143,5 +206,12 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) } asm volatile("isb"); } + +struct mm_region { + u64 base; + u64 size; + u64 attrs; +}; #endif + #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 34c07fe500..9b79506b59 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -32,7 +32,7 @@ typedef struct { volatile int counter; } atomic_t; static inline void atomic_add(int i, volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); v->counter += i; @@ -41,7 +41,7 @@ static inline void atomic_add(int i, volatile atomic_t *v) static inline void atomic_sub(int i, volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); v->counter -= i; @@ -50,7 +50,7 @@ static inline void atomic_sub(int i, volatile atomic_t *v) static inline void atomic_inc(volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); v->counter += 1; @@ -59,7 +59,7 @@ static inline void atomic_inc(volatile atomic_t *v) static inline void atomic_dec(volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); v->counter -= 1; @@ -68,7 +68,7 @@ static inline void atomic_dec(volatile atomic_t *v) static inline int atomic_dec_and_test(volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; int val; local_irq_save(flags); @@ -81,7 +81,7 @@ static inline int atomic_dec_and_test(volatile atomic_t *v) static inline int atomic_add_negative(int i, volatile atomic_t *v) { - unsigned long flags; + unsigned long flags = 0; int val; local_irq_save(flags); @@ -94,7 +94,7 @@ static inline int atomic_add_negative(int i, volatile atomic_t *v) static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) { - unsigned long flags; + unsigned long flags = 0; local_irq_save(flags); *addr &= ~mask; diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index d479a38291..f33efeb33e 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -51,7 +51,7 @@ static inline int __test_and_set_bit(int nr, volatile void *addr) static inline int test_and_set_bit(int nr, volatile void * addr) { - unsigned long flags; + unsigned long flags = 0; int out; local_irq_save(flags); @@ -73,7 +73,7 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr) static inline int test_and_clear_bit(int nr, volatile void * addr) { - unsigned long flags; + unsigned long flags = 0; int out; local_irq_save(flags); diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index c7bca05682..5a53e403a6 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -6,17 +6,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com* * Author: Govindraj R <govindraj.raja@ti.com> * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 of - * the License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _OMAP_COMMON_EHCI_H_ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index bd27281e79..dcfa0985b5 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -38,6 +38,9 @@ struct arch_global_data { unsigned long long timer_reset_value; #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; +#if defined(CONFIG_SYS_FULL_VA) + unsigned long pmd_addr[CONFIG_SYS_PTL1_ENTRIES]; +#endif unsigned long tlb_size; #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 71b31085b4..67cbbc2610 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -1,6 +1,9 @@ #ifndef __ASM_ARM_SYSTEM_H #define __ASM_ARM_SYSTEM_H +#include <common.h> +#include <linux/compiler.h> + #ifdef CONFIG_ARM64 /* @@ -14,7 +17,12 @@ #define CR_WXN (1 << 19) /* Write Permision Imply XN */ #define CR_EE (1 << 25) /* Exception (Big) Endian */ +#ifndef CONFIG_SYS_FULL_VA #define PGTABLE_SIZE (0x10000) +#else +#define PGTABLE_SIZE CONFIG_SYS_PGTABLE_SIZE +#endif + /* 2MB granularity */ #define MMU_SECTION_SHIFT 21 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) @@ -72,6 +80,17 @@ static inline void set_sctlr(unsigned int val) asm volatile("isb"); } +static inline unsigned long read_mpidr(void) +{ + unsigned long val; + + asm volatile("mrs %0, mpidr_el1" : "=r" (val)); + + return val; +} + +#define BSP_COREID 0 + void __asm_flush_dcache_all(void); void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); @@ -89,6 +108,24 @@ void smp_kick_all_cpus(void); void flush_l3_cache(void); +/* + *Issue a hypervisor call in accordance with ARM "SMC Calling convention", + * DEN0028A + * + * @args: input and output arguments + * + */ +void hvc_call(struct pt_regs *args); + +/* + *Issue a secure monitor call in accordance with ARM "SMC Calling convention", + * DEN0028A + * + * @args: input and output arguments + * + */ +void smc_call(struct pt_regs *args); + #endif /* __ASSEMBLY__ */ #else /* CONFIG_ARM64 */ @@ -137,7 +174,9 @@ void flush_l3_cache(void); #define CR_AFE (1 << 29) /* Access flag enable */ #define CR_TE (1 << 30) /* Thumb exception enable */ +#ifndef PGTABLE_SIZE #define PGTABLE_SIZE (4096 * 4) +#endif /* * This is used to ensure the compiler did actually allocate the register we diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 80548ebbf6..2f4c14e96b 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -83,8 +83,11 @@ ENTRY(_main) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #endif mov r0, sp - bl board_init_f_mem + bl board_init_f_alloc_reserve mov sp, r0 + /* set up gd here, outside any C code */ + mov r9, r0 + bl board_init_f_init_reserve mov r0, #0 bl board_init_f @@ -133,6 +136,7 @@ here: bl spl_relocate_stack_gd cmp r0, #0 movne sp, r0 + movne r9, r0 # endif ldr r0, =__bss_start /* this is auto-relocated! */ diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index cef1c7171c..cad22c7b41 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -75,8 +75,12 @@ ENTRY(_main) ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - bl board_init_f_mem + mov x0, sp + bl board_init_f_alloc_reserve mov sp, x0 + /* set up gd here, outside any C code */ + mov x18, x0 + bl board_init_f_init_reserve mov x0, #0 bl board_init_f diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index e90d3bba1f..d2d366ba4f 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -4,14 +4,7 @@ * See file CREDITS for list of people who contributed to this * project. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-bcm283x/lowlevel_init.S b/arch/arm/mach-bcm283x/lowlevel_init.S index c7b0843281..965de1dc7c 100644 --- a/arch/arm/mach-bcm283x/lowlevel_init.S +++ b/arch/arm/mach-bcm283x/lowlevel_init.S @@ -4,14 +4,7 @@ * See file CREDITS for list of people who contributed to this * project. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ .globl lowlevel_init diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c index 8c37ad9fd4..72cdc31d87 100644 --- a/arch/arm/mach-bcm283x/reset.c +++ b/arch/arm/mach-bcm283x/reset.c @@ -4,14 +4,7 @@ * See file CREDITS for list of people who contributed to this * project. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index d049395036..0c4309ff00 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -135,4 +135,9 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif +/* Use common timer */ +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK + #endif /* _KW_CONFIG_H */ diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 79ff0e8278..b9628462ea 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -1,31 +1,74 @@ if ARCH_MVEBU +config ARMADA_38X + bool + +config ARMADA_XP + bool + +config MV78230 + bool + select ARMADA_XP + +config MV78260 + bool + select ARMADA_XP + +config MV78460 + bool + select ARMADA_XP + +config DB_88F6820_GP + bool + select ARMADA_38X + choice prompt "Marvell MVEBU (Armada XP/38x) board select" optional +config TARGET_CLEARFOG + bool "Support ClearFog" + select DB_88F6820_GP + config TARGET_DB_88F6820_GP bool "Support DB-88F6820-GP" + select DB_88F6820_GP config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" + select MV78460 + +config TARGET_DS414 + bool "Support Synology DS414" + select MV78230 config TARGET_MAXBCM bool "Support maxbcm" + select MV78460 endchoice -config SYS_SOC - default "mvebu" +config SYS_BOARD + default "clearfog" if TARGET_CLEARFOG + default "db-88f6820-gp" if TARGET_DB_88F6820_GP + default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP + default "ds414" if TARGET_DS414 + default "maxbcm" if TARGET_MAXBCM -config MVEBU_BOOTROM_UARTBOOT - bool "Use kwboot to boot via BootROM xmodem protocol" - help - This option provides support for booting via the Marvell - xmodem protocol, used by the kwboot tool. +config SYS_CONFIG_NAME + default "clearfog" if TARGET_CLEARFOG + default "db-88f6820-gp" if TARGET_DB_88F6820_GP + default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP + default "ds414" if TARGET_DS414 + default "maxbcm" if TARGET_MAXBCM - Please don't forget to configure the boot device in - the board specific kwbimage.cfg file this way: - BOOT_FROM uart +config SYS_VENDOR + default "Marvell" if TARGET_DB_MV784MP_GP + default "Marvell" if TARGET_DB_88F6820_GP + default "solidrun" if TARGET_CLEARFOG + default "Synology" if TARGET_DS414 + +config SYS_SOC + default "mvebu" endif diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 21c56a4d96..b96b81bd39 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -15,8 +15,8 @@ else obj-y = cpu.o obj-y += dram.o ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ../../../drivers/ddr/marvell/a38x/xor.o -obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ../../../drivers/ddr/marvell/axp/xor.o +obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o +obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o endif obj-y += gpio.o obj-y += mbus.o @@ -24,7 +24,7 @@ obj-y += timer.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o -obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += serdes/a38x/ -obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += serdes/axp/ +obj-$(CONFIG_ARMADA_38X) += serdes/a38x/ +obj-$(CONFIG_ARMADA_XP) += serdes/axp/ endif diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 895ad929b1..30b175c646 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <netdev.h> #include <ahci.h> #include <linux/mbus.h> #include <asm/io.h> @@ -50,25 +49,106 @@ int mvebu_soc_family(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; - if (devid == SOC_MV78460_ID) + switch (devid) { + case SOC_MV78230_ID: + case SOC_MV78260_ID: + case SOC_MV78460_ID: return MVEBU_SOC_AXP; - - if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || - devid == SOC_88F6828_ID) + case SOC_88F6810_ID: + case SOC_88F6820_ID: + case SOC_88F6828_ID: return MVEBU_SOC_A38X; - + } return MVEBU_SOC_UNKNOWN; } #if defined(CONFIG_DISPLAY_CPUINFO) + +#if defined(CONFIG_ARMADA_38X) +/* SAR frequency values for Armada 38x */ +static const struct sar_freq_modes sar_freq_tab[] = { + { 0x0, 0x0, 666, 333, 333 }, + { 0x2, 0x0, 800, 400, 400 }, + { 0x4, 0x0, 1066, 533, 533 }, + { 0x6, 0x0, 1200, 600, 600 }, + { 0x8, 0x0, 1332, 666, 666 }, + { 0xc, 0x0, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#else +/* SAR frequency values for Armada XP */ +static const struct sar_freq_modes sar_freq_tab[] = { + { 0xa, 0x5, 800, 400, 400 }, + { 0x1, 0x5, 1066, 533, 533 }, + { 0x2, 0x5, 1200, 600, 600 }, + { 0x2, 0x9, 1200, 600, 400 }, + { 0x3, 0x5, 1333, 667, 667 }, + { 0x4, 0x5, 1500, 750, 750 }, + { 0x4, 0x9, 1500, 750, 500 }, + { 0xb, 0x9, 1600, 800, 533 }, + { 0xb, 0xa, 1600, 800, 640 }, + { 0xb, 0x5, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#endif + +void get_sar_freq(struct sar_freq_modes *sar_freq) +{ + u32 val; + u32 freq; + int i; + + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; +#if !defined(CONFIG_ARMADA_38X) + /* + * Shift CPU0 clock frequency select bit from SAR2 register + * into correct position + */ + freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) + >> SAR2_CPU_FREQ_OFFS) << 3; +#endif + for (i = 0; sar_freq_tab[i].val != 0xff; i++) { + if (sar_freq_tab[i].val == freq) { +#if defined(CONFIG_ARMADA_38X) + *sar_freq = sar_freq_tab[i]; + return; +#else + int k; + u8 ffc; + + ffc = (val & SAR_FFC_FREQ_MASK) >> + SAR_FFC_FREQ_OFFS; + for (k = i; sar_freq_tab[k].ffc != 0xff; k++) { + if (sar_freq_tab[k].ffc == ffc) { + *sar_freq = sar_freq_tab[k]; + return; + } + } + i = k; +#endif + } + } + + /* SAR value not found, return 0 for frequencies */ + *sar_freq = sar_freq_tab[i - 1]; +} + int print_cpuinfo(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; + struct sar_freq_modes sar_freq; puts("SoC: "); switch (devid) { + case SOC_MV78230_ID: + puts("MV78230-"); + break; + case SOC_MV78260_ID: + puts("MV78260-"); + break; case SOC_MV78460_ID: puts("MV78460-"); break; @@ -89,13 +169,13 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_AXP) { switch (revid) { case 1: - puts("A0\n"); + puts("A0"); break; case 2: - puts("B0\n"); + puts("B0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } @@ -103,17 +183,20 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_A38X) { switch (revid) { case MV_88F68XX_Z1_ID: - puts("Z1\n"); + puts("Z1"); break; case MV_88F68XX_A0_ID: - puts("A0\n"); + puts("A0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } + get_sar_freq(&sar_freq); + printf(" at %d MHz\n", sar_freq.p_clk); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -199,10 +282,10 @@ static void setup_usb_phys(void) clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); /* Power up PLL and PHY channel */ - clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9)); + setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9)); /* Assert VCOCAL_START */ - clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21)); + setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21)); mdelay(1); @@ -211,18 +294,20 @@ static void setup_usb_phys(void) */ for (dev = 0; dev < 3; dev++) { - clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15)); + setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15)); /* Assert REG_RCAL_START in channel REG 1 */ - clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12)); + setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); udelay(40); - clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0); + clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); } } +/* + * This function is not called from the SPL U-Boot version + */ int arch_cpu_init(void) { -#if !defined(CONFIG_SPL_BUILD) struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; @@ -233,27 +318,26 @@ int arch_cpu_init(void) * still locked to cache. */ mmu_disable(); -#endif /* Linux expects the internal registers to be at 0xf1000000 */ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); set_cbar(SOC_REGS_PHY_BASE + 0xC000); -#if !defined(CONFIG_SPL_BUILD) /* * From this stage on, the SoC detection is working. As we have * configured the internal register base to the value used * in the macros / defines in the U-Boot header (soc.h). */ - /* - * To fully release / unlock this area from cache, we need - * to flush all caches and disable the L2 cache. - */ - icache_disable(); - dcache_disable(); - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -#endif + if (mvebu_soc_family() == MVEBU_SOC_A38X) { + /* + * To fully release / unlock this area from cache, we need + * to flush all caches and disable the L2 cache. + */ + icache_disable(); + dcache_disable(); + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + } /* * We need to call mvebu_mbus_probe() before calling @@ -326,30 +410,6 @@ int arch_misc_init(void) } #endif /* CONFIG_ARCH_MISC_INIT */ -#ifdef CONFIG_MVNETA -int cpu_eth_init(bd_t *bis) -{ - u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE, - MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE }; - u8 phy_addr[] = CONFIG_PHY_ADDR; - int i; - - /* - * Only Armada XP supports all 4 ethernet interfaces. A38x has - * slightly different base addresses for its 2-3 interfaces. - */ - if (mvebu_soc_family() != MVEBU_SOC_AXP) { - enet_base[1] = MVEBU_EGIGA2_BASE; - enet_base[2] = MVEBU_EGIGA3_BASE; - } - - for (i = 0; i < ARRAY_SIZE(phy_addr); i++) - mvneta_initialize(bis, enet_base[i], i, phy_addr[i]); - - return 0; -} -#endif - #ifdef CONFIG_MV_SDHCI int board_mmc_init(bd_t *bis) { @@ -413,20 +473,43 @@ void scsi_init(void) } #endif -#ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - - /* First disable L2 cache - may still be enable from BootROM */ - if (mvebu_soc_family() == MVEBU_SOC_A38X) - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - /* Avoid problem with e.g. neta ethernet driver */ invalidate_dcache_all(); /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } -#endif + +void v7_outer_cache_enable(void) +{ + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + u32 u; + + /* The L2 cache is already disabled at this point */ + + /* + * For Aurora cache in no outer mode, enable via the CP15 + * coprocessor broadcasting of cache commands to L2. + */ + asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); + u |= BIT(8); /* Set the FW bit */ + asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); + + isb(); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + } +} + +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index ddc5b7ee3e..a8ec5ea21b 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -12,11 +12,8 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -#ifdef CONFIG_SYS_MVEBU_DDR_A38X -#include "../../../drivers/ddr/marvell/axp/xor.h" -#include "../../../drivers/ddr/marvell/axp/xor_regs.h" -#endif -#ifdef CONFIG_SYS_MVEBU_DDR_AXP +#if defined(CONFIG_ARCH_MVEBU) +/* Use common XOR definitions for A3x and AXP */ #include "../../../drivers/ddr/marvell/axp/xor.h" #include "../../../drivers/ddr/marvell/axp/xor_regs.h" #endif @@ -112,7 +109,7 @@ void mvebu_sdram_size_adjust(enum memory_bank bank) mvebu_sdram_bs_set(bank, size); } -#if defined(CONFIG_SYS_MVEBU_DDR_A38X) || defined(CONFIG_SYS_MVEBU_DDR_AXP) +#if defined(CONFIG_ARCH_MVEBU) static u32 xor_ctrl_save; static u32 xor_base_save; static u32 xor_mask_save; @@ -292,11 +289,18 @@ void dram_init_banksize(void) } } +#if defined(CONFIG_ARCH_MVEBU) void board_add_ram_info(int use_default) { + struct sar_freq_modes sar_freq; + + get_sar_freq(&sar_freq); + printf(" (%d MHz, ", sar_freq.d_clk); + if (ecc_enabled()) - printf(" (ECC"); + printf("ECC"); else - printf(" (ECC not"); + printf("ECC not"); printf(" enabled)"); } +#endif diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 1d49cab7fd..cc1fc5f9d4 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -17,12 +17,22 @@ #include <asm/arch/soc.h> -#if defined(CONFIG_ARMADA_XP) +#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X) +/* + * Set this for the common xor register definitions needed in dram.c + * for A38x as well here. + */ #define MV88F78X60 /* for the DDR training bin_hdr code */ #endif #define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#endif + /* * By default kwbimage.cfg from board specific folder is used * If for some board, different configuration file need to be used, @@ -47,8 +57,7 @@ * SPI Flash configuration */ #ifdef CONFIG_CMD_SF -#define CONFIG_HARD_SPI 1 -#define CONFIG_KIRKWOOD_SPI 1 +#define CONFIG_KIRKWOOD_SPI #ifndef CONFIG_ENV_SPI_BUS # define CONFIG_ENV_SPI_BUS 0 #endif @@ -60,6 +69,9 @@ #endif #endif +/* Needed for SPI NOR booting in SPL */ +#define CONFIG_DM_SEQ_ALIAS 1 + /* * Ethernet Driver configuration */ @@ -85,9 +97,9 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif -/* Common SPL configuration */ -#ifndef CONFIG_SPL_LDSCRIPT -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds" -#endif +/* Use common timer */ +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CONFIG_SYS_TIMER_RATE 25000000 #endif /* __MVEBU_CONFIG_H */ diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 5e8bf0c4ce..47f45c1512 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -106,6 +106,14 @@ struct kwgpio_registers { u32 irq_level; }; +struct sar_freq_modes { + u8 val; + u8 ffc; /* Fabric Frequency Configuration */ + u32 p_clk; + u32 nb_clk; + u32 d_clk; +}; + /* Needed for dynamic (board-specific) mbus configuration */ extern struct mvebu_mbus_state mbus_state; @@ -123,6 +131,8 @@ void return_to_bootrom(void); int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); +void get_sar_freq(struct sar_freq_modes *sar_freq); + /* * Highspeed SERDES PHY config init, ported from bin_hdr * to mainline U-Boot diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 22abde080e..cb216bc2cc 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -11,6 +11,8 @@ #ifndef _MVEBU_SOC_H #define _MVEBU_SOC_H +#define SOC_MV78230_ID 0x7823 +#define SOC_MV78260_ID 0x7826 #define SOC_MV78460_ID 0x7846 #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 @@ -33,10 +35,11 @@ #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) #if defined(CONFIG_SPL_BUILD) /* - * On A38x switching the regs base address without running from - * SDRAM doesn't seem to work. So let the SPL still use the - * default base address and switch to the new address in the - * main u-boot later. + * The SPL U-Boot version still runs with the default + * address for the internal registers, configured by + * the BootROM. Only the main U-Boot version uses the + * new internal register base address, that also is + * required for the Linux kernel. */ #define SOC_REGS_PHY_BASE 0xd0000000 #else @@ -47,10 +50,7 @@ #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE -#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) -#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000)) -#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100)) #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) @@ -60,13 +60,9 @@ #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) -#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) -#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) #define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000)) #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) -#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) -#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) @@ -101,4 +97,49 @@ #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE +#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) + +/* BootROM error register (also includes some status infos) */ +#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) +#define BOOTROM_ERR_MODE_OFFS 28 +#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) +#define BOOTROM_ERR_MODE_UART 0x6 + +#if defined(CONFIG_ARMADA_38X) +/* SAR values for Armada 38x */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) + +#define SAR_CPU_FREQ_OFFS 10 +#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 4 +#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 4 +#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x28 +#define BOOT_FROM_SPI 0x32 +#define BOOT_FROM_MMC 0x30 +#define BOOT_FROM_MMC_ALT 0x31 +#else +/* SAR values for Armada XP */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) + +#define SAR_CPU_FREQ_OFFS 21 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_FFC_FREQ_OFFS 24 +#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) +#define SAR2_CPU_FREQ_OFFS 20 +#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 5 +#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 5 +#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x2 +#define BOOT_FROM_SPI 0x3 +#endif + #endif /* _MVEBU_SOC_H */ diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S b/arch/arm/mach-mvebu/lowlevel_spl.S index 2e2181ecea..49e0b906d5 100644 --- a/arch/arm/mach-mvebu/lowlevel_spl.S +++ b/arch/arm/mach-mvebu/lowlevel_spl.S @@ -5,7 +5,6 @@ #include <config.h> #include <linux/linkage.h> -#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT ENTRY(save_boot_params) stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */ ldr r12, =CONFIG_SPL_BOOTROM_SAVE @@ -19,11 +18,6 @@ ENTRY(return_to_bootrom) mov r0, #0x0 /* @ return value: 0x0 NO_ERR */ ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */ ENDPROC(return_to_bootrom) -#else -ENTRY(save_boot_params) - b save_boot_params_ret -ENDPROC(save_boot_params) -#endif /* * cache_inv - invalidate Cache line diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 346278e1be..df263bc3b3 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -491,7 +491,7 @@ int mvebu_mbus_probe(struct mbus_win windows[], int count) #if defined(CONFIG_KIRKWOOD) mbus_state.soc = &kirkwood_mbus_data; #endif -#if defined(CONFIG_ARMADA_XP) +#if defined(CONFIG_ARCH_MVEBU) mbus_state.soc = &armada_370_xp_mbus_data; #endif diff --git a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h index 36e0ed80f0..c8d9485b7b 100644 --- a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h +++ b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h @@ -32,7 +32,7 @@ #define BOARD_ID_BASE 0x0 /* New board ID numbers */ -#define DB_88F78XX0_BP_ID (BOARD_ID_BASE) +#define DB_88F78XX0_BP_ID (BOARD_ID_BASE + 1) #define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1) #define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1) #define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1) @@ -44,7 +44,7 @@ #define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1) #define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1) #define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1) -#define INVALID_BAORD_ID 0xFFFFFFFF +#define INVALID_BOARD_ID 0xFFFFFFFF /* Sample at Reset */ #define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4)) diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 702273aee1..afc0cefda3 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -75,16 +75,24 @@ static u32 board_id_get(void) #endif } -static u8 board_sat_r_get(u8 dev_num, u8 reg) +__weak u8 board_sat_r_get(u8 dev_num, u8 reg) { u8 data; u8 *dev; u32 board_id = board_id_get(); int ret; - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - switch (board_id) { + case DB_78X60_AMC_ID: + case DB_78X60_PCAC_REV2_ID: + case RD_78460_CUSTOMER_ID: + case RD_78460_SERVER_ID: + case RD_78460_SERVER_REV2_ID: + case DB_78X60_PCAC_ID: + return (0x1 << 1) | 1; + case FPGA_88F78XX0_ID: + case RD_78460_NAS_ID: + return (0x0 << 1) | 1; case DB_784MP_GP_ID: dev = rd78460gp_twsi_dev; @@ -94,15 +102,12 @@ static u8 board_sat_r_get(u8 dev_num, u8 reg) dev = db88f78xx0rev2_twsi_dev; break; - case DB_78X60_PCAC_ID: - case FPGA_88F78XX0_ID: - case DB_78X60_PCAC_REV2_ID: - case RD_78460_SERVER_REV2_ID: default: return 0; } /* Read MPP module ID */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1); if (ret) return MV_ERROR; @@ -190,8 +195,17 @@ __weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) u16 ctrl_model_get(void) { - /* Right now only MV78460 supported */ + /* + * SoC version can't be autodetected. So we need to rely on a define + * from the config system here. + */ +#if defined(CONFIG_MV78230) + return MV_78230_DEV_ID; +#elif defined(CONFIG_MV78260) + return MV_78260_DEV_ID; +#else return MV_78460_DEV_ID; +#endif } u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info) @@ -202,6 +216,20 @@ u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info) return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF; } +static int serdes_max_lines_get(void) +{ + switch (ctrl_model_get()) { + case MV_78230_DEV_ID: + return 7; + case MV_78260_DEV_ID: + return 12; + case MV_78460_DEV_ID: + return 16; + } + + return 0; +} + int serdes_phy_config(void) { int status = MV_OK; @@ -221,39 +249,19 @@ int serdes_phy_config(void) u8 device_rev; u32 rx_high_imp_mode; u16 ctrl_mode; - u32 board_id = board_id_get(); u32 pex_if; u32 pex_if_num; /* - * TODO: - * Right now we only support the MV78460 with 16 serdes lines + * Get max. serdes lines count */ - max_serdes_lines = 16; + max_serdes_lines = serdes_max_lines_get(); if (max_serdes_lines == 0) return MV_OK; - switch (board_id) { - case DB_78X60_AMC_ID: - case DB_78X60_PCAC_REV2_ID: - case RD_78460_CUSTOMER_ID: - case RD_78460_SERVER_ID: - case RD_78460_SERVER_REV2_ID: - case DB_78X60_PCAC_ID: - satr11 = (0x1 << 1) | 1; - break; - case FPGA_88F78XX0_ID: - case RD_78460_NAS_ID: - satr11 = (0x0 << 1) | 1; - break; - case DB_88F78XX0_BP_REV2_ID: - case DB_784MP_GP_ID: - case DB_88F78XX0_BP_ID: - satr11 = board_sat_r_get(1, 1); - if ((u8) MV_ERROR == (u8) satr11) - return MV_ERROR; - break; - } + satr11 = board_sat_r_get(1, 1); + if ((u8) MV_ERROR == (u8) satr11) + return MV_ERROR; board_modules_scan(); memset(addr, 0, sizeof(addr)); @@ -1356,19 +1364,19 @@ int serdes_phy_config(void) pex_if, PEX_DEVICE_AND_VENDOR_ID)); devId &= 0xFFFF; devId |= ((ctrl_mode << 16) & 0xffff0000); - DEBUG_INIT_S("Update Device ID PEX"); - DEBUG_INIT_D(pex_if, 1); - DEBUG_INIT_D(devId, 8); - DEBUG_INIT_S("\n"); + DEBUG_INIT_FULL_S("Update Device ID PEX"); + DEBUG_INIT_FULL_D(pex_if, 1); + DEBUG_INIT_FULL_D(devId, 8); + DEBUG_INIT_FULL_S("\n"); reg_write(PEX_CFG_DIRECT_ACCESS (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId); if ((pex_if < 8) && (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)) pex_if += 3; } - DEBUG_INIT_S("Update PEX Device ID 0x"); - DEBUG_INIT_D(ctrl_mode, 4); - DEBUG_INIT_S("0\n"); + DEBUG_INIT_FULL_S("Update PEX Device ID 0x"); + DEBUG_INIT_FULL_D(ctrl_mode, 4); + DEBUG_INIT_FULL_S("0\n"); } tmp = reg_read(PEX_DBG_STATUS_REG(0)); DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp); diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 0ab729aa5d..0879873b97 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -1,10 +1,13 @@ /* - * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <debug_uart.h> +#include <fdtdec.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/cpu.h> @@ -12,14 +15,45 @@ DECLARE_GLOBAL_DATA_PTR; -u32 spl_boot_device(void) +static u32 get_boot_device(void) { -#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) - return BOOT_DEVICE_SPI; -#endif -#if defined(CONFIG_SPL_MMC_SUPPORT) - return BOOT_DEVICE_MMC1; + u32 val; + u32 boot_device; + + /* + * First check, if UART boot-mode is active. This can only + * be done, via the bootrom error register. Here the + * MSB marks if the UART mode is active. + */ + val = readl(CONFIG_BOOTROM_ERR_REG); + boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; + debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); + if (boot_device == BOOTROM_ERR_MODE_UART) + return BOOT_DEVICE_UART; + + /* + * Now check the SAR register for the strapped boot-device + */ + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; + debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); + switch (boot_device) { +#ifdef CONFIG_SPL_MMC_SUPPORT + case BOOT_FROM_MMC: + case BOOT_FROM_MMC_ALT: + return BOOT_DEVICE_MMC1; #endif + case BOOT_FROM_UART: + return BOOT_DEVICE_UART; + case BOOT_FROM_SPI: + default: + return BOOT_DEVICE_SPI; + }; +} + +u32 spl_boot_device(void) +{ + return get_boot_device(); } #ifdef CONFIG_SPL_MMC_SUPPORT @@ -31,18 +65,7 @@ u32 spl_boot_mode(void) void board_init_f(ulong dummy) { -#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT - /* - * Only call arch_cpu_init() when not returning to the - * Marvell BootROM, which is done when booting via - * the xmodem protocol (kwboot tool). Otherwise the - * internal register will get remapped and the BootROM - * can't continue to run correctly. - */ - - /* Linux expects the internal registers to be at 0xf1000000 */ - arch_cpu_init(); -#endif + int ret; /* * Pin muxing needs to be done before UART output, since @@ -51,6 +74,27 @@ void board_init_f(ulong dummy) */ board_early_init_f(); + /* Example code showing how to enable the debug UART on MVEBU */ +#ifdef EARLY_UART + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ +#endif + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + /* Use special translation offset for SPL */ + dm_set_translation_offset(0xd0000000 - 0xf1000000); + preloader_console_init(); timer_init(); @@ -61,7 +105,6 @@ void board_init_f(ulong dummy) /* Setup DDR */ ddr3_init(); -#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT /* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool. @@ -73,6 +116,6 @@ void board_init_f(ulong dummy) * need to return to the BootROM to enable this xmodem * UART download. */ - return_to_bootrom(); -#endif + if (get_boot_device() == BOOT_DEVICE_UART) + return_to_bootrom(); } diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c index 5449a8926c..f5c2eaa808 100644 --- a/arch/arm/mach-mvebu/timer.c +++ b/arch/arm/mach-mvebu/timer.c @@ -2,6 +2,8 @@ * Copyright (C) Marvell International Ltd. and its affiliates * Written-by: Prafulla Wadaskar <prafulla@marvell.com> * + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,108 +11,14 @@ #include <asm/io.h> #include <asm/arch/soc.h> -#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */ - -/* - * ARM Timers Registers Map - */ -#define CNTMR_CTRL_REG &tmr_regs->ctrl -#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload -#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val - -/* - * ARM Timers Control Register - * CPU_TIMERS_CTRL_REG (CTCR) - */ -#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) - -#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) - -/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */ -#if defined(CONFIG_ARMADA_XP) -#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11) -#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr)) -#else -#define CTCR_ARM_TIMER_25MHZ(cntr) 0 -#endif - -#define TIMER_LOAD_VAL 0xffffffff - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -static int init_done __attribute__((section(".data"))) = 0; - -/* Timer reload and current value registers */ -struct kwtmr_val { - u32 reload; /* Timer reload reg */ - u32 val; /* Timer value reg */ -}; - -/* Timer registers */ -struct kwtmr_registers { - u32 ctrl; /* Timer control reg */ - u32 pad[3]; - struct kwtmr_val tmr[4]; - u32 wdt_reload; - u32 wdt_val; -}; - DECLARE_GLOBAL_DATA_PTR; -static struct kwtmr_registers *tmr_regs = - (struct kwtmr_registers *)MVEBU_TIMER_BASE; - -static inline ulong read_timer(void) -{ - return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000); -} - -ulong get_timer_masked(void) -{ - ulong now = read_timer(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; - } - lastdec = now; +#define TIMER_LOAD_VAL 0xffffffff - return timestamp; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay(unsigned long usec) -{ - uint current; - ulong delayticks; - - current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); - - if (current < delayticks) { - delayticks -= current; - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; - while ((TIMER_LOAD_VAL - delayticks) < - readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; - } else { - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > - (current - delayticks)) ; - } -} +static int init_done __attribute__((section(".data"))) = 0; /* - * init the counter + * Timer initialization */ int timer_init(void) { @@ -120,35 +28,15 @@ int timer_init(void) init_done = 1; /* load value into timer */ - writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); - writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); + writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10); + writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14); +#if defined(CONFIG_ARCH_MVEBU) + /* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */ + setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11)); +#endif /* enable timer in auto reload mode */ - clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR), - CTCR_ARM_TIMER_EN(UBOOT_CNTR) | - CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR)); - - /* init the timestamp and lastdec value */ - lastdec = read_timer(); - timestamp = 0; + setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3); return 0; } - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/mach-mvebu/u-boot-spl.lds b/arch/arm/mach-mvebu/u-boot-spl.lds deleted file mode 100644 index eee1db49ee..0000000000 --- a/arch/arm/mach-mvebu/u-boot-spl.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_SIZE } -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - *(.vectors) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*_i2c_*))); - } >.sram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -} diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh index c1640bc32a..1adfbf7384 100755 --- a/arch/arm/mach-socfpga/qts-filter.sh +++ b/arch/arm/mach-socfpga/qts-filter.sh @@ -3,13 +3,15 @@ # # Process iocsr_config_*.[ch] # $1: SoC type -# $2: Input directory -# $3: Output directory +# $2: Input handoff directory +# $3: Input BSP Generated directory +# $4: Output directory # process_iocsr_config() { soc="$1" - in_dir="$2" - out_dir="$3" + in_qts_dir="$2" + in_bsp_dir="$3" + out_dir="$4" ( cat << EOF @@ -26,13 +28,13 @@ EOF # Retrieve the scan chain lengths grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \ - ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()" + ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()" echo "" # Retrieve the scan chain config and zap the ad-hoc length encoding sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \ - ${in_dir}/generated/iocsr_config_${soc}.c + ${in_bsp_dir}/generated/iocsr_config_${soc}.c cat << EOF @@ -49,8 +51,9 @@ EOF # process_pinmux_config() { soc="$1" - in_dir="$2" - out_dir="$3" + in_qts_dir="$2" + in_bsp_dir="$3" + out_dir="$4" ( cat << EOF @@ -67,7 +70,7 @@ EOF # Retrieve the pinmux config and zap the ad-hoc length encoding sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \ - ${in_dir}/generated/pinmux_config_${soc}.c + ${in_bsp_dir}/generated/pinmux_config_${soc}.c cat << EOF @@ -84,8 +87,9 @@ EOF # process_pll_config() { soc="$1" - in_dir="$2" - out_dir="$3" + in_qts_dir="$2" + in_bsp_dir="$3" + out_dir="$4" ( cat << EOF @@ -102,7 +106,7 @@ EOF # Retrieve the pll config and zap parenthesis sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \ - ${in_dir}/generated/pll_config.h + ${in_bsp_dir}/generated/pll_config.h cat << EOF @@ -126,8 +130,9 @@ grep_sdram_config() { # process_sdram_config() { soc="$1" - in_dir="$2" - out_dir="$3" + in_qts_dir="$2" + in_bsp_dir="$3" + out_dir="$4" ( cat << EOF @@ -144,29 +149,32 @@ EOF echo "/* SDRAM configuration */" # Retrieve the sdram config, zap broken lines and zap parenthesis - sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" ${in_dir}/generated/sdram/sdram_config.h | + sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" \ + ${in_bsp_dir}/generated/sdram/sdram_config.h | sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' | sort -u | grep_sdram_config echo "" echo "/* Sequencer auto configuration */" sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ - ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u | grep_sdram_config + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h | + sort -u | grep_sdram_config echo "" echo "/* Sequencer defines configuration */" sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ - ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u | grep_sdram_config + ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h | + sort -u | grep_sdram_config echo "" echo "/* Sequencer ac_rom_init configuration */" sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ - ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c echo "" echo "/* Sequencer inst_rom_init configuration */" sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ - ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c cat << EOF @@ -176,30 +184,36 @@ EOF } usage() { - echo "$0 [soc_type] [input_dir] [output_dir]" + echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]" echo "Process QTS-generated headers into U-Boot compatible ones." echo "" - echo " soc_type\t\tType of SoC, either 'cyclone5' or 'arria5'," - echo " input_dir\t\tDirectory with the QTS project." - echo " output_dir\t\tDirectory to store the U-Boot compatible headers." + echo -e " soc_type\t-\tType of SoC, either 'cyclone5' or 'arria5'." + echo -e " input_qts_dir\t-\tDirectory with compiled Quartus project" + echo -e "\t\t\t\tand containing the Quartus project file (QPF)." + echo -e " input_bsp_dir\t-\tDirectory with generated bsp containing" + echo -e "\t\t\t\tthe settings.bsp file." + echo -e " output_dir\t-\tDirectory to store the U-Boot compatible" + echo -e "\t\t\t\theaders." echo "" } soc="$1" -in_dir="$2" -out_dir="$3" +in_qts_dir="$2" +in_bsp_dir="$3" +out_dir="$4" -if [ "$#" -ne 3 ] ; then +if [ "$#" -ne 4 ] ; then usage exit 1 fi -if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then +if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \ + ! -d "${out_dir}" -o -z "${soc}" ] ; then usage exit 3 fi -process_iocsr_config "${soc}" "${in_dir}" "${out_dir}" -process_pinmux_config "${soc}" "${in_dir}" "${out_dir}" -process_pll_config "${soc}" "${in_dir}" "${out_dir}" -process_sdram_config "${soc}" "${in_dir}" "${out_dir}" +process_iocsr_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" +process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" +process_pll_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" +process_sdram_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig new file mode 100644 index 0000000000..7dbeb040d5 --- /dev/null +++ b/arch/arm/mach-stm32/Kconfig @@ -0,0 +1,12 @@ +if STM32 + +config STM32F4 + bool "stm32f4 family" + +config STM32F1 + bool "stm32f1 family" + +source "arch/arm/mach-stm32/stm32f4/Kconfig" +source "arch/arm/mach-stm32/stm32f1/Kconfig" + +endif diff --git a/arch/mips/mach-au1x00/config.mk b/arch/arm/mach-stm32/Makefile index 5c89129d8c..ea06034e10 100644 --- a/arch/mips/mach-au1x00/config.mk +++ b/arch/arm/mach-stm32/Makefile @@ -1,8 +1,9 @@ # -# (C) Copyright 2011 +# (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -mtune=4kc +obj-$(CONFIG_STM32F1) += stm32f1/ +obj-$(CONFIG_STM32F4) += stm32f4/ diff --git a/arch/arm/mach-stm32/stm32f1/Kconfig b/arch/arm/mach-stm32/stm32f1/Kconfig new file mode 100644 index 0000000000..f627fd2541 --- /dev/null +++ b/arch/arm/mach-stm32/stm32f1/Kconfig @@ -0,0 +1,3 @@ +if STM32F1 + +endif diff --git a/arch/arm/cpu/armv7m/stm32f1/Makefile b/arch/arm/mach-stm32/stm32f1/Makefile index e2081dbf9e..e2081dbf9e 100644 --- a/arch/arm/cpu/armv7m/stm32f1/Makefile +++ b/arch/arm/mach-stm32/stm32f1/Makefile diff --git a/arch/arm/cpu/armv7m/stm32f1/clock.c b/arch/arm/mach-stm32/stm32f1/clock.c index 28208485d4..28208485d4 100644 --- a/arch/arm/cpu/armv7m/stm32f1/clock.c +++ b/arch/arm/mach-stm32/stm32f1/clock.c diff --git a/arch/arm/cpu/armv7m/stm32f1/flash.c b/arch/arm/mach-stm32/stm32f1/flash.c index 7d41f63733..7d41f63733 100644 --- a/arch/arm/cpu/armv7m/stm32f1/flash.c +++ b/arch/arm/mach-stm32/stm32f1/flash.c diff --git a/arch/arm/cpu/armv7m/stm32f1/soc.c b/arch/arm/mach-stm32/stm32f1/soc.c index 4438621b9a..4438621b9a 100644 --- a/arch/arm/cpu/armv7m/stm32f1/soc.c +++ b/arch/arm/mach-stm32/stm32f1/soc.c diff --git a/arch/arm/cpu/armv7m/stm32f1/timer.c b/arch/arm/mach-stm32/stm32f1/timer.c index 6a261986e9..6a261986e9 100644 --- a/arch/arm/cpu/armv7m/stm32f1/timer.c +++ b/arch/arm/mach-stm32/stm32f1/timer.c diff --git a/arch/arm/mach-stm32/stm32f4/Kconfig b/arch/arm/mach-stm32/stm32f4/Kconfig new file mode 100644 index 0000000000..a63619e07f --- /dev/null +++ b/arch/arm/mach-stm32/stm32f4/Kconfig @@ -0,0 +1,8 @@ +if STM32F4 + +config TARGET_STM32F429_DISCOVERY + bool "STM32F429 Discovery board" + +source "board/st/stm32f429-discovery/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7m/stm32f4/Makefile b/arch/arm/mach-stm32/stm32f4/Makefile index 42d01db14d..42d01db14d 100644 --- a/arch/arm/cpu/armv7m/stm32f4/Makefile +++ b/arch/arm/mach-stm32/stm32f4/Makefile diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c index 3deb17aa83..3deb17aa83 100644 --- a/arch/arm/cpu/armv7m/stm32f4/clock.c +++ b/arch/arm/mach-stm32/stm32f4/clock.c diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/mach-stm32/stm32f4/flash.c index a379f477df..a379f477df 100644 --- a/arch/arm/cpu/armv7m/stm32f4/flash.c +++ b/arch/arm/mach-stm32/stm32f4/flash.c diff --git a/arch/arm/cpu/armv7m/stm32f4/soc.c b/arch/arm/mach-stm32/stm32f4/soc.c index b5d06dbe83..b5d06dbe83 100644 --- a/arch/arm/cpu/armv7m/stm32f4/soc.c +++ b/arch/arm/mach-stm32/stm32f4/soc.c diff --git a/arch/arm/cpu/armv7m/stm32f4/timer.c b/arch/arm/mach-stm32/stm32f4/timer.c index 1dee190766..1dee190766 100644 --- a/arch/arm/cpu/armv7m/stm32f4/timer.c +++ b/arch/arm/mach-stm32/stm32f4/timer.c diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index 0e9cb97832..6dad40325d 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra cache routines */ diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index f75c6c664a..c50d56dc88 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra SoC common clock control functions */ diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index ba04a56be7..a3ebb57f20 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index c7d705d8ef..0dbddd45d4 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra vpr routines */ diff --git a/arch/arm/mach-tegra/tegra114/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c index 52441c71e6..ca9d970abc 100644 --- a/arch/arm/mach-tegra/tegra114/funcmux.c +++ b/arch/arm/mach-tegra/tegra114/funcmux.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra114 high-level function multiplexing */ diff --git a/arch/arm/mach-tegra/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c index 67f49d7756..7fbc2e2865 100644 --- a/arch/arm/mach-tegra/tegra20/cpu.c +++ b/arch/arm/mach-tegra/tegra20/cpu.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index c76e74c65f..66b021b824 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/arm/mach-tegra/tegra30/funcmux.c b/arch/arm/mach-tegra/tegra30/funcmux.c index 409335ce1d..8c68339043 100644 --- a/arch/arm/mach-tegra/tegra30/funcmux.c +++ b/arch/arm/mach-tegra/tegra30/funcmux.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra30 high-level function multiplexing */ diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index b4ca8b6934..4398114658 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -11,6 +11,12 @@ #include "ssc-regs.h" #ifdef CONFIG_UNIPHIER_L2CACHE_ON +static void uniphier_cache_sync(void) +{ + writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ + readl(SSCOPE); /* need a read back to confirm */ +} + static void uniphier_cache_maint_all(u32 operation) { /* try until the command is successfully set */ @@ -25,8 +31,7 @@ static void uniphier_cache_maint_all(u32 operation) /* clear the complete notification flag */ writel(SSCOLPQS_EF, SSCOLPQS); - writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ - readl(SSCOPE); /* need a read back to confirm */ + uniphier_cache_sync(); } void v7_outer_cache_flush_all(void) @@ -67,7 +72,9 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) */ start = start & ~(SSC_LINE_SIZE - 1); - if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) { + size = end - start; + + if (unlikely(size >= (u32)(-SSC_LINE_SIZE))) { /* this means cache operation for all range */ uniphier_cache_maint_all(operation); return; @@ -77,7 +84,7 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) * If end address is not aligned to cache-line, * do cache operation for the last cache-line */ - size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1); + size = ALIGN(size, SSC_LINE_SIZE); while (size) { u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ? @@ -88,8 +95,7 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) size -= chunk_size; } - writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ - readl(SSCOPE); /* need a read back to confirm */ + uniphier_cache_sync(); } void v7_outer_cache_flush_range(u32 start, u32 end) @@ -99,12 +105,37 @@ void v7_outer_cache_flush_range(u32 start, u32 end) void v7_outer_cache_inval_range(u32 start, u32 end) { + if (start & (SSC_LINE_SIZE - 1)) { + start &= ~(SSC_LINE_SIZE - 1); + __uniphier_cache_maint_range(start, SSC_LINE_SIZE, + SSCOQM_CM_WB_INV); + start += SSC_LINE_SIZE; + } + + if (start >= end) { + uniphier_cache_sync(); + return; + } + + if (end & (SSC_LINE_SIZE - 1)) { + end &= ~(SSC_LINE_SIZE - 1); + __uniphier_cache_maint_range(end, SSC_LINE_SIZE, + SSCOQM_CM_WB_INV); + } + + if (start >= end) { + uniphier_cache_sync(); + return; + } + uniphier_cache_maint_range(start, end, SSCOQM_CM_INV); } void v7_outer_cache_enable(void) { u32 tmp; + + writel(U32_MAX, SSCLPDAWCR); /* activate all ways */ tmp = readl(SSCC); tmp |= SSCC_ON; writel(tmp, SSCC); diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c index 2c8cbc2579..9fb34f79a7 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c @@ -40,18 +40,12 @@ int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) writel(0x0000040B, &phy->dcr); if (freq == 1333) { writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8363c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x1a8363c0, &phy->dtpr[1]); writel(0x5002c200, &phy->dtpr[2]); writel(0x00000b51, &phy->mr0); } else { writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a878400, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); + writel(0x1a878400, &phy->dtpr[1]); writel(0xa00214f8, &phy->dtpr[2]); writel(0x00000d71, &phy->mr0); } diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index 63a84e68c0..bb7acdee1e 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -16,54 +16,7 @@ #include "../init.h" #include "../soc-info.h" #include "ddrmphy-regs.h" - -/* UM registers */ -#define UMC_MBUS0 0x00080004 -#define UMC_MBUS1 0x00081004 -#define UMC_MBUS2 0x00082004 -#define UMC_MBUS3 0x00083004 - -/* UD registers */ -#define UMC_BITPERPIXELMODE_D0 0x010 -#define UMC_PAIR1DOFF_D0 0x054 - -/* DC registers */ -#define UMC_INITSET 0x014 -#define UMC_INITSTAT 0x018 -#define UMC_CMDCTLA 0x000 -#define UMC_CMDCTLB 0x004 -#define UMC_SPCCTLA 0x030 -#define UMC_SPCCTLB 0x034 -#define UMC_SPCSETB 0x03c -#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ -#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ -#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ -#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ -#define UMC_ACSSETA 0x060 -#define UMC_FLOWCTLA 0x400 -#define UMC_FLOWCTLB 0x404 -#define UMC_FLOWCTLC 0x408 -#define UMC_FLOWCTLG 0x508 -#define UMC_FLOWCTLOB0 0x520 -#define UMC_FLOWCTLOB1 0x524 -#define UMC_RDATACTL_D0 0x600 -#define UMC_RDATACTL_RADLTY_SHIFT 4 -#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) -#define UMC_RDATACTL_RAD2LTY_SHIFT 8 -#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) -#define UMC_WDATACTL_D0 0x604 -#define UMC_RDATACTL_D1 0x608 -#define UMC_WDATACTL_D1 0x60c -#define UMC_DATASET 0x610 -#define UMC_RESPCTL 0x624 -#define UMC_DCCGCTL 0x720 -#define UMC_ERRMASKA 0x958 -#define UMC_ERRMASKB 0x95c -#define UMC_BSICMAPSET 0x988 -#define UMC_DIOCTLA 0xc00 -#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ -#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ -#define UMC_DFICUPDCTLA 0xc20 +#include "umc-regs.h" enum dram_freq { FREQ_1866M, diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index 6159281fd3..a6957a4a51 100644 --- a/arch/arm/mach-uniphier/dram/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h @@ -69,6 +69,10 @@ #define UMC_SPCCTLB 0x00000034 #define UMC_SPCSETA 0x00000038 #define UMC_SPCSETB 0x0000003C +#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ +#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ +#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ +#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ #define UMC_SPCSETC 0x00000040 #define UMC_SPCSETD 0x00000044 #define UMC_SPCSTATA 0x00000050 @@ -79,17 +83,39 @@ #define UMC_FLOWCTLB 0x00000404 #define UMC_FLOWCTLC 0x00000408 #define UMC_FLOWCTLG 0x00000508 +#define UMC_FLOWCTLOB0 0x00000520 +#define UMC_FLOWCTLOB1 0x00000524 #define UMC_RDATACTL_D0 0x00000600 +#define UMC_RDATACTL_RADLTY_SHIFT 4 +#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) +#define UMC_RDATACTL_RAD2LTY_SHIFT 8 +#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) #define UMC_WDATACTL_D0 0x00000604 #define UMC_RDATACTL_D1 0x00000608 #define UMC_WDATACTL_D1 0x0000060C #define UMC_DATASET 0x00000610 +#define UMC_RESPCTL 0x00000624 #define UMC_DCCGCTL 0x00000720 #define UMC_DICGCTLA 0x00000724 #define UMC_DICGCTLB 0x00000728 +#define UMC_ERRMASKA 0x00000958 +#define UMC_ERRMASKB 0x0000095c +#define UMC_BSICMAPSET 0x00000988 #define UMC_DIOCTLA 0x00000C00 +#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ +#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ #define UMC_DFICUPDCTLA 0x00000C20 +/* UM registers */ +#define UMC_MBUS0 0x00080004 +#define UMC_MBUS1 0x00081004 +#define UMC_MBUS2 0x00082004 +#define UMC_MBUS3 0x00083004 + +/* UD registers */ +#define UMC_BITPERPIXELMODE_D0 0x010 +#define UMC_PAIR1DOFF_D0 0x054 + #ifndef __ASSEMBLY__ #include <linux/types.h> diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile deleted file mode 100644 index de243feaab..0000000000 --- a/arch/arm/mvebu-common/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = dram.o -obj-y += gpio.o -obj-$(CONFIG_ARMADA_XP) += mbus.o -obj-y += timer.o - -obj-y += serdes/ diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 979eb5a765..ae261b1132 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -34,7 +34,7 @@ #if defined(CONFIG_SERIAL_BOOT) #define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) -#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE) +#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE) #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) #endif @@ -490,7 +490,7 @@ asm_dspi_rd_status: /* copy 4 boot pages to dram as soon as possible */ /* each page is 996 bytes (1056 total with 60 ECC bytes */ move.l #0x00000000, %a1 /* src */ - move.l #TEXT_BASE, %a2 /* dst */ + move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */ move.l #0x3E0, %d0 /* sz in long */ asm_boot_nand_copy: @@ -571,7 +571,7 @@ asm_nand_init: move.l #4, %d2 /* start at 4 */ move.l #0xFC0FFF04, %a0 /* cmd2 */ move.l #0xFC0FFF0C, %a1 /* rar */ - move.l #(TEXT_BASE + 0xF80), %a2 /* dst */ + move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2 /* dst */ asm_nand_read: move.l #0x11000000, %d0 /* rar */ @@ -609,7 +609,7 @@ asm_nand_copy: bgt asm_nand_read /* jump to memory and execute */ - move.l #(TEXT_BASE + 0x400), %a0 + move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0 jmp (%a0) #endif /* CONFIG_SYS_NAND_BOOT */ diff --git a/arch/m68k/include/asm/fsl_i2c.h b/arch/m68k/include/asm/fsl_i2c.h index 2bc9bf434e..1b1c25ef89 100644 --- a/arch/m68k/include/asm/fsl_i2c.h +++ b/arch/m68k/include/asm/fsl_i2c.h @@ -8,23 +8,7 @@ * and Jeff Brown. * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_FSL_I2C_H_ diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 14f46a8f04..206be3e3ee 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -25,7 +25,7 @@ _start: addi r8, r0, __end mts rslr, r8 - /* TODO: Redo this code to call board_init_f_mem() */ + /* TODO: Redo this code to call board_init_f_*() */ #if defined(CONFIG_SPL_BUILD) addi r1, r0, CONFIG_SPL_STACK_ADDR mts rshr, r1 @@ -142,7 +142,7 @@ _start: ori r12, r12, 0x1a0 mts rmsr, r12 - /* TODO: Redo this code to call board_init_f_mem() */ + /* TODO: Redo this code to call board_init_f_*() */ clear_bss: /* clear BSS segments */ addi r5, r0, __bss_start diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7f7e258a80..1b39c4c0c6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -28,6 +28,7 @@ config TARGET_MALTA select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SWAP_IO_SPACE + select MIPS_L1_CACHE_SHIFT_6 config TARGET_VCT bool "Support vct" @@ -43,6 +44,7 @@ config TARGET_DBAU1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select MIPS_TUNE_4KC config TARGET_PB1X00 bool "Support pb1x00" @@ -50,7 +52,7 @@ config TARGET_PB1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD - + select MIPS_TUNE_4KC endchoice @@ -174,6 +176,15 @@ config CPU_MIPS64 bool default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 +config MIPS_TUNE_4KC + bool + +config MIPS_TUNE_14KC + bool + +config MIPS_TUNE_24KC + bool + config 32BIT bool @@ -186,6 +197,26 @@ config SWAP_IO_SPACE config SYS_MIPS_CACHE_INIT_RAM_LOAD bool +config MIPS_L1_CACHE_SHIFT_4 + bool + +config MIPS_L1_CACHE_SHIFT_5 + bool + +config MIPS_L1_CACHE_SHIFT_6 + bool + +config MIPS_L1_CACHE_SHIFT_7 + bool + +config MIPS_L1_CACHE_SHIFT + int + default "7" if MIPS_L1_CACHE_SHIFT_7 + default "6" if MIPS_L1_CACHE_SHIFT_6 + default "5" if MIPS_L1_CACHE_SHIFT_5 + default "4" if MIPS_L1_CACHE_SHIFT_4 + default "5" + endif endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 43f0f5c504..2133e7e065 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -7,4 +7,25 @@ head-y := arch/mips/cpu/start.o libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ -libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/ +machine-$(CONFIG_SOC_AU1X00) += au1x00 + +machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) +libs-y += $(machdirs) + +PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) + +# Optimize for MIPS architectures +arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 +arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 +arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 +arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 + +# Allow extra optimization for specific CPUs/SoCs +tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc +tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc +tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc + +# Include default header files +cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic + +PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) $(cflags-y) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 52e28f2ca5..609a998f3b 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -35,12 +35,6 @@ PLATFORM_LDFLAGS += -m$(64bit-emul) OBJCOPYFLAGS += -O $(64bit-bfd) endif -cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 -cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 -cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 -cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 -PLATFORM_CPPFLAGS += $(cpuflags-y) - PLATFORM_CPPFLAGS += -D__MIPS__ # @@ -63,10 +57,21 @@ PLATFORM_CPPFLAGS += -D__MIPS__ # On the other hand, we want PIC in the U-Boot code to relocate it from ROM # to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic +ifdef CONFIG_SPL_BUILD +PF_ABICALLS := -mno-abicalls +PF_PIC := -fno-pic +PF_PIE := +else +PF_ABICALLS := -mabicalls +PF_PIC := -fpic +PF_PIE := -pie +PF_OBJCOPY := -j .got -j .u_boot_list -j .rel.dyn -j .padding +PF_OBJCOPY += -j .dtb.init.rodata +endif + +PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC) PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -LDFLAGS_FINAL += --gc-sections -pie -OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got -OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding +LDFLAGS_FINAL += --gc-sections $(PF_PIE) +OBJCOPYFLAGS += -j .text -j .rodata -j .data $(PF_OBJCOPY) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 3b5b622abe..e95cdca61e 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -56,9 +56,7 @@ .set noreorder - .globl _start - .text -_start: +ENTRY(_start) /* U-boot entry point */ b reset nop @@ -192,6 +190,8 @@ reset: jr t9 move ra, zero + END(_start) + /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -202,9 +202,7 @@ reset: * a1 = gd * a2 = destination address */ - .globl relocate_code - .ent relocate_code -relocate_code: +ENTRY(relocate_code) move sp, a0 # set new stack pointer move fp, sp @@ -317,4 +315,4 @@ in_ram: jr t9 move ra, zero - .end relocate_code + END(relocate_code) diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/mips/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile new file mode 100644 index 0000000000..47b6eb50c3 --- /dev/null +++ b/arch/mips/dts/Makefile @@ -0,0 +1,16 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +dtb-y += + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/mips/dts/include/dt-bindings b/arch/mips/dts/include/dt-bindings new file mode 120000 index 0000000000..0cecb3d080 --- /dev/null +++ b/arch/mips/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings
\ No newline at end of file diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi new file mode 100644 index 0000000000..24ee6c3e73 --- /dev/null +++ b/arch/mips/dts/skeleton.dtsi @@ -0,0 +1,23 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + + chosen { + }; + + aliases { + }; + + memory { + device_type = "memory"; + reg = <0 0>; + }; +}; diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index b768bb5081..0994e9670b 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -1,15 +1,15 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1996, 99 Ralf Baechle * Copyright (C) 2000, 2002 Maciej W. Rozycki * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_ADDRSPACE_H #define _ASM_ADDRSPACE_H +#include <spaces.h> + /* * Configure language */ @@ -50,7 +50,7 @@ */ #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) #define XPHYSADDR(a) ((_ACAST64_(a)) & \ - _CONST64_(0x000000ffffffffff)) + _CONST64_(0x0000ffffffffffff)) #ifdef CONFIG_64BIT diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 933ccb1b78..44694a3fb8 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -1,8 +1,4 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle * Copyright (C) 1999 by Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. @@ -13,6 +9,8 @@ * Some of the routines below contain useless nops that will be optimized * away by gas in -O mode. These nops are however required to fill delay * slots in noreorder mode. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ASM_H #define __ASM_ASM_H @@ -33,50 +31,58 @@ * Not used for the kernel but here seems to be the right place. */ #ifdef __PIC__ -#define CPRESTORE(register) \ +#define CPRESTORE(register) \ .cprestore register -#define CPADD(register) \ +#define CPADD(register) \ .cpadd register -#define CPLOAD(register) \ - .cpload register +#define CPLOAD(register) \ + .cpload register #else #define CPRESTORE(register) #define CPADD(register) #define CPLOAD(register) #endif +#define ENTRY(symbol) \ + .globl symbol; \ + .type symbol, @function; \ + .ent symbol, 0; \ +symbol: + /* * LEAF - declare leaf routine */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ + .section .text.symbol, "x"; \ symbol: .frame sp, 0, ra /* * NESTED - declare nested routine entry point */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ + .section .text.symbol, "x"; \ symbol: .frame sp, framesize, rpc /* * END - mark end of function */ -#define END(function) \ - .end function; \ +#define END(function) \ + .end function; \ .size function, .-function /* * EXPORT - export definition of symbol */ #define EXPORT(symbol) \ - .globl symbol; \ + .globl symbol; \ symbol: /* @@ -90,16 +96,16 @@ symbol: /* * ABS - export absolute symbol */ -#define ABS(symbol,value) \ - .globl symbol; \ +#define ABS(symbol,value) \ + .globl symbol; \ symbol = value -#define PANIC(msg) \ +#define PANIC(msg) \ .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal panic; \ -9: b 9b; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal panic; \ +9: b 9b; \ .set pop; \ TEXT(msg) @@ -107,31 +113,31 @@ symbol = value * Print formatted string */ #ifdef CONFIG_PRINTK -#define PRINT(string) \ +#define PRINT(string) \ .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal printk; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal printk; \ .set pop; \ TEXT(string) #else #define PRINT(string) #endif -#define TEXT(msg) \ +#define TEXT(msg) \ .pushsection .data; \ -8: .asciiz msg; \ +8: .asciiz msg; \ .popsection; /* * Build text tables */ -#define TTABLE(string) \ +#define TTABLE(string) \ .pushsection .text; \ - .word 1f; \ + .word 1f; \ .popsection \ .pushsection .data; \ -1: .asciiz string; \ +1: .asciiz string; \ .popsection /* @@ -143,21 +149,29 @@ symbol = value */ #ifdef CONFIG_CPU_HAS_PREFETCH -#define PREF(hint,addr) \ +#define PREF(hint, addr) \ .set push; \ - .set mips4; \ + .set arch=r5000; \ pref hint, addr; \ .set pop -#define PREFX(hint,addr) \ +#define PREFE(hint, addr) \ + .set push; \ + .set mips0; \ + .set eva; \ + prefe hint, addr; \ + .set pop + +#define PREFX(hint, addr) \ .set push; \ - .set mips4; \ + .set arch=r5000; \ prefx hint, addr; \ .set pop #else /* !CONFIG_CPU_HAS_PREFETCH */ #define PREF(hint, addr) +#define PREFE(hint, addr) #define PREFX(hint, addr) #endif /* !CONFIG_CPU_HAS_PREFETCH */ @@ -166,42 +180,42 @@ symbol = value * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. */ #if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set reorder; \ - beqz rt, 9f; \ - move rd, rs; \ + beqz rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set reorder; \ - bnez rt, 9f; \ - move rd, rs; \ + bnez rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set noreorder; \ - bnezl rt, 9f; \ - move rd, rs; \ + bnezl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set noreorder; \ - beqzl rt, 9f; \ - move rd, rs; \ + beqzl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ movn rd, rs, rt -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ movz rd, rs, rt #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ @@ -296,6 +310,7 @@ symbol = value #define LONG_SUBU subu #define LONG_L lw #define LONG_S sw +#define LONG_SP swp #define LONG_SLL sll #define LONG_SLLV sllv #define LONG_SRL srl @@ -318,6 +333,7 @@ symbol = value #define LONG_SUBU dsubu #define LONG_L ld #define LONG_S sd +#define LONG_SP sdp #define LONG_SLL dsll #define LONG_SLLV dsllv #define LONG_SRL dsrl diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index c31ff6efb4..cce6995c74 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -1,10 +1,8 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org) * Copyright (c) 2000 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_BITOPS_H #define _ASM_BITOPS_H diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h index b5e685feb6..67fdf71301 100644 --- a/arch/mips/include/asm/byteorder.h +++ b/arch/mips/include/asm/byteorder.h @@ -1,9 +1,7 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1996, 99, 2003 by Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_BYTEORDER_H #define _ASM_BYTEORDER_H diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 0dfb54ef4d..806bd26ba9 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -7,15 +7,9 @@ #ifndef __MIPS_CACHE_H__ #define __MIPS_CACHE_H__ -/* - * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use - * that as a default for aligning DMA buffers unless the board config has - * specified another cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 128 -#endif +#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) #endif /* __MIPS_CACHE_H__ */ diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h index f3ce721861..5e77dfa029 100644 --- a/arch/mips/include/asm/cachectl.h +++ b/arch/mips/include/asm/cachectl.h @@ -1,9 +1,7 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_CACHECTL #define _ASM_CACHECTL diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index af2adc701e..a3b07c6ad0 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -1,12 +1,10 @@ /* * Cache operations for the cache instruction. * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle * (C) Copyright 1999 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_CACHEOPS_H #define __ASM_CACHEOPS_H diff --git a/arch/mips/include/asm/const.h b/arch/mips/include/asm/const.h new file mode 100644 index 0000000000..f600e7a5b7 --- /dev/null +++ b/arch/mips/include/asm/const.h @@ -0,0 +1,31 @@ +/* + * const.h: Macros for dealing with constants. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _LINUX_CONST_H +#define _LINUX_CONST_H + +/* Some constant macros are used in both assembler and + * C code. Therefore we cannot annotate them always with + * 'UL' and other type specifiers unilaterally. We + * use the following macros to deal with this. + * + * Similarly, _AT() will cast an expression with a type in C, but + * leave it unchanged in asm. + */ + +#ifdef __ASSEMBLY__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#define _AT(T,X) ((T)(X)) +#endif + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* !(_LINUX_CONST_H) */ diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h new file mode 100644 index 0000000000..a6e9d94019 --- /dev/null +++ b/arch/mips/include/asm/cpu-features.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_CPU_FEATURES_H +#define __ASM_CPU_FEATURES_H + +#include <cpu-feature-overrides.h> + +#ifdef CONFIG_32BIT +# ifndef cpu_has_64bits +# define cpu_has_64bits 0 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 0 +# endif +#endif + +#ifdef CONFIG_64BIT +# ifndef cpu_has_64bits +# define cpu_has_64bits 1 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 1 +# endif +#endif + +#endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/gpio.h b/arch/mips/include/asm/gpio.h new file mode 100644 index 0000000000..306ab4c9f2 --- /dev/null +++ b/arch/mips/include/asm/gpio.h @@ -0,0 +1 @@ +#include <asm-generic/gpio.h> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index a7ab087c0d..b8ac5a5ac5 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -1,21 +1,28 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995 Waldorf GmbH - * Copyright (C) 1994 - 2000 Ralf Baechle + * Copyright (C) 1994 - 2000, 06 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 FSMLabs, Inc. + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki <macro@mips.com> + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_IO_H #define _ASM_IO_H -#if 0 -#include <linux/pagemap.h> -#endif +#include <linux/compiler.h> +#include <linux/types.h> + #include <asm/addrspace.h> #include <asm/byteorder.h> +#include <asm/cpu-features.h> +#include <asm/pgtable-bits.h> +#include <asm/processor.h> +#include <asm/string.h> + +#include <ioremap.h> +#include <mangle-port.h> +#include <spaces.h> /* * Slowdown I/O port space accesses for antique hardware. @@ -23,44 +30,20 @@ #undef CONF_SLOWDOWN_IO /* - * Sane hardware offers swapping of I/O space accesses in hardware; less - * sane hardware forces software to fiddle with this ... + * Raw operations are never swapped in software. OTOH values that raw + * operations are working on may or may not have been swapped by the bus + * hardware. An example use would be for flash memory that's used for + * execute in place. */ -#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__) +# define __raw_ioswabb(a, x) (x) +# define __raw_ioswabw(a, x) (x) +# define __raw_ioswabl(a, x) (x) +# define __raw_ioswabq(a, x) (x) +# define ____raw_ioswabq(a, x) (x) -#define __ioswab8(x) (x) -#define __ioswab16(x) swab16(x) -#define __ioswab32(x) swab32(x) +/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ -#else - -#define __ioswab8(x) (x) -#define __ioswab16(x) (x) -#define __ioswab32(x) (x) - -#endif - -/* - * This file contains the definitions for the MIPS counterpart of the - * x86 in/out instructions. This heap of macros and C results in much - * better code than the approach of doing it in plain C. The macros - * result in code that is to fast for certain hardware. On the other - * side the performance of the string functions should be improved for - * sake of certain devices like EIDE disks that do highspeed polled I/O. - * - * Ralf - * - * This file contains the definitions for the x86 IO instructions - * inb/inw/inl/outb/outw/outl and the "string versions" of the same - * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" - * versions of the single-IO instructions (inb_p/inw_p/..). - * - * This file is not meant to be obfuscating: it's just complicated - * to (a) handle it all in a way that makes gcc able to optimize it - * as well as possible and (b) trying to avoid writing the same thing - * over and over again with slight variations and possibly making a - * mistake somewhere. - */ +#define IO_SPACE_LIMIT 0xffff /* * On MIPS I/O ports are memory mapped, so we access them using normal @@ -84,6 +67,7 @@ extern const unsigned long mips_io_port_base; static inline void set_io_port_base(unsigned long base) { * (unsigned long *) &mips_io_port_base = base; + barrier(); } /* @@ -114,378 +98,429 @@ static inline void set_io_port_base(unsigned long base) #endif /* - * Change virtual addresses to physical addresses and vv. - * These are trivial on the 1:1 Linux/MIPS mapping + * virt_to_phys - map virtual addresses to physical + * @address: address to remap + * + * The returned physical address is the physical (CPU) mapping for + * the memory address given. It is only valid to use this function on + * addresses directly mapped or allocated via kmalloc. + * + * This function does not give bus mappings for DMA transfers. In + * almost all conceivable cases a device driver should not be using + * this function */ -static inline phys_addr_t virt_to_phys(volatile void * address) +static inline unsigned long virt_to_phys(volatile const void *address) { -#ifndef CONFIG_64BIT - return CPHYSADDR(address); + unsigned long addr = (unsigned long)address; + + /* this corresponds to kernel implementation of __pa() */ +#ifdef CONFIG_64BIT + if (addr < CKSEG0) + return XPHYSADDR(addr); + + return CPHYSADDR(addr); #else - return XPHYSADDR(address); + return addr - PAGE_OFFSET + PHYS_OFFSET; #endif } -static inline void * phys_to_virt(unsigned long address) +/* + * phys_to_virt - map physical address to virtual + * @address: address to remap + * + * The returned virtual address is a current CPU mapping for + * the memory address given. It is only valid to use this function on + * addresses that have a kernel mapping + * + * This function does not handle bus mappings for DMA transfers. In + * almost all conceivable cases a device driver should not be using + * this function + */ +static inline void *phys_to_virt(unsigned long address) { -#ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); -#else - return (void *)CKSEG0ADDR(address); -#endif + return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); } /* - * IO bus memory addresses are also 1:1 with the physical address + * ISA I/O bus memory addresses are 1:1 with the physical address. */ -static inline unsigned long virt_to_bus(volatile void * address) +static inline unsigned long isa_virt_to_bus(volatile void *address) { -#ifndef CONFIG_64BIT - return CPHYSADDR(address); -#else - return XPHYSADDR(address); -#endif + return (unsigned long)address - PAGE_OFFSET; } -static inline void * bus_to_virt(unsigned long address) +static inline void *isa_bus_to_virt(unsigned long address) { -#ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); -#else - return (void *)CKSEG0ADDR(address); -#endif + return (void *)(address + PAGE_OFFSET); } +#define isa_page_to_bus page_to_phys + /* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. + * However PCI ones are not necessarily 1:1 and therefore these interfaces + * are forbidden in portable PCI drivers. + * + * Allow them for x86 for legacy drivers, though. */ -extern unsigned long isa_slot_offset; +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt -extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); - -#if 0 -static inline void *ioremap(unsigned long offset, unsigned long size) +static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size, + unsigned long flags) { - return __ioremap(offset, size, _CACHE_UNCACHED); -} + void __iomem *addr; + phys_addr_t phys_addr; -static inline void *ioremap_nocache(unsigned long offset, unsigned long size) -{ - return __ioremap(offset, size, _CACHE_UNCACHED); -} + addr = plat_ioremap(offset, size, flags); + if (addr) + return addr; -extern void iounmap(void *addr); -#endif + phys_addr = fixup_bigphys_addr(offset, size); + return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr); +} /* - * XXX We need system specific versions of these to handle EISA address bits - * 24-31 on SNI. - * XXX more SNI hacks. + * ioremap - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. */ -#define __raw_readb(addr) (*(volatile unsigned char *)(addr)) -#define __raw_readw(addr) (*(volatile unsigned short *)(addr)) -#define __raw_readl(addr) (*(volatile unsigned int *)(addr)) -#define readb(addr) __raw_readb((addr)) -#define readw(addr) __ioswab16(__raw_readw((addr))) -#define readl(addr) __ioswab32(__raw_readl((addr))) - -#define __raw_writeb(b, addr) (*(volatile unsigned char *)(addr)) = (b) -#define __raw_writew(b, addr) (*(volatile unsigned short *)(addr)) = (b) -#define __raw_writel(b, addr) (*(volatile unsigned int *)(addr)) = (b) -#define writeb(b, addr) __raw_writeb((b), (addr)) -#define writew(b, addr) __raw_writew(__ioswab16(b), (addr)) -#define writel(b, addr) __raw_writel(__ioswab32(b), (addr)) - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -/* END SNI HACKS ... */ +#define ioremap(offset, size) \ + __ioremap_mode((offset), (size), _CACHE_UNCACHED) /* - * ISA space is 'always mapped' on currently supported MIPS systems, no need - * to explicitly ioremap() it. The fact that the ISA IO space is mapped - * to PAGE_OFFSET is pure coincidence - it does not mean ISA values - * are physical addresses. The following constant pointer can be - * used as the IO-area pointer (it can be iounmapped as well, so the - * analogy with PCI is quite large): + * ioremap_nocache - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap_nocache performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. + * + * This version of ioremap ensures that the memory is marked uncachable + * on the CPU as well as honouring existing caching rules from things like + * the PCI bus. Note that there are other caches and buffers on many + * busses. In particular driver authors should read up on PCI writes + * + * It's useful if some control registers are in such an area and + * write combining or read caching is not desirable: */ -#define __ISA_IO_base ((char *)(PAGE_OFFSET)) +#define ioremap_nocache(offset, size) \ + __ioremap_mode((offset), (size), _CACHE_UNCACHED) +#define ioremap_uc ioremap_nocache -#define isa_readb(a) readb(a) -#define isa_readw(a) readw(a) -#define isa_readl(a) readl(a) -#define isa_writeb(b,a) writeb(b,a) -#define isa_writew(w,a) writew(w,a) -#define isa_writel(l,a) writel(l,a) - -#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) -#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) +/* + * ioremap_cachable - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap_nocache performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. + * + * This version of ioremap ensures that the memory is marked cachable by + * the CPU. Also enables full write-combining. Useful for some + * memory-like regions on I/O busses. + */ +#define ioremap_cachable(offset, size) \ + __ioremap_mode((offset), (size), _page_cachable_default) /* - * We don't have csum_partial_copy_fromio() yet, so we cheat here and - * just copy it. The net code will then do the checksum later. + * These two are MIPS specific ioremap variant. ioremap_cacheable_cow + * requests a cachable mapping, ioremap_uncached_accelerated requests a + * mapping using the uncached accelerated mode which isn't supported on + * all processors. */ -#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) -#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d)) +#define ioremap_cacheable_cow(offset, size) \ + __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) +#define ioremap_uncached_accelerated(offset, size) \ + __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) -static inline int check_signature(unsigned long io_addr, - const unsigned char *signature, int length) +static inline void iounmap(const volatile void __iomem *addr) { - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; + plat_iounmap(addr); } -#define isa_check_signature(io, s, l) check_signature(i,s,l) -/* - * Talk about misusing macros.. - */ +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define war_octeon_io_reorder_wmb() wmb() +#else +#define war_octeon_io_reorder_wmb() do { } while (0) +#endif -#define __OUT1(s) \ -static inline void __out##s(unsigned int value, unsigned int port) { +#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ + \ +static inline void pfx##write##bwlq(type val, \ + volatile void __iomem *mem) \ +{ \ + volatile type *__mem; \ + type __val; \ + \ + war_octeon_io_reorder_wmb(); \ + \ + __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ + \ + __val = pfx##ioswab##bwlq(__mem, val); \ + \ + if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ + *__mem = __val; \ + else if (cpu_has_64bits) { \ + type __tmp; \ + \ + __asm__ __volatile__( \ + ".set arch=r4000" "\t\t# __writeq""\n\t" \ + "dsll32 %L0, %L0, 0" "\n\t" \ + "dsrl32 %L0, %L0, 0" "\n\t" \ + "dsll32 %M0, %M0, 0" "\n\t" \ + "or %L0, %L0, %M0" "\n\t" \ + "sd %L0, %2" "\n\t" \ + ".set mips0" "\n" \ + : "=r" (__tmp) \ + : "0" (__val), "m" (*__mem)); \ + } else \ + BUG(); \ +} \ + \ +static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ +{ \ + volatile type *__mem; \ + type __val; \ + \ + __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ + \ + if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ + __val = *__mem; \ + else if (cpu_has_64bits) { \ + __asm__ __volatile__( \ + ".set arch=r4000" "\t\t# __readq" "\n\t" \ + "ld %L0, %1" "\n\t" \ + "dsra32 %M0, %L0, 0" "\n\t" \ + "sll %L0, %L0, 0" "\n\t" \ + ".set mips0" "\n" \ + : "=r" (__val) \ + : "m" (*__mem)); \ + } else { \ + __val = 0; \ + BUG(); \ + } \ + \ + return pfx##ioswab##bwlq(__mem, __val); \ +} -#define __OUT2(m) \ -__asm__ __volatile__ ("s" #m "\t%0,%1(%2)" +#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ + \ +static inline void pfx##out##bwlq##p(type val, unsigned long port) \ +{ \ + volatile type *__addr; \ + type __val; \ + \ + war_octeon_io_reorder_wmb(); \ + \ + __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ + \ + __val = pfx##ioswab##bwlq(__addr, val); \ + \ + /* Really, we want this to be atomic */ \ + BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ + \ + *__addr = __val; \ + slow; \ +} \ + \ +static inline type pfx##in##bwlq##p(unsigned long port) \ +{ \ + volatile type *__addr; \ + type __val; \ + \ + __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ + \ + BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ + \ + __val = *__addr; \ + slow; \ + \ + return pfx##ioswab##bwlq(__addr, __val); \ +} -#define __OUT(m,s,w) \ -__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \ -__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \ -__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \ - SLOW_DOWN_IO; } \ -__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \ - SLOW_DOWN_IO; } +#define __BUILD_MEMORY_PFX(bus, bwlq, type) \ + \ +__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) + +#define BUILDIO_MEM(bwlq, type) \ + \ +__BUILD_MEMORY_PFX(__raw_, bwlq, type) \ +__BUILD_MEMORY_PFX(, bwlq, type) \ +__BUILD_MEMORY_PFX(__mem_, bwlq, type) \ + +BUILDIO_MEM(b, u8) +BUILDIO_MEM(w, u16) +BUILDIO_MEM(l, u32) +BUILDIO_MEM(q, u64) + +#define __BUILD_IOPORT_PFX(bus, bwlq, type) \ + __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ + __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) + +#define BUILDIO_IOPORT(bwlq, type) \ + __BUILD_IOPORT_PFX(, bwlq, type) \ + __BUILD_IOPORT_PFX(__mem_, bwlq, type) + +BUILDIO_IOPORT(b, u8) +BUILDIO_IOPORT(w, u16) +BUILDIO_IOPORT(l, u32) +#ifdef CONFIG_64BIT +BUILDIO_IOPORT(q, u64) +#endif -#define __IN1(t,s) \ -static inline t __in##s(unsigned int port) { t _v; +#define __BUILDIO(bwlq, type) \ + \ +__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) + +__BUILDIO(q, u64) + +#define readb_relaxed readb +#define readw_relaxed readw +#define readl_relaxed readl +#define readq_relaxed readq + +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel +#define writeq_relaxed writeq + +#define readb_be(addr) \ + __raw_readb((__force unsigned *)(addr)) +#define readw_be(addr) \ + be16_to_cpu(__raw_readw((__force unsigned *)(addr))) +#define readl_be(addr) \ + be32_to_cpu(__raw_readl((__force unsigned *)(addr))) +#define readq_be(addr) \ + be64_to_cpu(__raw_readq((__force unsigned *)(addr))) + +#define writeb_be(val, addr) \ + __raw_writeb((val), (__force unsigned *)(addr)) +#define writew_be(val, addr) \ + __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) +#define writel_be(val, addr) \ + __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) +#define writeq_be(val, addr) \ + __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) /* - * Required nops will be inserted by the assembler + * Some code tests for these symbols */ -#define __IN2(m) \ -__asm__ __volatile__ ("l" #m "\t%0,%1(%2)" - -#define __IN(t,m,s,w) \ -__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \ -__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \ -__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \ -__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); } - -#define __INS1(s) \ -static inline void __ins##s(unsigned int port, void * addr, unsigned long count) { - -#define __INS2(m) \ -if (count) \ -__asm__ __volatile__ ( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n" \ - "1:\tl" #m "\t$1,%4(%5)\n\t" \ - "subu\t%1,1\n\t" \ - "s" #m "\t$1,(%0)\n\t" \ - "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%6\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" - -#define __INS(m,s,i) \ -__INS1(s) __INS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), \ - "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ -__INS1(s##c) __INS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), \ - "r" (mips_io_port_base), "I" (i) \ - : "$1");} - -#define __OUTS1(s) \ -static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) { - -#define __OUTS2(m) \ -if (count) \ -__asm__ __volatile__ ( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n" \ - "1:\tl" #m "\t$1,(%0)\n\t" \ - "subu\t%1,1\n\t" \ - "s" #m "\t$1,%4(%5)\n\t" \ - "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%6\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" - -#define __OUTS(m,s,i) \ -__OUTS1(s) __OUTS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ -__OUTS1(s##c) __OUTS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \ - : "$1");} - -__IN(unsigned char,b,b,8) -__IN(unsigned short,h,w,16) -__IN(unsigned int,w,l,32) - -__OUT(b,b,8) -__OUT(h,w,16) -__OUT(w,l,32) - -__INS(b,b,1) -__INS(h,w,2) -__INS(w,l,4) - -__OUTS(b,b,1) -__OUTS(h,w,2) -__OUTS(w,l,4) +#define readq readq +#define writeq writeq + +#define __BUILD_MEMORY_STRING(bwlq, type) \ + \ +static inline void writes##bwlq(volatile void __iomem *mem, \ + const void *addr, unsigned int count) \ +{ \ + const volatile type *__addr = addr; \ + \ + while (count--) { \ + __mem_write##bwlq(*__addr, mem); \ + __addr++; \ + } \ +} \ + \ +static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ + unsigned int count) \ +{ \ + volatile type *__addr = addr; \ + \ + while (count--) { \ + *__addr = __mem_read##bwlq(mem); \ + __addr++; \ + } \ +} +#define __BUILD_IOPORT_STRING(bwlq, type) \ + \ +static inline void outs##bwlq(unsigned long port, const void *addr, \ + unsigned int count) \ +{ \ + const volatile type *__addr = addr; \ + \ + while (count--) { \ + __mem_out##bwlq(*__addr, port); \ + __addr++; \ + } \ +} \ + \ +static inline void ins##bwlq(unsigned long port, void *addr, \ + unsigned int count) \ +{ \ + volatile type *__addr = addr; \ + \ + while (count--) { \ + *__addr = __mem_in##bwlq(port); \ + __addr++; \ + } \ +} -/* - * Note that due to the way __builtin_constant_p() works, you - * - can't use it inside an inline function (it will never be true) - * - you don't have to worry about side effects within the __builtin.. - */ -#define outb(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outbc((val),(port)) : \ - __outb((val),(port))) - -#define inb(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inbc(port) : \ - __inb(port)) - -#define outb_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outbc_p((val),(port)) : \ - __outb_p((val),(port))) - -#define inb_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inbc_p(port) : \ - __inb_p(port)) - -#define outw(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outwc((val),(port)) : \ - __outw((val),(port))) - -#define inw(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inwc(port) : \ - __inw(port)) - -#define outw_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outwc_p((val),(port)) : \ - __outw_p((val),(port))) - -#define inw_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inwc_p(port) : \ - __inw_p(port)) - -#define outl(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outlc((val),(port)) : \ - __outl((val),(port))) - -#define inl(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inlc(port) : \ - __inl(port)) - -#define outl_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outlc_p((val),(port)) : \ - __outl_p((val),(port))) - -#define inl_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inlc_p(port) : \ - __inl_p(port)) - - -#define outsb(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outsbc((port),(addr),(count)) : \ - __outsb ((port),(addr),(count))) - -#define insb(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __insbc((port),(addr),(count)) : \ - __insb((port),(addr),(count))) - -#define outsw(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outswc((port),(addr),(count)) : \ - __outsw ((port),(addr),(count))) - -#define insw(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inswc((port),(addr),(count)) : \ - __insw((port),(addr),(count))) - -#define outsl(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outslc((port),(addr),(count)) : \ - __outsl ((port),(addr),(count))) - -#define insl(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inslc((port),(addr),(count)) : \ - __insl((port),(addr),(count))) +#define BUILDSTRING(bwlq, type) \ + \ +__BUILD_MEMORY_STRING(bwlq, type) \ +__BUILD_IOPORT_STRING(bwlq, type) -#define IO_SPACE_LIMIT 0xffff +BUILDSTRING(b, u8) +BUILDSTRING(w, u16) +BUILDSTRING(l, u32) +#ifdef CONFIG_64BIT +BUILDSTRING(q, u64) +#endif -/* - * The caches on some architectures aren't dma-coherent and have need to - * handle this in software. There are three types of operations that - * can be applied to dma buffers. - * - * - dma_cache_wback_inv(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_wback(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_inv(start, size) invalidates the affected parts of the - * caches. Dirty lines of the caches may be written back or simply - * be discarded. This operation is necessary before dma operations - * to the memory. - */ -extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); -extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); -extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); -#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size) -#define dma_cache_wback(start,size) _dma_cache_wback(start,size) -#define dma_cache_inv(start,size) _dma_cache_inv(start,size) +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define mmiowb() wmb() +#else +/* Depends on MIPS II instruction set */ +#define mmiowb() asm volatile ("sync" ::: "memory") +#endif -static inline void sync(void) +static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) +{ + memset((void __force *)addr, val, count); +} +static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) +{ + memcpy(dst, (void __force *)src, count); +} +static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) { + memcpy((void __force *)dst, src, count); } /* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". + * Read a 32-bit register that requires a 64-bit read cycle on the bus. + * Avoid interrupt mucking, just adjust the address for 4-byte access. + * Assume the addresses are 8-byte aligned. + */ +#ifdef __MIPSEB__ +#define __CSR_32_ADJUST 4 +#else +#define __CSR_32_ADJUST 0 +#endif + +#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) +#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) + +/* + * U-Boot specific */ -#define MAP_NOCACHE (0) +#define sync() mmiowb() + +#define MAP_NOCACHE (1) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) #define MAP_WRTHROUGH (0) @@ -493,6 +528,9 @@ static inline void sync(void) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { + if (flags == MAP_NOCACHE) + return ioremap(paddr, len); + return (void *)paddr; } @@ -501,7 +539,61 @@ map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) */ static inline void unmap_physmem(void *vaddr, unsigned long flags) { +} +#define __BUILD_CLRBITS(bwlq, sfx, end, type) \ + \ +static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \ +{ \ + type __val = __raw_read##bwlq(mem); \ + __val = end##_to_cpu(__val); \ + __val &= ~clr; \ + __val = cpu_to_##end(__val); \ + __raw_write##bwlq(__val, mem); \ } +#define __BUILD_SETBITS(bwlq, sfx, end, type) \ + \ +static inline void setbits_##sfx(volatile void __iomem *mem, type set) \ +{ \ + type __val = __raw_read##bwlq(mem); \ + __val = end##_to_cpu(__val); \ + __val |= set; \ + __val = cpu_to_##end(__val); \ + __raw_write##bwlq(__val, mem); \ +} + +#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \ + \ +static inline void clrsetbits_##sfx(volatile void __iomem *mem, \ + type clr, type set) \ +{ \ + type __val = __raw_read##bwlq(mem); \ + __val = end##_to_cpu(__val); \ + __val &= ~clr; \ + __val |= set; \ + __val = cpu_to_##end(__val); \ + __raw_write##bwlq(__val, mem); \ +} + +#define BUILD_CLRSETBITS(bwlq, sfx, end, type) \ + \ +__BUILD_CLRBITS(bwlq, sfx, end, type) \ +__BUILD_SETBITS(bwlq, sfx, end, type) \ +__BUILD_CLRSETBITS(bwlq, sfx, end, type) + +#define __to_cpu(v) (v) +#define cpu_to__(v) (v) + +BUILD_CLRSETBITS(b, 8, _, u8) +BUILD_CLRSETBITS(w, le16, le16, u16) +BUILD_CLRSETBITS(w, be16, be16, u16) +BUILD_CLRSETBITS(w, 16, _, u16) +BUILD_CLRSETBITS(l, le32, le32, u32) +BUILD_CLRSETBITS(l, be32, be32, u32) +BUILD_CLRSETBITS(l, 32, _, u32) +BUILD_CLRSETBITS(q, le64, le64, u64) +BUILD_CLRSETBITS(q, be64, be64, u64) +BUILD_CLRSETBITS(q, 64, _, u64) + #endif /* _ASM_IO_H */ diff --git a/arch/mips/include/asm/isadep.h b/arch/mips/include/asm/isadep.h index 24c6cda793..3d79ebcf59 100644 --- a/arch/mips/include/asm/isadep.h +++ b/arch/mips/include/asm/isadep.h @@ -4,6 +4,8 @@ * of Coprocessor 0 registers. * * Copyright (c) 1998 Harald Koerfgen + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ISADEP_H @@ -18,7 +20,7 @@ * kernel or user mode? (CP0_STATUS) */ #define KU_MASK 0x08 -#define KU_USER 0x08 +#define KU_USER 0x08 #define KU_KERN 0x00 #else @@ -26,7 +28,7 @@ * kernel or user mode? */ #define KU_MASK 0x18 -#define KU_USER 0x10 +#define KU_USER 0x10 #define KU_KERN 0x00 #endif diff --git a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h new file mode 100644 index 0000000000..613f844f08 --- /dev/null +++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2003 Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H + +/* Intentionally empty file ... */ + +#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h new file mode 100644 index 0000000000..6b191d54a6 --- /dev/null +++ b/arch/mips/include/asm/mach-generic/ioremap.h @@ -0,0 +1,32 @@ +/* + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_GENERIC_IOREMAP_H +#define __ASM_MACH_GENERIC_IOREMAP_H + +#include <linux/types.h> + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, + phys_addr_t size) +{ + return phys_addr; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} + +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT + +#endif /* __ASM_MACH_GENERIC_IOREMAP_H */ diff --git a/arch/mips/include/asm/mach-generic/mangle-port.h b/arch/mips/include/asm/mach-generic/mangle-port.h new file mode 100644 index 0000000000..f18e53f7b8 --- /dev/null +++ b/arch/mips/include/asm/mach-generic/mangle-port.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2003, 2004 Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H +#define __ASM_MACH_GENERIC_MANGLE_PORT_H + +#define __swizzle_addr_b(port) (port) +#define __swizzle_addr_w(port) (port) +#define __swizzle_addr_l(port) (port) +#define __swizzle_addr_q(port) (port) + +/* + * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; + * less sane hardware forces software to fiddle with this... + * + * Regardless, if the host bus endianness mismatches that of PCI/ISA, then + * you can't have the numerical value of data and byte addresses within + * multibyte quantities both preserved at the same time. Hence two + * variations of functions: non-prefixed ones that preserve the value + * and prefixed ones that preserve byte addresses. The latters are + * typically used for moving raw data between a peripheral and memory (cf. + * string I/O functions), hence the "__mem_" prefix. + */ +#if defined(CONFIG_SWAP_IO_SPACE) + +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) le16_to_cpu(x) +# define __mem_ioswabw(a, x) (x) +# define ioswabl(a, x) le32_to_cpu(x) +# define __mem_ioswabl(a, x) (x) +# define ioswabq(a, x) le64_to_cpu(x) +# define __mem_ioswabq(a, x) (x) + +#else + +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) + +#endif + +#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h new file mode 100644 index 0000000000..ab06674b14 --- /dev/null +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef _ASM_MACH_GENERIC_SPACES_H +#define _ASM_MACH_GENERIC_SPACES_H + +#include <asm/const.h> + +/* + * This gives the physical RAM offset. + */ +#ifndef PHYS_OFFSET +#define PHYS_OFFSET _AC(0, UL) +#endif + +#ifdef CONFIG_32BIT +#ifdef CONFIG_KVM_GUEST +#define CAC_BASE _AC(0x40000000, UL) +#else +#define CAC_BASE _AC(0x80000000, UL) +#endif +#ifndef IO_BASE +#define IO_BASE _AC(0xa0000000, UL) +#endif +#ifndef UNCAC_BASE +#define UNCAC_BASE _AC(0xa0000000, UL) +#endif + +#ifndef MAP_BASE +#ifdef CONFIG_KVM_GUEST +#define MAP_BASE _AC(0x60000000, UL) +#else +#define MAP_BASE _AC(0xc0000000, UL) +#endif +#endif + +/* + * Memory above this physical address will be considered highmem. + */ +#ifndef HIGHMEM_START +#define HIGHMEM_START _AC(0x20000000, UL) +#endif + +#endif /* CONFIG_32BIT */ + +#ifdef CONFIG_64BIT + +#ifndef CAC_BASE +#ifdef CONFIG_DMA_NONCOHERENT +#define CAC_BASE _AC(0x9800000000000000, UL) +#else +#define CAC_BASE _AC(0xa800000000000000, UL) +#endif +#endif + +#ifndef IO_BASE +#define IO_BASE _AC(0x9000000000000000, UL) +#endif + +#ifndef UNCAC_BASE +#define UNCAC_BASE _AC(0x9000000000000000, UL) +#endif + +#ifndef MAP_BASE +#define MAP_BASE _AC(0xc000000000000000, UL) +#endif + +/* + * Memory above this physical address will be considered highmem. + * Fixme: 59 bits is a fictive number and makes assumptions about processors + * in the distant future. Nobody will care for a few years :-) + */ +#ifndef HIGHMEM_START +#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL)) +#endif + +#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) + +#endif /* CONFIG_64BIT */ + +/* + * This handles the memory map. + */ +#ifndef PAGE_OFFSET +#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET) +#endif + +#ifndef FIXADDR_TOP +#ifdef CONFIG_KVM_GUEST +#define FIXADDR_TOP ((unsigned long)(long)(int)0x7ffe0000) +#else +#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) +#endif +#endif + +#endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index c7a08499ff..3185dc7abf 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1,22 +1,16 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle * Copyright (C) 2000 Silicon Graphics, Inc. * Modified for further R[236]000 support by Paul M. Antoine, 1996. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000, 07 MIPS Technologies, Inc. * Copyright (C) 2003, 2004 Maciej W. Rozycki + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_MIPSREGS_H #define _ASM_MIPSREGS_H -#if 0 -#include <linux/linkage.h> -#endif - /* * The following macros are especially useful for __asm__ * inline assembler. @@ -49,7 +43,9 @@ #define CP0_PAGEMASK $5 #define CP0_WIRED $6 #define CP0_INFO $7 +#define CP0_HWRENA $7, 0 #define CP0_BADVADDR $8 +#define CP0_BADINSTR $8, 1 #define CP0_COUNT $9 #define CP0_ENTRYHI $10 #define CP0_COMPARE $11 @@ -57,7 +53,11 @@ #define CP0_CAUSE $13 #define CP0_EPC $14 #define CP0_PRID $15 +#define CP0_EBASE $15, 1 +#define CP0_CMGCRBASE $15, 3 #define CP0_CONFIG $16 +#define CP0_CONFIG3 $16, 3 +#define CP0_CONFIG5 $16, 5 #define CP0_LLADDR $17 #define CP0_WATCHLO $18 #define CP0_WATCHHI $19 @@ -98,74 +98,36 @@ /* * Coprocessor 0 Set 2 register names */ -#define CP0_S2_SRSCTL $12 /* MIPSR2 */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ /* * Coprocessor 0 Set 3 register names */ -#define CP0_S3_SRSMAP $12 /* MIPSR2 */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ /* * TX39 Series */ #define CP0_TX39_CACHE $7 -/* - * Coprocessor 1 (FPU) register names - */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 -/* - * FPU Status Register Values - */ -/* - * Status Register Values - */ +/* Generic EntryLo bit definitions */ +#define ENTRYLO_G (_ULCAST_(1) << 0) +#define ENTRYLO_V (_ULCAST_(1) << 1) +#define ENTRYLO_D (_ULCAST_(1) << 2) +#define ENTRYLO_C_SHIFT 3 +#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT) -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ +/* R3000 EntryLo bit definitions */ +#define R3K_ENTRYLO_G (_ULCAST_(1) << 8) +#define R3K_ENTRYLO_V (_ULCAST_(1) << 9) +#define R3K_ENTRYLO_D (_ULCAST_(1) << 10) +#define R3K_ENTRYLO_N (_ULCAST_(1) << 11) -/* - * X the exception cause indicator - * E the exception enable - * S the sticky/flag bit - */ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 - -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 - -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 - -/* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ +/* MIPS32/64 EntryLo bit definitions */ +#define MIPS_ENTRYLO_PFN_SHIFT 6 +#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2)) +#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1)) /* * Values for PageMask register @@ -183,14 +145,22 @@ #else #define PM_4K 0x00000000 +#define PM_8K 0x00002000 #define PM_16K 0x00006000 +#define PM_32K 0x0000e000 #define PM_64K 0x0001e000 +#define PM_128K 0x0003e000 #define PM_256K 0x0007e000 +#define PM_512K 0x000fe000 #define PM_1M 0x001fe000 +#define PM_2M 0x003fe000 #define PM_4M 0x007fe000 +#define PM_8M 0x00ffe000 #define PM_16M 0x01ffe000 +#define PM_32M 0x03ffe000 #define PM_64M 0x07ffe000 #define PM_256M 0x1fffe000 +#define PM_1G 0x7fffe000 #endif @@ -208,10 +178,22 @@ #define PL_256M 28 /* + * PageGrain bits + */ +#define PG_RIE (_ULCAST_(1) << 31) +#define PG_XIE (_ULCAST_(1) << 30) +#define PG_ELPA (_ULCAST_(1) << 29) +#define PG_ESP (_ULCAST_(1) << 28) +#define PG_IEC (_ULCAST_(1) << 27) + +/* MIPS32/64 EntryHI bit definitions */ +#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) + +/* * R4x00 interrupt enable / cause bits */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) #define IE_IRQ0 (_ULCAST_(1) << 10) #define IE_IRQ1 (_ULCAST_(1) << 11) #define IE_IRQ2 (_ULCAST_(1) << 12) @@ -222,8 +204,8 @@ /* * R4x00 interrupt cause bits */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) #define C_IRQ0 (_ULCAST_(1) << 10) #define C_IRQ1 (_ULCAST_(1) << 11) #define C_IRQ2 (_ULCAST_(1) << 12) @@ -271,7 +253,7 @@ /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_UM (_ULCAST_(1) << 4) #define ST0_IL (_ULCAST_(1) << 23) #define ST0_DL (_ULCAST_(1) << 24) @@ -281,75 +263,43 @@ #define ST0_MX 0x01000000 /* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 - -/* * Status register bits available in all MIPS CPUs. */ #define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) #define ST0_CH 0x00040000 +#define ST0_NMI 0x00080000 #define ST0_SR 0x00100000 #define ST0_TS 0x00200000 #define ST0_BEV 0x00400000 @@ -363,36 +313,52 @@ #define ST0_XX 0x80000000 /* MIPS IV naming */ /* + * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) + */ +#define INTCTLB_IPFDC 23 +#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC) +#define INTCTLB_IPPCI 26 +#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) +#define INTCTLB_IPTI 29 +#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) + +/* * Bitfields and bit numbers in the coprocessor 0 cause register. * * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_FDCI 21 +#define CAUSEF_FDCI (_ULCAST_(1) << 21) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_PCI 26 +#define CAUSEF_PCI (_ULCAST_(1) << 26) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_TI 30 +#define CAUSEF_TI (_ULCAST_(1) << 30) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) /* * Bits in the coprocessor 0 config register. @@ -410,43 +376,43 @@ #define CONF_BE (_ULCAST_(1) << 15) /* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) #define CONF_EB (_ULCAST_(1) << 13) #define CONF_EM (_ULCAST_(1) << 14) #define CONF_SM (_ULCAST_(1) << 16) #define CONF_SC (_ULCAST_(1) << 17) #define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EP (_ULCAST_(15) << 24) #define CONF_EC (_ULCAST_(7) << 28) #define CONF_CM (_ULCAST_(1) << 31) -/* Bits specific to the R4xx0. */ +/* Bits specific to the R4xx0. */ #define R4K_CONF_SW (_ULCAST_(1) << 20) #define R4K_CONF_SS (_ULCAST_(1) << 21) #define R4K_CONF_SB (_ULCAST_(3) << 22) -/* Bits specific to the R5000. */ +/* Bits specific to the R5000. */ #define R5K_CONF_SE (_ULCAST_(1) << 12) #define R5K_CONF_SS (_ULCAST_(3) << 20) -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) +/* Bits specific to the RM7000. */ +#define RM7K_CONF_SE (_ULCAST_(1) << 3) #define RM7K_CONF_TE (_ULCAST_(1) << 12) #define RM7K_CONF_CLK (_ULCAST_(1) << 16) #define RM7K_CONF_TC (_ULCAST_(1) << 17) #define RM7K_CONF_SI (_ULCAST_(3) << 20) #define RM7K_CONF_SC (_ULCAST_(1) << 31) -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15) << 9) #define R10K_CONF_SB (_ULCAST_(1) << 13) #define R10K_CONF_SK (_ULCAST_(1) << 14) #define R10K_CONF_SS (_ULCAST_(7) << 16) @@ -454,14 +420,14 @@ #define R10K_CONF_DC (_ULCAST_(7) << 26) #define R10K_CONF_IC (_ULCAST_(7) << 29) -/* Bits specific to the VR41xx. */ +/* Bits specific to the VR41xx. */ #define VR41_CONF_CS (_ULCAST_(1) << 12) #define VR41_CONF_P4K (_ULCAST_(1) << 13) #define VR41_CONF_BP (_ULCAST_(1) << 16) #define VR41_CONF_M16 (_ULCAST_(1) << 20) #define VR41_CONF_AD (_ULCAST_(1) << 23) -/* Bits specific to the R30xx. */ +/* Bits specific to the R30xx. */ #define R30XX_CONF_FDM (_ULCAST_(1) << 19) #define R30XX_CONF_REV (_ULCAST_(1) << 22) #define R30XX_CONF_AC (_ULCAST_(1) << 23) @@ -478,8 +444,10 @@ #define TX49_CONF_HALT (_ULCAST_(1) << 18) #define TX49_CONF_CWFON (_ULCAST_(1) << 27) -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7) +#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) #define MIPS_CONF_AR (_ULCAST_(7) << 10) #define MIPS_CONF_AT (_ULCAST_(3) << 13) #define MIPS_CONF_M (_ULCAST_(1) << 31) @@ -487,50 +455,245 @@ /* * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. */ -#define MIPS_CONF1_FP (_ULCAST_(1) << 0) -#define MIPS_CONF1_EP (_ULCAST_(1) << 1) -#define MIPS_CONF1_CA (_ULCAST_(1) << 2) -#define MIPS_CONF1_WR (_ULCAST_(1) << 3) -#define MIPS_CONF1_PC (_ULCAST_(1) << 4) -#define MIPS_CONF1_MD (_ULCAST_(1) << 5) -#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA_SHIFT 7 -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) -#define MIPS_CONF1_DL_SHIFT 10 +#define MIPS_CONF1_FP (_ULCAST_(1) << 0) +#define MIPS_CONF1_EP (_ULCAST_(1) << 1) +#define MIPS_CONF1_CA (_ULCAST_(1) << 2) +#define MIPS_CONF1_WR (_ULCAST_(1) << 3) +#define MIPS_CONF1_PC (_ULCAST_(1) << 4) +#define MIPS_CONF1_MD (_ULCAST_(1) << 5) +#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA_SHF 7 +#define MIPS_CONF1_DA_SZ 3 +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL_SHF 10 +#define MIPS_CONF1_DL_SZ 3 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) -#define MIPS_CONF1_DS_SHIFT 13 +#define MIPS_CONF1_DS_SHF 13 +#define MIPS_CONF1_DS_SZ 3 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) -#define MIPS_CONF1_IA_SHIFT 16 +#define MIPS_CONF1_IA_SHF 16 +#define MIPS_CONF1_IA_SZ 3 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) -#define MIPS_CONF1_IL_SHIFT 19 +#define MIPS_CONF1_IL_SHF 19 +#define MIPS_CONF1_IL_SZ 3 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) -#define MIPS_CONF1_IS_SHIFT 22 +#define MIPS_CONF1_IS_SHF 22 +#define MIPS_CONF1_IS_SZ 3 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) -#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) - -#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) -#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) -#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) -#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) -#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) -#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) -#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) +#define MIPS_CONF1_TLBS_SHIFT (25) +#define MIPS_CONF1_TLBS_SIZE (6) +#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) + +#define MIPS_CONF2_SA (_ULCAST_(15) << 0) +#define MIPS_CONF2_SL (_ULCAST_(15) << 4) +#define MIPS_CONF2_SS (_ULCAST_(15) << 8) +#define MIPS_CONF2_SU (_ULCAST_(15) << 12) +#define MIPS_CONF2_TA (_ULCAST_(15) << 16) +#define MIPS_CONF2_TL (_ULCAST_(15) << 20) +#define MIPS_CONF2_TS (_ULCAST_(15) << 24) #define MIPS_CONF2_TU (_ULCAST_(7) << 28) -#define MIPS_CONF3_TL (_ULCAST_(1) << 0) -#define MIPS_CONF3_SM (_ULCAST_(1) << 1) -#define MIPS_CONF3_MT (_ULCAST_(1) << 2) -#define MIPS_CONF3_SP (_ULCAST_(1) << 4) -#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) -#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) -#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_TL (_ULCAST_(1) << 0) +#define MIPS_CONF3_SM (_ULCAST_(1) << 1) +#define MIPS_CONF3_MT (_ULCAST_(1) << 2) +#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) +#define MIPS_CONF3_SP (_ULCAST_(1) << 4) +#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) +#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) +#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_ITL (_ULCAST_(1) << 8) +#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) +#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) +#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) +#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) +#define MIPS_CONF3_MCU (_ULCAST_(1) << 17) +#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) +#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) +#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) +#define MIPS_CONF3_PW (_ULCAST_(1) << 24) +#define MIPS_CONF3_SC (_ULCAST_(1) << 25) +#define MIPS_CONF3_BI (_ULCAST_(1) << 26) +#define MIPS_CONF3_BP (_ULCAST_(1) << 27) +#define MIPS_CONF3_MSA (_ULCAST_(1) << 28) +#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) +#define MIPS_CONF3_BPG (_ULCAST_(1) << 30) + +#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) +#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) +#define MIPS_CONF4_FTLBSETS_SHIFT (0) +#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) +#define MIPS_CONF4_FTLBWAYS_SHIFT (4) +#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) +#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) +/* bits 10:8 in FTLB-only configurations */ +#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) +/* bits 12:8 in VTLB-FTLB only configurations */ +#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) +#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) +#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) +#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) +#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) +#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) +#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) +#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) +#define MIPS_CONF4_AE (_ULCAST_(1) << 28) +#define MIPS_CONF4_IE (_ULCAST_(3) << 29) +#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) + +#define MIPS_CONF5_NF (_ULCAST_(1) << 0) +#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) +#define MIPS_CONF5_MRP (_ULCAST_(1) << 3) +#define MIPS_CONF5_LLB (_ULCAST_(1) << 4) +#define MIPS_CONF5_MVH (_ULCAST_(1) << 5) +#define MIPS_CONF5_FRE (_ULCAST_(1) << 8) +#define MIPS_CONF5_UFE (_ULCAST_(1) << 9) +#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) +#define MIPS_CONF5_EVA (_ULCAST_(1) << 28) +#define MIPS_CONF5_CV (_ULCAST_(1) << 29) +#define MIPS_CONF5_K (_ULCAST_(1) << 30) + +#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) +/* proAptiv FTLB on/off bit */ +#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) +/* FTLB probability bits */ +#define MIPS_CONF6_FTLBP_SHIFT (16) #define MIPS_CONF7_WII (_ULCAST_(1) << 31) #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) +#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) +#define MIPS_CONF7_AR (_ULCAST_(1) << 16) +/* FTLB probability bits for R6 */ +#define MIPS_CONF7_FTLBP_SHIFT (18) + +/* MAAR bit definitions */ +#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) +#define MIPS_MAAR_ADDR_SHIFT 12 +#define MIPS_MAAR_S (_ULCAST_(1) << 1) +#define MIPS_MAAR_V (_ULCAST_(1) << 0) + +/* CMGCRBase bit definitions */ +#define MIPS_CMGCRB_BASE 11 +#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) + +/* + * Bits in the MIPS32 Memory Segmentation registers. + */ +#define MIPS_SEGCFG_PA_SHIFT 9 +#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) +#define MIPS_SEGCFG_AM_SHIFT 4 +#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) +#define MIPS_SEGCFG_EU_SHIFT 3 +#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) +#define MIPS_SEGCFG_C_SHIFT 0 +#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) + +#define MIPS_SEGCFG_UUSK _ULCAST_(7) +#define MIPS_SEGCFG_USK _ULCAST_(5) +#define MIPS_SEGCFG_MUSUK _ULCAST_(4) +#define MIPS_SEGCFG_MUSK _ULCAST_(3) +#define MIPS_SEGCFG_MSK _ULCAST_(2) +#define MIPS_SEGCFG_MK _ULCAST_(1) +#define MIPS_SEGCFG_UK _ULCAST_(0) + +#define MIPS_PWFIELD_GDI_SHIFT 24 +#define MIPS_PWFIELD_GDI_MASK 0x3f000000 +#define MIPS_PWFIELD_UDI_SHIFT 18 +#define MIPS_PWFIELD_UDI_MASK 0x00fc0000 +#define MIPS_PWFIELD_MDI_SHIFT 12 +#define MIPS_PWFIELD_MDI_MASK 0x0003f000 +#define MIPS_PWFIELD_PTI_SHIFT 6 +#define MIPS_PWFIELD_PTI_MASK 0x00000fc0 +#define MIPS_PWFIELD_PTEI_SHIFT 0 +#define MIPS_PWFIELD_PTEI_MASK 0x0000003f + +#define MIPS_PWSIZE_GDW_SHIFT 24 +#define MIPS_PWSIZE_GDW_MASK 0x3f000000 +#define MIPS_PWSIZE_UDW_SHIFT 18 +#define MIPS_PWSIZE_UDW_MASK 0x00fc0000 +#define MIPS_PWSIZE_MDW_SHIFT 12 +#define MIPS_PWSIZE_MDW_MASK 0x0003f000 +#define MIPS_PWSIZE_PTW_SHIFT 6 +#define MIPS_PWSIZE_PTW_MASK 0x00000fc0 +#define MIPS_PWSIZE_PTEW_SHIFT 0 +#define MIPS_PWSIZE_PTEW_MASK 0x0000003f + +#define MIPS_PWCTL_PWEN_SHIFT 31 +#define MIPS_PWCTL_PWEN_MASK 0x80000000 +#define MIPS_PWCTL_DPH_SHIFT 7 +#define MIPS_PWCTL_DPH_MASK 0x00000080 +#define MIPS_PWCTL_HUGEPG_SHIFT 6 +#define MIPS_PWCTL_HUGEPG_MASK 0x00000060 +#define MIPS_PWCTL_PSN_SHIFT 0 +#define MIPS_PWCTL_PSN_MASK 0x0000003f + +/* CDMMBase register bit definitions */ +#define MIPS_CDMMBASE_SIZE_SHIFT 0 +#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) +#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9) +#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10) +#define MIPS_CDMMBASE_ADDR_SHIFT 11 +#define MIPS_CDMMBASE_ADDR_START 15 + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Interesting Bits in the R10K CP0 Branch Diagnostic Register + */ +/* Disable Branch Target Address Cache */ +#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27) +/* Enable Branch Prediction Global History */ +#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26) +/* Disable Branch Return Cache */ +#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22) + +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_UFR $1 +#define CP1_UNFR $4 +#define CP1_FCCR $25 +#define CP1_FEXR $26 +#define CP1_FENR $28 +#define CP1_STATUS $31 + + /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ @@ -541,11 +704,150 @@ #define MIPS_FPIR_W (_ULCAST_(1) << 20) #define MIPS_FPIR_L (_ULCAST_(1) << 21) #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) +#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) +#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) +#define MIPS_FPIR_FREP (_ULCAST_(1) << 29) + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. + */ +#define MIPS_FCCR_CONDX_S 0 +#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) +#define MIPS_FCCR_COND0_S 0 +#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) +#define MIPS_FCCR_COND1_S 1 +#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) +#define MIPS_FCCR_COND2_S 2 +#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) +#define MIPS_FCCR_COND3_S 3 +#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) +#define MIPS_FCCR_COND4_S 4 +#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) +#define MIPS_FCCR_COND5_S 5 +#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) +#define MIPS_FCCR_COND6_S 6 +#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) +#define MIPS_FCCR_COND7_S 7 +#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. + */ +#define MIPS_FENR_FS_S 2 +#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) + +/* + * FPU Status Register Values + */ +#define FPU_CSR_COND_S 23 /* $fcc0 */ +#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) + +#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ +#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) + +#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ +#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) +#define FPU_CSR_COND1_S 25 /* $fcc1 */ +#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) +#define FPU_CSR_COND2_S 26 /* $fcc2 */ +#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) +#define FPU_CSR_COND3_S 27 /* $fcc3 */ +#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) +#define FPU_CSR_COND4_S 28 /* $fcc4 */ +#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) +#define FPU_CSR_COND5_S 29 /* $fcc5 */ +#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) +#define FPU_CSR_COND6_S 30 /* $fcc6 */ +#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) +#define FPU_CSR_COND7_S 31 /* $fcc7 */ +#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) + +/* + * Bits 22:20 of the FPU Status Register will be read as 0, + * and should be written as zero. + */ +#define FPU_CSR_RSVD (_ULCAST_(7) << 20) + +#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) +#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) + +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ +#define FPU_CSR_RM 0x00000003 +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + #ifndef __ASSEMBLY__ /* - * Functions to access the R10000 performance counters. These are basically + * Macros for handling the ISA mode bit for MIPS16 and microMIPS. + */ +#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ + defined(CONFIG_SYS_SUPPORTS_MICROMIPS) +#define get_isa16_mode(x) ((x) & 0x1) +#define msk_isa16_mode(x) ((x) & ~0x1) +#define set_isa16_mode(x) do { (x) |= 0x1; } while (0) +#else +#define get_isa16_mode(x) 0 +#define msk_isa16_mode(x) (x) +#define set_isa16_mode(x) do { } while (0) +#endif + +/* + * microMIPS instructions can be 16-bit or 32-bit in length. This + * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. + */ +static inline int mm_insn_16bit(u16 insn) +{ + u16 opcode = (insn >> 10) & 0x7; + + return (opcode >= 1 && opcode <= 3) ? 1 : 0; +} + +/* + * TLB Invalidate Flush + */ +static inline void tlbinvf(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".word 0x42000004\n\t" /* tlbinvf */ + ".set pop"); +} + + +/* + * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit * performance counter number encoded into bits 1 ... 5 of the instruction. * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware @@ -589,6 +891,7 @@ do { \ : "r" (val), "i" (counter)); \ } while (0) + /* * Macros to access the system control coprocessor */ @@ -705,8 +1008,8 @@ do { \ ".set\tmips64\n\t" \ "dmfc0\t%M0, " #source "\n\t" \ "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ else \ @@ -714,8 +1017,8 @@ do { \ ".set\tmips64\n\t" \ "dmfc0\t%M0, " #source ", " #sel "\n\t" \ "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ local_irq_restore(__flags); \ @@ -751,15 +1054,57 @@ do { \ local_irq_restore(__flags); \ } while (0) +#define __readx_32bit_c0_register(source) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .set mips32r2 \n" \ + " .insn \n" \ + " # mfhc0 $1, %1 \n" \ + " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (source)); \ + __res; \ +}) + +#define __writex_32bit_c0_register(register, value) \ +({ \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .set mips32r2 \n" \ + " move $1, %0 \n" \ + " # mthc0 $1, %1 \n" \ + " .insn \n" \ + " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ + " .set pop \n" \ + : \ + : "r" (value), "i" (register)); \ +}) + #define read_c0_index() __read_32bit_c0_register($0, 0) #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) +#define read_c0_random() __read_32bit_c0_register($1, 0) +#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) + #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) +#define readx_c0_entrylo0() __readx_32bit_c0_register(2) +#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val) + #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) +#define readx_c0_entrylo1() __readx_32bit_c0_register(3) +#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val) + #define read_c0_conf() __read_32bit_c0_register($3, 0) #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) @@ -767,17 +1112,20 @@ do { \ #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) #define read_c0_userlocal() __read_ulong_c0_register($4, 2) -#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) +#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) +#define read_c0_pagegrain() __read_32bit_c0_register($5, 1) +#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) + #define read_c0_wired() __read_32bit_c0_register($6, 0) #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) #define read_c0_info() __read_32bit_c0_register($7, 0) -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) @@ -805,19 +1153,8 @@ do { \ #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) #define read_c0_status() __read_32bit_c0_register($12, 0) -#ifdef CONFIG_MIPS_MT_SMTC -#define write_c0_status(val) \ -do { \ - __write_32bit_c0_register($12, 0, val); \ - __ehb(); \ -} while (0) -#else -/* - * Legacy non-SMTC code, which may be hazardous - * but which might not support EHB - */ + #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#endif /* CONFIG_MIPS_MT_SMTC */ #define read_c0_cause() __read_32bit_c0_register($13, 0) #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) @@ -827,6 +1164,8 @@ do { \ #define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) + #define read_c0_config() __read_32bit_c0_register($16, 0) #define read_c0_config1() __read_32bit_c0_register($16, 1) #define read_c0_config2() __read_32bit_c0_register($16, 2) @@ -844,8 +1183,15 @@ do { \ #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) +#define read_c0_lladdr() __read_ulong_c0_register($17, 0) +#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) +#define read_c0_maar() __read_ulong_c0_register($17, 1) +#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) +#define read_c0_maari() __read_32bit_c0_register($17, 2) +#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) + /* - * The WatchLo register. There may be upto 8 of them. + * The WatchLo register. There may be up to 8 of them. */ #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) @@ -865,7 +1211,7 @@ do { \ #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) /* - * The WatchHi register. There may be upto 8 of them. + * The WatchHi register. There may be up to 8 of them. */ #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) @@ -892,15 +1238,15 @@ do { \ #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) #define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) - -/* RM9000 PerfControl performance counter control register */ -#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) -#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) #define read_c0_diag() __read_32bit_c0_register($22, 0) #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) +/* R10K CP0 Branch Diagnostic register is 64bits wide */ +#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0) +#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val) + #define read_c0_diag1() __read_32bit_c0_register($22, 1) #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) @@ -926,36 +1272,40 @@ do { \ * MIPS32 / MIPS64 performance counters */ #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) -#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) +#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) -#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) +#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) +#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) +#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) -#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) +#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) -#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) +#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) +#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) +#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) -#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) +#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) -#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) +#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) +#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) +#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) -#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) +#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) -#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) - -/* RM9000 PerfCount performance counter register */ -#define read_c0_perfcount() __read_64bit_c0_register($25, 0) -#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) +#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) +#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) +#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) #define read_c0_ecc() __read_32bit_c0_register($26, 0) #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) #define read_c0_taglo() __read_32bit_c0_register($28, 0) #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) @@ -963,6 +1313,12 @@ do { \ #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) +#define read_c0_ddatalo() __read_32bit_c0_register($28, 3) +#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) + +#define read_c0_staglo() __read_32bit_c0_register($28, 4) +#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) + #define read_c0_taghi() __read_32bit_c0_register($29, 0) #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) @@ -985,271 +1341,524 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) +#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) +#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) + +/* MIPSR3 */ +#define read_c0_segctl0() __read_32bit_c0_register($5, 2) +#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) + +#define read_c0_segctl1() __read_32bit_c0_register($5, 3) +#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) + +#define read_c0_segctl2() __read_32bit_c0_register($5, 4) +#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) + +/* Hardware Page Table Walker */ +#define read_c0_pwbase() __read_ulong_c0_register($5, 5) +#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) + +#define read_c0_pwfield() __read_ulong_c0_register($5, 6) +#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) + +#define read_c0_pwsize() __read_ulong_c0_register($5, 7) +#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) + +#define read_c0_pwctl() __read_32bit_c0_register($6, 6) +#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) + +/* Cavium OCTEON (cnMIPS) */ +#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) +#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) + +#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) +#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) + +#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) +#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) /* - * Macros to access the floating point coprocessor control registers + * The cacheerr registers are not standardized. On OCTEON, they are + * 64 bits wide. */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) +#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) +#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) -#define rddsp(mask) \ +#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) +#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) + +/* BMIPS3300 */ +#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) +#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) + +#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) +#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) + +#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) +#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) + +/* BMIPS43xx */ +#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) +#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) + +#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) +#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) + +#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) +#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) + +#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) +#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) + +#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) +#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) + +/* BMIPS5000 */ +#define read_c0_brcm_config() __read_32bit_c0_register($22, 0) +#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) + +#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) +#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) + +#define read_c0_brcm_action() __read_32bit_c0_register($22, 2) +#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) + +#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) +#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) + +#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) +#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) + +#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) +#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) + +/* + * Macros to access the floating point coprocessor control registers + */ +#define _read_32bit_cp1_register(source, gas_hardfloat) \ ({ \ unsigned int __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ - : "i" (mask)); \ + " .set push \n" \ + " .set reorder \n" \ + " # gas fails to assemble cfc1 for some archs, \n" \ + " # like Octeon. \n" \ + " .set mips1 \n" \ + " "STR(gas_hardfloat)" \n" \ + " cfc1 %0,"STR(source)" \n" \ + " .set pop \n" \ + : "=r" (__res)); \ __res; \ }) -#define wrdsp(val, mask) \ -do { \ +#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ + " .set reorder \n" \ + " "STR(gas_hardfloat)" \n" \ + " ctc1 %0,"STR(dest)" \n" \ " .set pop \n" \ + : : "r" (val)); \ +}) + +#ifdef GAS_HAS_SET_HARDFLOAT +#define read_32bit_cp1_register(source) \ + _read_32bit_cp1_register(source, .set hardfloat) +#define write_32bit_cp1_register(dest, val) \ + _write_32bit_cp1_register(dest, val, .set hardfloat) +#else +#define read_32bit_cp1_register(source) \ + _read_32bit_cp1_register(source, ) +#define write_32bit_cp1_register(dest, val) \ + _write_32bit_cp1_register(dest, val, ) +#endif + +#ifdef HAVE_AS_DSP +#define rddsp(mask) \ +({ \ + unsigned int __dspctl; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set dsp \n" \ + " rddsp %0, %x1 \n" \ + " .set pop \n" \ + : "=r" (__dspctl) \ + : "i" (mask)); \ + __dspctl; \ +}) + +#define wrdsp(val, mask) \ +({ \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set dsp \n" \ + " wrdsp %0, %x1 \n" \ + " .set pop \n" \ : \ : "r" (val), "i" (mask)); \ -} while (0) +}) + +#define mflo0() \ +({ \ + long mflo0; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac0 \n" \ + " .set pop \n" \ + : "=r" (mflo0)); \ + mflo0; \ +}) + +#define mflo1() \ +({ \ + long mflo1; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac1 \n" \ + " .set pop \n" \ + : "=r" (mflo1)); \ + mflo1; \ +}) + +#define mflo2() \ +({ \ + long mflo2; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac2 \n" \ + " .set pop \n" \ + : "=r" (mflo2)); \ + mflo2; \ +}) + +#define mflo3() \ +({ \ + long mflo3; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac3 \n" \ + " .set pop \n" \ + : "=r" (mflo3)); \ + mflo3; \ +}) #define mfhi0() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac0 \n" \ - " .word 0x00000810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi0; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac0 \n" \ + " .set pop \n" \ + : "=r" (mfhi0)); \ + mfhi0; \ }) #define mfhi1() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac1 \n" \ - " .word 0x00200810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi1; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac1 \n" \ + " .set pop \n" \ + : "=r" (mfhi1)); \ + mfhi1; \ }) #define mfhi2() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac2 \n" \ - " .word 0x00400810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi2; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac2 \n" \ + " .set pop \n" \ + : "=r" (mfhi2)); \ + mfhi2; \ }) #define mfhi3() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac3 \n" \ - " .word 0x00600810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi3; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac3 \n" \ + " .set pop \n" \ + : "=r" (mfhi3)); \ + mfhi3; \ }) -#define mflo0() \ + +#define mtlo0(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac0 \n" \ - " .word 0x00000812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac0 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) -#define mflo1() \ +#define mtlo1(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac1 \n" \ - " .word 0x00200812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac1 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) -#define mflo2() \ +#define mtlo2(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac2 \n" \ - " .word 0x00400812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac2 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) -#define mflo3() \ +#define mtlo3(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac3 \n" \ - " .word 0x00600812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac3 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) #define mthi0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac0 \n" \ - " .word 0x00200011 \n" \ - " .set pop \n" \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac0 \n" \ + " .set pop \n" \ : \ : "r" (x)); \ -} while (0) +}) #define mthi1(x) \ -do { \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac1 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi2(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac2 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi3(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac3 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#else + +#ifdef CONFIG_CPU_MICROMIPS +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac1 \n" \ - " .word 0x00200811 \n" \ + " # rddsp $1, %x1 \n" \ + " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) -#define mthi2(x) \ -do { \ +#define wrdsp(val, mask) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mthi $1, $ac2 \n" \ - " .word 0x00201011 \n" \ + " # wrdsp $1, %x1 \n" \ + " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ -} while (0) + : "r" (val), "i" (mask)); \ +}) -#define mthi3(x) \ -do { \ +#define _umips_dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac3 \n" \ - " .word 0x00201811 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mtlo0(x) \ -do { \ +#define _umips_dsp_mtxxx(val, ins) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac0 \n" \ - " .word 0x00200013 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ " .set pop \n" \ : \ - : "r" (x)); \ -} while (0) + : "r" (val), "i" (ins)); \ +}) -#define mtlo1(x) \ -do { \ +#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) +#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) + +#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) +#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) + +#define mflo0() _umips_dsp_mflo(0) +#define mflo1() _umips_dsp_mflo(1) +#define mflo2() _umips_dsp_mflo(2) +#define mflo3() _umips_dsp_mflo(3) + +#define mfhi0() _umips_dsp_mfhi(0) +#define mfhi1() _umips_dsp_mfhi(1) +#define mfhi2() _umips_dsp_mfhi(2) +#define mfhi3() _umips_dsp_mfhi(3) + +#define mtlo0(x) _umips_dsp_mtlo(x, 0) +#define mtlo1(x) _umips_dsp_mtlo(x, 1) +#define mtlo2(x) _umips_dsp_mtlo(x, 2) +#define mtlo3(x) _umips_dsp_mtlo(x, 3) + +#define mthi0(x) _umips_dsp_mthi(x, 0) +#define mthi1(x) _umips_dsp_mthi(x, 1) +#define mthi2(x) _umips_dsp_mthi(x, 2) +#define mthi3(x) _umips_dsp_mthi(x, 3) + +#else /* !CONFIG_CPU_MICROMIPS */ +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac1 \n" \ - " .word 0x00200813 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ -} while (0) + : "r" (val), "i" (mask)); \ +}) -#define mtlo2(x) \ -do { \ +#define _dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac2 \n" \ - " .word 0x00201013 \n" \ + " .word (0x00000810 | %1) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mtlo3(x) \ -do { \ +#define _dsp_mtxxx(val, ins) \ +({ \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac3 \n" \ - " .word 0x00201813 \n" \ + " .word (0x00200011 | %1) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ -} while (0) + : "r" (val), "i" (ins)); \ +}) + +#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) +#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) + +#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) +#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) + +#define mflo0() _dsp_mflo(0) +#define mflo1() _dsp_mflo(1) +#define mflo2() _dsp_mflo(2) +#define mflo3() _dsp_mflo(3) + +#define mfhi0() _dsp_mfhi(0) +#define mfhi1() _dsp_mfhi(1) +#define mfhi2() _dsp_mfhi(2) +#define mfhi3() _dsp_mfhi(3) + +#define mtlo0(x) _dsp_mtlo(x, 0) +#define mtlo1(x) _dsp_mtlo(x, 1) +#define mtlo2(x) _dsp_mtlo(x, 2) +#define mtlo3(x) _dsp_mtlo(x, 3) + +#define mthi0(x) _dsp_mthi(x, 0) +#define mthi1(x) _dsp_mthi(x, 1) +#define mthi2(x) _dsp_mthi(x, 2) +#define mthi3(x) _dsp_mthi(x, 3) + +#endif /* CONFIG_CPU_MICROMIPS */ +#endif /* * TLB operations. @@ -1324,11 +1933,11 @@ static inline void tlb_write_random(void) static inline unsigned int \ set_c0_##name(unsigned int set) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ + new = res | set; \ + write_c0_##name(new); \ \ return res; \ } \ @@ -1336,24 +1945,24 @@ set_c0_##name(unsigned int set) \ static inline unsigned int \ clear_c0_##name(unsigned int clear) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ + new = res & ~clear; \ + write_c0_##name(new); \ \ return res; \ } \ \ static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ +change_c0_##name(unsigned int change, unsigned int val) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ + new = res & ~change; \ + new |= (val & change); \ + write_c0_##name(new); \ \ return res; \ } @@ -1361,9 +1970,27 @@ change_c0_##name(unsigned int change, unsigned int new) \ __BUILD_SET_C0(status) __BUILD_SET_C0(cause) __BUILD_SET_C0(config) +__BUILD_SET_C0(config5) __BUILD_SET_C0(intcontrol) __BUILD_SET_C0(intctl) __BUILD_SET_C0(srsmap) +__BUILD_SET_C0(pagegrain) +__BUILD_SET_C0(brcm_config_0) +__BUILD_SET_C0(brcm_bus_pll) +__BUILD_SET_C0(brcm_reset) +__BUILD_SET_C0(brcm_cmt_intr) +__BUILD_SET_C0(brcm_cmt_ctrl) +__BUILD_SET_C0(brcm_config) +__BUILD_SET_C0(brcm_mode) + +/* + * Return low 10 bits of ebase. + * Note that under KVM (MIPSVZ) this returns vcpu id. + */ +static inline unsigned int get_ebase_cpunum(void) +{ + return read_c0_ebase() & 0x3ff; +} #endif /* !__ASSEMBLY__ */ diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h new file mode 100644 index 0000000000..9e5fa98d1c --- /dev/null +++ b/arch/mips/include/asm/pgtable-bits.h @@ -0,0 +1,283 @@ +/* + * Copyright (C) 1994 - 2002 by Ralf Baechle + * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. + * Copyright (C) 2002 Maciej W. Rozycki + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef _ASM_PGTABLE_BITS_H +#define _ASM_PGTABLE_BITS_H + + +/* + * Note that we shift the lower 32bits of each EntryLo[01] entry + * 6 bits to the left. That way we can convert the PFN into the + * physical address by a single 'and' operation and gain 6 additional + * bits for storing information which isn't present in a normal + * MIPS page table. + * + * Similar to the Alpha port, we need to keep track of the ref + * and mod bits in software. We have a software "yeah you can read + * from this page" bit, and a hardware one which actually lets the + * process read from the page. On the same token we have a software + * writable bit and the real hardware one which actually lets the + * process write to the page, this keeps a mod bit via the hardware + * dirty bit. + * + * Certain revisions of the R4000 and R5000 have a bug where if a + * certain sequence occurs in the last 3 instructions of an executable + * page, and the following page is not mapped, the cpu can do + * unpredictable things. The code (when it is written) to deal with + * this problem will be in the update_mmu_cache() code for the r4k. + */ +#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) + +/* + * The following bits are implemented by the TLB hardware + */ +#define _PAGE_NO_EXEC_SHIFT 0 +#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT) +#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) +#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT) +#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) +#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) +#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) +#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) +#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) +#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) +#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) +#define _CACHE_MASK (7 << _CACHE_SHIFT) + +/* + * The following bits are implemented in software + */ +#define _PAGE_PRESENT_SHIFT (24) +#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) +#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ (1 << _PAGE_READ_SHIFT) +#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) +#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) +#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) +#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) + +#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) + +/* + * Bits for extended EntryLo0/EntryLo1 registers + */ +#define _PFNX_MASK 0xffffff + +#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + +/* + * The following bits are implemented in software + */ +#define _PAGE_PRESENT_SHIFT (0) +#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) +#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ (1 << _PAGE_READ_SHIFT) +#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) +#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) +#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) +#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) + +/* + * The following bits are implemented by the TLB hardware + */ +#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4) +#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) +#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) +#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) +#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) +#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) +#define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1) +#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) +#define _CACHE_MASK _CACHE_UNCACHED + +#define _PFN_SHIFT PAGE_SHIFT + +#else +/* + * Below are the "Normal" R4K cases + */ + +/* + * The following bits are implemented in software + */ +#define _PAGE_PRESENT_SHIFT 0 +#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) +/* R2 or later cores check for RI/XI support to determine _PAGE_READ */ +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) +#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +#else +#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ (1 << _PAGE_READ_SHIFT) +#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +#endif +#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) +#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) +#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) +#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) + +#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) +/* Huge TLB page */ +#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) +#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) +#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) +#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) +#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */ + +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) +/* XI - page cannot be executed */ +#ifdef _PAGE_SPLITTING_SHIFT +#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1) +#else +#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1) +#endif +#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0) + +/* RI - page cannot be read */ +#define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) +#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT)) +#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT +#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0) +#endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */ + +#if defined(_PAGE_NO_READ_SHIFT) +#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) +#elif defined(_PAGE_SPLITTING_SHIFT) +#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1) +#else +#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1) +#endif +#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) + +#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) +#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) +#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) +#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) +#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) +#define _CACHE_MASK (7 << _CACHE_SHIFT) + +#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) + +#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ + +#ifndef _PAGE_NO_EXEC +#define _PAGE_NO_EXEC 0 +#endif +#ifndef _PAGE_NO_READ +#define _PAGE_NO_READ 0 +#endif + +#define _PAGE_SILENT_READ _PAGE_VALID +#define _PAGE_SILENT_WRITE _PAGE_DIRTY + +#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) + +/* + * The final layouts of the PTE bits are: + * + * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P + * 32-bit, R1 or earler: CCC D V G M A W R P + * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P + * 32-bit, R2 or later: CCC D V G RI/R XI M A W P + */ + + +#ifndef __ASSEMBLY__ +/* + * pte_to_entrylo converts a page table entry (PTE) into a Mips + * entrylo0/1 value. + */ +static inline uint64_t pte_to_entrylo(unsigned long pte_val) +{ +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) + if (cpu_has_rixi) { + int sa; +#ifdef CONFIG_32BIT + sa = 31 - _PAGE_NO_READ_SHIFT; +#else + sa = 63 - _PAGE_NO_READ_SHIFT; +#endif + /* + * C has no way to express that this is a DSRL + * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily + * in the fast path this is done in assembly + */ + return (pte_val >> _PAGE_GLOBAL_SHIFT) | + ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); + } +#endif + + return pte_val >> _PAGE_GLOBAL_SHIFT; +} +#endif + +/* + * Cache attributes + */ +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + +#define _CACHE_CACHABLE_NONCOHERENT 0 +#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED + +#elif defined(CONFIG_CPU_SB1) + +/* No penalty for being coherent on the SB1, so just + use it for "noncoherent" spaces, too. Shouldn't hurt. */ + +#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) + +#elif defined(CONFIG_CPU_LOONGSON3) + +/* Using COHERENT flag for NONCOHERENT doesn't hurt. */ + +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ +#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ + +#elif defined(CONFIG_MACH_INGENIC) + +/* Ingenic uses the WA bit to achieve write-combine memory writes */ +#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) + +#endif + +#ifndef _CACHE_CACHABLE_NO_WA +#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_WA +#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_UNCACHED +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_NONCOHERENT +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_CE +#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_COW +#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_CUW +#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_UNCACHED_ACCELERATED +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) +#endif + +#define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED) +#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) + +#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ + _PFN_MASK | _CACHE_MASK) + +#endif /* _ASM_PGTABLE_BITS_H */ diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 4deac5207a..90c0affdee 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -1,10 +1,7 @@ -/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * +/* * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_POSIX_TYPES_H #define _ASM_POSIX_TYPES_H diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index ba7f5381a3..02a3b167f5 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -1,12 +1,10 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994 Waldorf GMBH * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle * Copyright (C) 1996 Paul M. Antoine * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index 5659c0c873..da051f6e10 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -1,35 +1,27 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_PTRACE_H #define _ASM_PTRACE_H -/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ -#define FPR_BASE 32 -#define PC 64 -#define CAUSE 65 -#define BADVADDR 66 -#define MMHI 67 -#define MMLO 68 -#define FPC_CSR 69 -#define FPC_EIR 70 -#define DSP_BASE 71 /* 3 more hi / lo register pairs */ -#define DSP_CONTROL 77 -#define ACX 78 +#include <linux/compiler.h> +#include <linux/types.h> +#include <asm/isadep.h> /* * This struct defines the way the registers are stored on the stack during a * system call/exception. As usual the registers k0/k1 aren't being saved. + * + * If you add a register here, also add it to regoffset_table[] in + * arch/mips/kernel/ptrace.c. */ struct pt_regs { #ifdef CONFIG_32BIT /* Pad bytes for argument save space on the stack. */ - unsigned long pad0[6]; + unsigned long pad0[8]; #endif /* Saved main processor registers. */ @@ -45,34 +37,50 @@ struct pt_regs { unsigned long cp0_badvaddr; unsigned long cp0_cause; unsigned long cp0_epc; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long cp0_tcstatus; -#endif /* CONFIG_MIPS_MT_SMTC */ -} __attribute__ ((aligned (8))); +#ifdef CONFIG_CPU_CAVIUM_OCTEON + unsigned long long mpl[6]; /* MTM{0-5} */ + unsigned long long mtp[6]; /* MTP{0-5} */ +#endif + unsigned long __last[0]; +} __aligned(8); -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 -/* #define PTRACE_GETFPXREGS 18 */ -/* #define PTRACE_SETFPXREGS 19 */ +static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) +{ + return regs->regs[31]; +} -#define PTRACE_OLDSETOPTIONS 21 +/* + * Don't use asm-generic/ptrace.h it defines FP accessors that don't make + * sense on MIPS. We rather want an error if they get invoked. + */ -#define PTRACE_GET_THREAD_AREA 25 -#define PTRACE_SET_THREAD_AREA 26 +static inline void instruction_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + regs->cp0_epc = val; +} -/* Calls to trace a 64bit program from a 32bit program. */ -#define PTRACE_PEEKTEXT_3264 0xc0 -#define PTRACE_PEEKDATA_3264 0xc1 -#define PTRACE_POKETEXT_3264 0xc2 -#define PTRACE_POKEDATA_3264 0xc3 -#define PTRACE_GET_THREAD_AREA_3264 0xc4 +/* Query offset/name of register from its name/offset */ +extern int regs_query_register_offset(const char *name); +#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last)) -#ifdef __KERNEL__ +/** + * regs_get_register() - get register value from its offset + * @regs: pt_regs from which register value is gotten. + * @offset: offset number of the register. + * + * regs_get_register returns the value of a register. The @offset is the + * offset of the register in struct pt_regs address which specified by @regs. + * If @offset is bigger than MAX_REG_OFFSET, this returns 0. + */ +static inline unsigned long regs_get_register(struct pt_regs *regs, + unsigned int offset) +{ + if (unlikely(offset > MAX_REG_OFFSET)) + return 0; -#include <asm/isadep.h> + return *(unsigned long *)((unsigned long)regs + offset); +} /* * Does the process account for user or for system time? @@ -82,6 +90,17 @@ struct pt_regs { #define instruction_pointer(regs) ((regs)->cp0_epc) #define profile_pc(regs) instruction_pointer(regs) -#endif +/* Helpers for working with the user stack pointer */ + +static inline unsigned long user_stack_pointer(struct pt_regs *regs) +{ + return regs->regs[29]; +} + +static inline void user_stack_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + regs->regs[29] = val; +} #endif /* _ASM_PTRACE_H */ diff --git a/arch/mips/include/asm/reboot.h b/arch/mips/include/asm/reboot.h index 978d206816..2a6b7244e7 100644 --- a/arch/mips/include/asm/reboot.h +++ b/arch/mips/include/asm/reboot.h @@ -1,10 +1,8 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_REBOOT_H #define _ASM_REBOOT_H diff --git a/arch/mips/include/asm/reg.h b/arch/mips/include/asm/reg.h index fc6bc0c169..af6fbb469e 100644 --- a/arch/mips/include/asm/reg.h +++ b/arch/mips/include/asm/reg.h @@ -2,12 +2,10 @@ * Various register offset definitions for debuggers, core file * examiners and whatnot. * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1995, 1999 by Ralf Baechle * Copyright (C) 1995, 1999 Silicon Graphics + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_MIPS_REG_H #define __ASM_MIPS_REG_H diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h index 2e65cc3c43..f1efc45791 100644 --- a/arch/mips/include/asm/regdef.h +++ b/arch/mips/include/asm/regdef.h @@ -1,11 +1,11 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1985 MIPS Computer Systems, Inc. * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. + * Copyright (C) 2011 Wind River Systems, + * written by Ralf Baechle <ralf@linux-mips.org> + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_REGDEF_H #define _ASM_REGDEF_H @@ -30,9 +30,13 @@ #define t2 $10 #define t3 $11 #define t4 $12 +#define ta0 $12 #define t5 $13 +#define ta1 $13 #define t6 $14 +#define ta2 $14 #define t7 $15 +#define ta3 $15 #define s0 $16 /* callee saved */ #define s1 $17 #define s2 $18 diff --git a/arch/mips/include/asm/sgidefs.h b/arch/mips/include/asm/sgidefs.h index 67f2658958..2a0388652a 100644 --- a/arch/mips/include/asm/sgidefs.h +++ b/arch/mips/include/asm/sgidefs.h @@ -1,11 +1,9 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1996, 1999, 2001 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SGIDEFS_H #define __ASM_SGIDEFS_H diff --git a/arch/mips/include/asm/string.h b/arch/mips/include/asm/string.h index 579a591e62..1fbe899aaa 100644 --- a/arch/mips/include/asm/string.h +++ b/arch/mips/include/asm/string.h @@ -1,11 +1,9 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle * Copyright (c) 2000 by Silicon Graphics, Inc. * Copyright (c) 2001 MIPS Technologies, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_STRING_H #define _ASM_STRING_H diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index d56f73b8b8..e6435cce29 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -1,8 +1,4 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994 - 1999 by Ralf Baechle * Copyright (C) 1996 by Paul M. Antoine * Copyright (C) 1994 - 1999 by Ralf Baechle @@ -12,6 +8,8 @@ * * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_SYSTEM_H #define _ASM_SYSTEM_H diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h index aebafdbba1..627440dc24 100644 --- a/arch/mips/include/asm/types.h +++ b/arch/mips/include/asm/types.h @@ -1,10 +1,8 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_TYPES_H #define _ASM_TYPES_H diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h index c25a8462c7..eebe06a9c9 100644 --- a/arch/mips/include/asm/unaligned.h +++ b/arch/mips/include/asm/unaligned.h @@ -1,9 +1,7 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_MIPS_UNALIGNED_H #define _ASM_MIPS_UNALIGNED_H diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index e245614d16..bf8ff598ac 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -27,7 +27,7 @@ static inline unsigned long icache_line_size(void) { unsigned long conf1, il; conf1 = read_c0_config1(); - il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT; + il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF; if (!il) return 0; return 2 << il; @@ -37,7 +37,7 @@ static inline unsigned long dcache_line_size(void) { unsigned long conf1, dl; conf1 = read_c0_config1(); - dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT; + dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; if (!dl) return 0; return 2 << dl; diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 137d7283ff..14cc2c49fd 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -54,24 +54,24 @@ mfc0 $1, CP0_CONFIG, 1 /* detect line size */ - srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT - andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT) + srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF + andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF) move \sz, zero beqz \line_sz, 10f li \sz, 2 sllv \line_sz, \sz, \line_sz /* detect associativity */ - srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT - andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT) + srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF + andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF) addi \sz, \sz, 1 /* sz *= line_sz */ mul \sz, \sz, \line_sz /* detect log32(sets) */ - srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT - andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT) + srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF + andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF) addiu $1, $1, 1 andi $1, $1, 0x7 @@ -103,14 +103,14 @@ LEAF(mips_cache_reset) li t2, CONFIG_SYS_ICACHE_SIZE li t8, CONFIG_SYS_CACHELINE_SIZE #else - l1_info t2, t8, MIPS_CONF1_IA_SHIFT + l1_info t2, t8, MIPS_CONF1_IA_SHF #endif #ifdef CONFIG_SYS_DCACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE li t9, CONFIG_SYS_CACHELINE_SIZE #else - l1_info t3, t9, MIPS_CONF1_DA_SHIFT + l1_info t3, t9, MIPS_CONF1_DA_SHF #endif #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD diff --git a/arch/mips/mach-au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c index d6ebe07643..921686081f 100644 --- a/arch/mips/mach-au1x00/au1x00_eth.c +++ b/arch/mips/mach-au1x00/au1x00_eth.c @@ -43,7 +43,7 @@ #include <net.h> #include <command.h> #include <asm/io.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #if defined(CONFIG_CMD_MII) #include <miiphy.h> @@ -279,7 +279,7 @@ int au1x00_enet_initialize(bd_t *bis){ memset(dev, 0, sizeof *dev); - sprintf(dev->name, "Au1X00 ethernet"); + strcpy(dev->name, "Au1X00 ethernet"); dev->iobase = 0; dev->priv = 0; dev->init = au1x00_init; diff --git a/arch/mips/mach-au1x00/au1x00_serial.c b/arch/mips/mach-au1x00/au1x00_serial.c index 046350826a..47845049bb 100644 --- a/arch/mips/mach-au1x00/au1x00_serial.c +++ b/arch/mips/mach-au1x00/au1x00_serial.c @@ -11,7 +11,7 @@ #include <config.h> #include <common.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #include <serial.h> #include <linux/compiler.h> diff --git a/arch/mips/mach-au1x00/au1x00_usb_ohci.c b/arch/mips/mach-au1x00/au1x00_usb_ohci.c index 74bdb77303..42484e5712 100644 --- a/arch/mips/mach-au1x00/au1x00_usb_ohci.c +++ b/arch/mips/mach-au1x00/au1x00_usb_ohci.c @@ -23,7 +23,7 @@ #include <common.h> #include <malloc.h> #include <asm/io.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #include <usb.h> #include "au1x00_usb_ohci.h" diff --git a/arch/mips/include/asm/au1x00.h b/arch/mips/mach-au1x00/include/mach/au1x00.h index f76c4c3160..f76c4c3160 100644 --- a/arch/mips/include/asm/au1x00.h +++ b/arch/mips/mach-au1x00/include/mach/au1x00.h diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 54787c53ca..204d0cd9d4 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -106,14 +106,18 @@ _reloc: stw r0, 4(sp) mov fp, sp - /* Allocate and zero GD, update SP */ + /* Allocate and initialize reserved area, update SP */ mov r4, sp - movhi r2, %hi(board_init_f_mem@h) - ori r2, r2, %lo(board_init_f_mem@h) + movhi r2, %hi(board_init_f_alloc_reserve@h) + ori r2, r2, %lo(board_init_f_alloc_reserve@h) callr r2 - - /* Update stack- and frame-pointers */ mov sp, r2 + mov r4, sp + movhi r2, %hi(board_init_f_init_reserve@h) + ori r2, r2, %lo(board_init_f_init_reserve@h) + callr r2 + + /* Update frame-pointer */ mov fp, sp /* Call board_init_f -- never returns */ diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c index 5ba8bed20d..fff8f2b8d3 100644 --- a/arch/powerpc/cpu/mpc8260/ether_scc.c +++ b/arch/powerpc/cpu/mpc8260/ether_scc.c @@ -355,7 +355,7 @@ int mpc82xx_scc_enet_initialize(bd_t *bis) dev = (struct eth_device *) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); - sprintf(dev->name, "SCC"); + strcpy(dev->name, "SCC"); dev->init = sec_init; dev->halt = sec_halt; dev->send = sec_send; diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c index 262ae7f711..997aea488f 100644 --- a/arch/powerpc/cpu/mpc83xx/law.c +++ b/arch/powerpc/cpu/mpc83xx/law.c @@ -1,9 +1,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 26a65c586d..dd99155a28 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -1,9 +1,7 @@ /* * Copyright 2008, 2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index 2e196033c2..ea4ab3a042 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -148,7 +148,7 @@ int fec_initialize(bd_t *bis) /* for FEC1 make sure that the name of the interface is the same as the old one for compatibility reasons */ if (i == 0) { - sprintf (dev->name, "FEC"); + strcpy(dev->name, "FEC"); } else { sprintf (dev->name, "FEC%d", ether_fcc_info[i].ether_index + 1); diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 549844032b..3474637fac 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -77,7 +77,7 @@ int scc_initialize(bd_t *bis) dev = (struct eth_device*) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); - sprintf(dev->name, "SCC"); + strcpy(dev->name, "SCC"); dev->iobase = 0; dev->priv = 0; dev->init = scc_init; diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index 15cee3fd4a..c35406d37b 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -981,11 +981,11 @@ static void *video_logo (void) U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info); - sprintf (info, "(C) 2002 DENX Software Engineering"); + strcpy(info, "(C) 2002 DENX Software Engineering"); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, info); - sprintf (info, " Wolfgang DENK, wd@denx.de"); + strcpy(info, " Wolfgang DENK, wd@denx.de"); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, info); diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index c1fe5790a3..728a35130c 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -1,9 +1,7 @@ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 3dd0557aa6..137afce37a 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -762,8 +762,9 @@ _start: bl cpu_init_f /* run low-level CPU init code (from Flash) */ #ifdef CONFIG_SYS_GENERIC_BOARD mr r3, r1 - bl board_init_f_mem + bl board_init_f_alloc_reserve mr r1, r3 + bl board_init_f_init_reserve li r0,0 stwu r0, -4(r1) stwu r0, -4(r1) @@ -1038,8 +1039,9 @@ _start: bl cpu_init_f /* run low-level CPU init code (from Flash) */ #ifdef CONFIG_SYS_GENERIC_BOARD mr r3, r1 - bl board_init_f_mem + bl board_init_f_alloc_reserve mr r1, r3 + bl board_init_f_init_reserve stwu r0, -4(r1) stwu r0, -4(r1) #endif diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h index 11641912a6..9e46e22a1b 100644 --- a/arch/powerpc/include/asm/fsl_dma.h +++ b/arch/powerpc/include/asm/fsl_dma.h @@ -3,23 +3,7 @@ * * Copyright 2006 Freescale Semiconductor, Inc. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_FSL_DMA_H_ diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h index d6537fd633..cbbc834273 100644 --- a/arch/powerpc/include/asm/fsl_i2c.h +++ b/arch/powerpc/include/asm/fsl_i2c.h @@ -8,23 +8,7 @@ * and Jeff Brown. * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_FSL_I2C_H_ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 8e1d22adef..2a759c85b8 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -1,9 +1,7 @@ /* * Copyright 2008-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _FSL_LAW_H_ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index b0082affd3..c8da8b2347 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -3,23 +3,7 @@ * * Copyright 2008 Qstreams Networks, Inc. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_MPC8XXX_SPI_H_ diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c index 528865f5d3..ab64f6e210 100644 --- a/arch/sandbox/cpu/eth-raw-os.c +++ b/arch/sandbox/cpu/eth-raw-os.c @@ -198,7 +198,8 @@ int sandbox_eth_raw_os_send(void *packet, int length, addr.sin_family = AF_INET; addr.sin_port = udph->source; addr.sin_addr.s_addr = iph->saddr; - retval = bind(priv->local_bind_sd, &addr, sizeof(addr)); + retval = bind(priv->local_bind_sd, (struct sockaddr *)&addr, + sizeof(addr)); if (retval < 0) printf("Failed to bind: %d %s\n", errno, strerror(errno)); diff --git a/arch/sh/include/asm/mmc.h b/arch/sh/include/asm/mmc.h index 85a530050e..c096057547 100644 --- a/arch/sh/include/asm/mmc.h +++ b/arch/sh/include/asm/mmc.h @@ -4,9 +4,7 @@ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> * Copyright (C) 2012 Renesas Solutions Corp. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. + * SPDX-License-Identifier: GPL-2.0 * */ #ifndef _SH_MMC_H_ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 7e7cb612d7..f07567c81a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -242,6 +242,15 @@ config FSP_SYS_MALLOC_F_LEN help Additional size of malloc() pool before relocation. +config FSP_USE_UPD + bool + depends on HAVE_FSP + default y + help + Most FSPs use UPD data region for some FSP customization. But there + are still some FSPs that might not even have UPD. For such FSPs, + override this to n in their platform Kconfig files. + config ENABLE_MRC_CACHE bool "Enable MRC cache" depends on !EFI && !SYS_COREBOOT diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index a72d615f21..d49b8d2737 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -121,16 +121,23 @@ const struct pch_azalia_config azalia_config = { }; /** - * Override the FSP's UPD. + * Override the FSP's configuration data. * If the device tree does not specify an integer setting, use the default * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. */ -void update_fsp_upd(struct upd_region *fsp_upd) +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) { + struct upd_region *fsp_upd = &config->fsp_upd; struct memory_down_data *mem; const void *blob = gd->fdt_blob; int node; + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; + fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 56abd8fae3..1768a26a35 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -48,7 +48,6 @@ config DCACHE_RAM_MRC_VAR_SIZE config CPU_SPECIFIC_OPTIONS def_bool y select SMM_TSEG - select HAVE_INTEL_ME select X86_RAMTEST config SMM_TSEG_SIZE diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 4334f5b3e5..7917350bff 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -20,8 +20,11 @@ #include <asm/mtrr.h> #include <asm/processor.h> #include <asm/sipi.h> +#include <asm/fw_cfg.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> +#include <dm/lists.h> +#include <dm/root.h> #include <linux/linkage.h> DECLARE_GLOBAL_DATA_PTR; @@ -104,7 +107,7 @@ static void ap_do_flight_plan(struct udevice *cpu) } } -static int find_cpu_by_apid_id(int apic_id, struct udevice **devp) +static int find_cpu_by_apic_id(int apic_id, struct udevice **devp) { struct udevice *dev; @@ -137,7 +140,7 @@ static void ap_init(unsigned int cpu_index) enable_lapic(); apic_id = lapicid(); - ret = find_cpu_by_apid_id(apic_id, &dev); + ret = find_cpu_by_apic_id(apic_id, &dev); if (ret) { debug("Unknown CPU apic_id %x\n", apic_id); goto done; @@ -210,7 +213,7 @@ static int save_bsp_msrs(char *start, int size) return msr_count; } -static int load_sipi_vector(atomic_t **ap_countp) +static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) { struct sipi_params_16bit *params16; struct sipi_params *params; @@ -239,7 +242,7 @@ static int load_sipi_vector(atomic_t **ap_countp) params->idt_ptr = (uint32_t)x86_get_idt(); params->stack_size = CONFIG_AP_STACK_SIZE; - size = params->stack_size * CONFIG_MAX_CPUS; + size = params->stack_size * num_cpus; stack = memalign(size, 4096); if (!stack) return -ENOMEM; @@ -432,7 +435,7 @@ static int init_bsp(struct udevice **devp) lapic_setup(); apic_id = lapicid(); - ret = find_cpu_by_apid_id(apic_id, devp); + ret = find_cpu_by_apic_id(apic_id, devp); if (ret) { printf("Cannot find boot CPU, APIC ID %d\n", apic_id); return ret; @@ -441,6 +444,69 @@ static int init_bsp(struct udevice **devp) return 0; } +#ifdef CONFIG_QEMU +static int qemu_cpu_fixup(void) +{ + int ret; + int cpu_num; + int cpu_online; + struct udevice *dev, *pdev; + struct cpu_platdata *plat; + char *cpu; + + /* first we need to find '/cpus' */ + for (device_find_first_child(dm_root(), &pdev); + pdev; + device_find_next_child(&pdev)) { + if (!strcmp(pdev->name, "cpus")) + break; + } + if (!pdev) { + printf("unable to find cpus device\n"); + return -ENODEV; + } + + /* calculate cpus that are already bound */ + cpu_num = 0; + for (uclass_find_first_device(UCLASS_CPU, &dev); + dev; + uclass_find_next_device(&dev)) { + cpu_num++; + } + + /* get actual cpu number */ + cpu_online = qemu_fwcfg_online_cpus(); + if (cpu_online < 0) { + printf("unable to get online cpu number: %d\n", cpu_online); + return cpu_online; + } + + /* bind addtional cpus */ + dev = NULL; + for (; cpu_num < cpu_online; cpu_num++) { + /* + * allocate device name here as device_bind_driver() does + * not copy device name, 8 bytes are enough for + * sizeof("cpu@") + 3 digits cpu number + '\0' + */ + cpu = malloc(8); + if (!cpu) { + printf("unable to allocate device name\n"); + return -ENOMEM; + } + sprintf(cpu, "cpu@%d", cpu_num); + ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev); + if (ret) { + printf("binding cpu@%d failed: %d\n", cpu_num, ret); + return ret; + } + plat = dev_get_parent_platdata(dev); + plat->cpu_id = cpu_num; + } + return 0; +} +#endif + int mp_init(struct mp_params *p) { int num_aps; @@ -454,6 +520,12 @@ int mp_init(struct mp_params *p) if (ret) return ret; +#ifdef CONFIG_QEMU + ret = qemu_cpu_fixup(); + if (ret) + return ret; +#endif + ret = init_bsp(&cpu); if (ret) { debug("Cannot init boot CPU: err=%d\n", ret); @@ -483,7 +555,7 @@ int mp_init(struct mp_params *p) mp_info.records = p->flight_plan; /* Load the SIPI vector */ - ret = load_sipi_vector(&ap_count); + ret = load_sipi_vector(&ap_count, num_cpus); if (ap_count == NULL) return -1; diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 3f3958aa8e..176ea54ae4 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -7,5 +7,5 @@ ifndef CONFIG_EFI_STUB obj-y += car.o dram.o endif -obj-y += qemu.o +obj-y += cpu.o fw_cfg.o qemu.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c new file mode 100644 index 0000000000..a1b70c6bde --- /dev/null +++ b/arch/x86/cpu/qemu/cpu.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015, Miao Yan <yanmiaobest@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <errno.h> +#include <asm/cpu.h> +#include <asm/fw_cfg.h> + +DECLARE_GLOBAL_DATA_PTR; + +int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size) +{ + if (size < CPU_MAX_NAME_LEN) + return -ENOSPC; + + cpu_get_name(buf); + + return 0; +} + +static int cpu_qemu_get_count(struct udevice *dev) +{ + return qemu_fwcfg_online_cpus(); +} + +static const struct cpu_ops cpu_qemu_ops = { + .get_desc = cpu_qemu_get_desc, + .get_count = cpu_qemu_get_count, +}; + +static const struct udevice_id cpu_qemu_ids[] = { + { .compatible = "cpu-qemu" }, + { } +}; + +U_BOOT_DRIVER(cpu_qemu_drv) = { + .name = "cpu_qemu", + .id = UCLASS_CPU, + .of_match = cpu_qemu_ids, + .ops = &cpu_qemu_ops, +}; diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c new file mode 100644 index 0000000000..05992145cf --- /dev/null +++ b/arch/x86/cpu/qemu/fw_cfg.c @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2015 Miao Yan <yanmiaoebst@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/fw_cfg.h> + +static bool fwcfg_present; +static bool fwcfg_dma_present; + +/* Read configuration item using fw_cfg PIO interface */ +static void qemu_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + uint32_t i = 0; + uint8_t *data = address; + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + outw(entry, FW_CONTROL_PORT); + while (size--) + data[i++] = inb(FW_DATA_PORT); +} + +/* Read configuration item using fw_cfg DMA interface */ +static void qemu_fwcfg_read_entry_dma(uint16_t entry, + uint32_t size, void *address) +{ + struct fw_cfg_dma_access dma; + + dma.length = cpu_to_be32(size); + dma.address = cpu_to_be64((uintptr_t)address); + dma.control = cpu_to_be32(FW_CFG_DMA_READ); + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16)); + + barrier(); + + debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n", + address, size, be32_to_cpu(dma.control)); + + outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH); + + while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR) + __asm__ __volatile__ ("pause"); +} + +static bool qemu_fwcfg_present(void) +{ + uint32_t qemu; + + qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); + return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE; +} + +static bool qemu_fwcfg_dma_present(void) +{ + uint8_t dma_enabled; + + qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); + if (dma_enabled & FW_CFG_DMA_ENABLED) + return true; + + return false; +} + +static void qemu_fwcfg_read_entry(uint16_t entry, + uint32_t length, void *address) +{ + if (fwcfg_dma_present) + qemu_fwcfg_read_entry_dma(entry, length, address); + else + qemu_fwcfg_read_entry_pio(entry, length, address); +} + +int qemu_fwcfg_online_cpus(void) +{ + uint16_t nb_cpus; + + if (!fwcfg_present) + return -ENODEV; + + qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus); + + return le16_to_cpu(nb_cpus); +} + +/* + * This function prepares kernel for zboot. It loads kernel data + * to 'load_addr', initrd to 'initrd_addr' and kernel command + * line using qemu fw_cfg interface. + */ +static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr) +{ + char *data_addr; + uint32_t setup_size, kernel_size, cmdline_size, initrd_size; + + qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size); + qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size); + + if (setup_size == 0 || kernel_size == 0) { + printf("warning: no kernel available\n"); + return -1; + } + + data_addr = load_addr; + qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA, + le32_to_cpu(setup_size), data_addr); + data_addr += le32_to_cpu(setup_size); + + qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA, + le32_to_cpu(kernel_size), data_addr); + data_addr += le32_to_cpu(kernel_size); + + data_addr = initrd_addr; + qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size); + if (initrd_size == 0) { + printf("warning: no initrd available\n"); + } else { + qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA, + le32_to_cpu(initrd_size), data_addr); + data_addr += le32_to_cpu(initrd_size); + } + + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size); + if (cmdline_size) { + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA, + le32_to_cpu(cmdline_size), data_addr); + /* + * if kernel cmdline only contains '\0', (e.g. no -append + * when invoking qemu), do not update bootargs + */ + if (*data_addr != '\0') { + if (setenv("bootargs", data_addr) < 0) + printf("warning: unable to change bootargs\n"); + } + } + + printf("loading kernel to address %p size %x", load_addr, + le32_to_cpu(kernel_size)); + if (initrd_size) + printf(" initrd %p size %x\n", + initrd_addr, + le32_to_cpu(initrd_size)); + else + printf("\n"); + + return 0; +} + +static int qemu_fwcfg_list_firmware(void) +{ + int i; + uint32_t count; + struct fw_cfg_files *files; + + qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); + if (!count) + return 0; + + count = be32_to_cpu(count); + files = malloc(count * sizeof(struct fw_cfg_file)); + if (!files) + return -ENOMEM; + + files->count = count; + qemu_fwcfg_read_entry(FW_CFG_INVALID, + count * sizeof(struct fw_cfg_file), + files->files); + + for (i = 0; i < files->count; i++) + printf("%-56s\n", files->files[i].name); + free(files); + return 0; +} + +void qemu_fwcfg_init(void) +{ + fwcfg_present = qemu_fwcfg_present(); + if (fwcfg_present) + fwcfg_dma_present = qemu_fwcfg_dma_present(); +} + +static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + if (qemu_fwcfg_list_firmware() < 0) + return CMD_RET_FAILURE; + + return 0; +} + +static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int ret = qemu_fwcfg_online_cpus(); + if (ret < 0) { + printf("QEMU fw_cfg interface not found\n"); + return CMD_RET_FAILURE; + } + + printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus()); + + return 0; +} + +static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + char *env; + void *load_addr; + void *initrd_addr; + + env = getenv("loadaddr"); + load_addr = env ? + (void *)simple_strtoul(env, NULL, 16) : + (void *)CONFIG_LOADADDR; + + env = getenv("ramdiskaddr"); + initrd_addr = env ? + (void *)simple_strtoul(env, NULL, 16) : + (void *)CONFIG_RAMDISK_ADDR; + + if (argc == 2) { + load_addr = (void *)simple_strtoul(argv[0], NULL, 16); + initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16); + } else if (argc == 1) { + load_addr = (void *)simple_strtoul(argv[0], NULL, 16); + } + + return qemu_fwcfg_setup_kernel(load_addr, initrd_addr); +} + +static cmd_tbl_t fwcfg_commands[] = { + U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""), + U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""), + U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""), +}; + +static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret; + cmd_tbl_t *fwcfg_cmd; + + if (!fwcfg_present) { + printf("QEMU fw_cfg interface not found\n"); + return CMD_RET_USAGE; + } + + fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands, + ARRAY_SIZE(fwcfg_commands)); + argc -= 2; + argv += 2; + if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs) + return CMD_RET_USAGE; + + ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv); + + return cmd_process_error(fwcfg_cmd, ret); +} + +U_BOOT_CMD( + qfw, 4, 1, do_qemu_fw, + "QEMU firmware interface", + "<command>\n" + " - list : print firmware(s) currently loaded\n" + " - cpus : print online cpu number\n" + " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n" +) diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 1f93f72dc8..46111c9cf0 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -11,6 +11,7 @@ #include <asm/processor.h> #include <asm/arch/device.h> #include <asm/arch/qemu.h> +#include <asm/fw_cfg.h> static bool i440fx; @@ -57,6 +58,8 @@ static void qemu_chipset_init(void) x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, CONFIG_PCIE_ECAM_BASE | BAR_EN); } + + qemu_fwcfg_init(); } int arch_cpu_init(void) diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 37ce3940b0..72c681dcea 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -252,17 +252,6 @@ int arch_cpu_init(void) */ quark_setup_bars(); - /* - * Initialize PCIe controller - * - * Quark SoC holds the PCIe controller in reset following a power on. - * U-Boot needs to release the PCIe controller from reset. The PCIe - * controller (D23:F0/F1) will not be visible in PCI configuration - * space and any access to its PCI configuration registers will cause - * system hang while it is held in reset. - */ - quark_pcie_early_init(); - /* Initialize USB2 PHY */ quark_usb_early_init(); @@ -277,6 +266,22 @@ int arch_cpu_init(void) return 0; } +int arch_cpu_init_dm(void) +{ + /* + * Initialize PCIe controller + * + * Quark SoC holds the PCIe controller in reset following a power on. + * U-Boot needs to release the PCIe controller from reset. The PCIe + * controller (D23:F0/F1) will not be visible in PCI configuration + * space and any access to its PCI configuration registers will cause + * system hang while it is held in reset. + */ + quark_pcie_early_init(); + + return 0; +} + int print_cpuinfo(void) { post_code(POST_CPU_INFO); diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index 78bc966bbd..f83bb5f221 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -8,13 +8,13 @@ #include <common.h> #include <asm/fsp/fsp_support.h> -void update_fsp_upd(struct upd_region *fsp_upd) +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) { - /* Override any UPD setting if required */ - - /* Uncomment the line below to enable DEBUG message */ - /* fsp_upd->serial_dbgport_type = 1; */ + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; - /* Examples on how to initialize the pointers in UPD region */ - /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */ + /* Override any UPD setting if required */ } diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 5b4ee79d88..485868ff57 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -123,8 +123,9 @@ car_init_ret: #endif /* Set up global data */ mov %esp, %eax - call board_init_f_mem + call board_init_f_alloc_reserve mov %eax, %esp + call board_init_f_init_reserve #ifdef CONFIG_DEBUG_UART call debug_uart_init diff --git a/arch/x86/dts/microcode/m12306a2_00000008.dtsi b/arch/x86/dts/microcode/m12306a2_00000008.dtsi new file mode 100644 index 0000000000..6b35c39f8f --- /dev/null +++ b/arch/x86/dts/microcode/m12306a2_00000008.dtsi @@ -0,0 +1,554 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x8>; +intel,date-code = <0x5182011>; +intel,processor-signature = <0x306a2>; +intel,checksum = <0xa0e51feb>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x08000000 0x11201805 0xa2060300 + 0xeb1fe5a0 0x01000000 0x12000000 0xd01f0000 + 0x00200000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x08000000 + 0x00000000 0x00000000 0x17051120 0xd1070000 + 0x01000000 0xa2060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x5665ff94 0x179da7cf 0x1e819fb2 0xb0c24e8e + 0x5cb7beb5 0x43af9a6c 0xcb0b4ccc 0x195d8712 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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a/arch/x86/dts/microcode/m12306a4_00000007.dtsi b/arch/x86/dts/microcode/m12306a4_00000007.dtsi new file mode 100644 index 0000000000..c39fbd3cdf --- /dev/null +++ b/arch/x86/dts/microcode/m12306a4_00000007.dtsi @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x7>; +intel,date-code = <0x9082011>; +intel,processor-signature = <0x306a4>; +intel,checksum = <0x7e23e5af>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x07000000 0x11200809 0xa4060300 + 0xafe5237e 0x01000000 0x12000000 0xd0230000 + 0x00240000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x07000000 + 0x00000000 0x00000000 0x07091120 0xd1080000 + 0x01000000 0xa4060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x9539a0b3 0xc7bb991d 0x308f0f1a 0xb1ba077d + 0x8bd7260b 0xd710ad0c 0xf82ee64b 0xe6f11ce1 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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b/arch/x86/dts/microcode/m12306a5_00000007.dtsi new file mode 100644 index 0000000000..de5037252b --- /dev/null +++ b/arch/x86/dts/microcode/m12306a5_00000007.dtsi @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x7>; +intel,date-code = <0x9092011>; +intel,processor-signature = <0x306a5>; +intel,checksum = <0x8e38731>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x07000000 0x11200909 0xa5060300 + 0x3187e308 0x01000000 0x12000000 0xd0230000 + 0x00240000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x07000000 + 0x00000000 0x00000000 0x08091120 0x71080000 + 0x01000000 0xa5060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x27649db1 0x904b6445 0x6acff7e8 0xc4ac0631 + 0x6830ec45 0x3aece98d 0x97bf40c8 0x83b8fef0 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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b/arch/x86/dts/microcode/m12306a8_00000010.dtsi new file mode 100644 index 0000000000..0672ff1af0 --- /dev/null +++ b/arch/x86/dts/microcode/m12306a8_00000010.dtsi @@ -0,0 +1,682 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x10>; +intel,date-code = <0x2202012>; +intel,processor-signature = <0x306a8>; +intel,checksum = <0xe44a4ef2>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x10000000 0x12202002 0xa8060300 + 0xf24e4ae4 0x01000000 0x12000000 0xd0270000 + 0x00280000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x10000000 + 0x00000000 0x00000000 0x17021220 0xe1090000 + 0x01000000 0xa8060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x493d401b 0x64106cf1 0x0ffc7f0f 0x9b4b97f6 + 0xb8fab9c2 0x46353316 0x0247d91b 0x3c36c361 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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0xddb42e82 0x9688712a + 0xb430e384 0x6484e439 0x44f68d17 0x195c6382 + 0xddee2db1 0xd9af2e18 0x7fbd30d6 0x2ac223db + 0x0d3bd809 0xec982530 0x1a41d13f 0xef2849a8 + 0x9c233021 0xc074a29c 0xe7b8f28f 0xd0adf47f + 0x23cdf70d 0x6795e85d 0x1168d6ea 0x3c8bb4c7 + 0xad1d00c9 0xf3eeb5d0 0x2f950982 0x9fbbde57 + 0xdc733a93 0xb23e2beb 0x7dbb34af 0xf1323cff + 0xf6c9a9bc 0xf69900a6 0x9447ab0b 0xf03e55fa + 0x2816479b 0x487e507e 0x494087fb 0x0601d1ef + 0x27c86510 0x6a14691a 0xb78886de 0xe89e8c84 + 0xf2cd073c 0x09144b70 0xa82227a5 0x82f88828 + 0x71f7e10a 0x6c2b46b6 0xf813fe7d 0xf76d2602 + 0x044d5543 0x9e1b6a76 0x967ad7b5 0xe803b0a7 + 0x01e03dd9 0x6d5c94d8 0x112357c8 0x8e0bfe12 + 0xcc8c7461 0xfbc1c562 0x9838886c 0xa16c46a7 + 0x020631ad 0x70fb29ff 0x5f5f1795 0x07a762e8 + 0x3467aa2b 0xd396d1d7 0xa12aaf4c 0xd3c13b6b + 0xf158d7dd 0x17b1317a 0xd847a91d 0x7612ab8e + >; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 8a06229479..9086b461b9 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -32,17 +32,10 @@ cpu@0 { device_type = "cpu"; - compatible = "cpu-x86"; + compatible = "cpu-qemu"; reg = <0>; intel,apic-id = <0>; }; - - cpu@1 { - device_type = "cpu"; - compatible = "cpu-x86"; - reg = <1>; - intel,apic-id = <1>; - }; }; tsc-timer { diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 0b685c8b79..145e8115ce 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -43,17 +43,10 @@ cpu@0 { device_type = "cpu"; - compatible = "cpu-x86"; + compatible = "cpu-qemu"; reg = <0>; intel,apic-id = <0>; }; - - cpu@1 { - device_type = "cpu"; - compatible = "cpu-x86"; - reg = <1>; - intel,apic-id = <1>; - }; }; tsc-timer { diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h new file mode 100644 index 0000000000..e539890c33 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +struct fsp_config_data { + struct fsp_cfg_common common; + struct upd_region fsp_upd; +}; + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-coreboot/timestamp.h b/arch/x86/include/asm/arch-coreboot/timestamp.h index fcfc1d5442..0cd7a99e2a 100644 --- a/arch/x86/include/asm/arch-coreboot/timestamp.h +++ b/arch/x86/include/asm/arch-coreboot/timestamp.h @@ -3,18 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __COREBOOT_TIMESTAMP_H__ diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 21df083842..31437c8618 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -105,6 +105,8 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define GPIO_ROUT 0xb8 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */ +#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */ #define LPC_EN 0x82 /* LPC IF Enables Register */ #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ @@ -121,6 +123,14 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) +#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */ +#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */ +#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */ +#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */ +#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */ +#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */ +#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */ +#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */ /* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h new file mode 100644 index 0000000000..e539890c33 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +struct fsp_config_data { + struct fsp_cfg_common common; + struct upd_region fsp_upd; +}; + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h index 2d34d138ab..afafb30c14 100644 --- a/arch/x86/include/asm/fsp/fsp_api.h +++ b/arch/x86/include/asm/fsp/fsp_api.h @@ -11,6 +11,16 @@ #include <linux/linkage.h> /* + * FSP common configuration structure. + * This needs to be included in the platform-specific struct fsp_config_data. + */ +struct fsp_cfg_common { + struct fsp_header *fsp_hdr; + u32 stack_top; + u32 boot_mode; +}; + +/* * FspInit continuation function prototype. * Control will be returned to this callback function after FspInit API call. */ @@ -30,7 +40,7 @@ struct common_buf { * Stack top pointer used by the bootloader. The new stack frame will be * set up at this location after FspInit API call. */ - u32 *stack_top; + u32 stack_top; u32 boot_mode; /* Current system boot mode */ void *upd_data; /* User platform configuraiton data region */ u32 reserved[7]; /* Reserved */ diff --git a/arch/x86/include/asm/fsp/fsp_platform.h b/arch/x86/include/asm/fsp/fsp_platform.h deleted file mode 100644 index 61286ceb46..0000000000 --- a/arch/x86/include/asm/fsp/fsp_platform.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: Intel - */ - -#ifndef __FSP_PLATFORM_H__ -#define __FSP_PLATFORM_H__ - -struct fspinit_rtbuf { - struct common_buf common; /* FSP common runtime data structure */ -}; - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 7317dda902..61d811f70e 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -13,16 +13,10 @@ #include "fsp_ffs.h" #include "fsp_api.h" #include "fsp_hob.h" -#include "fsp_platform.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" #include <asm/arch/fsp/fsp_vpd.h> - -struct shared_data { - struct fsp_header *fsp_hdr; - u32 *stack_top; - struct upd_region fsp_upd; -}; +#include <asm/arch/fsp/fsp_configs.h> #define FSP_LOWMEM_BASE 0x100000UL #define FSP_HIGHMEM_BASE 0x100000000ULL @@ -49,14 +43,12 @@ void fsp_init_done(void *hob_list); /** * FSP Continuation function * - * @shared_data: Shared data base before stack migration * @status: Always 0 * @hob_list: HOB list pointer * * @retval: Never returns */ -void fsp_continue(struct shared_data *shared_data, u32 status, - void *hob_list); +void fsp_continue(u32 status, void *hob_list); /** * Find FSP header offset in FSP image @@ -199,13 +191,15 @@ void *fsp_get_nvs_data(const void *hob_list, u32 *len); void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len); /** - * This function overrides the default configurations in the UPD data region. + * This function overrides the default configurations of FSP. * - * @fsp_upd: A pointer to the upd_region data strcture + * @config: A pointer to the FSP configuration data structure + * @rt_buf: A pointer to the FSP runtime buffer data structure * * @return: None */ -void update_fsp_upd(struct upd_region *fsp_upd); +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf); /** * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h new file mode 100644 index 0000000000..fb110fa8e7 --- /dev/null +++ b/arch/x86/include/asm/fw_cfg.h @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FW_CFG__ +#define __FW_CFG__ + +#define FW_CONTROL_PORT 0x510 +#define FW_DATA_PORT 0x511 +#define FW_DMA_PORT_LOW 0x514 +#define FW_DMA_PORT_HIGH 0x518 + +enum qemu_fwcfg_items { + FW_CFG_SIGNATURE = 0x00, + FW_CFG_ID = 0x01, + FW_CFG_UUID = 0x02, + FW_CFG_RAM_SIZE = 0x03, + FW_CFG_NOGRAPHIC = 0x04, + FW_CFG_NB_CPUS = 0x05, + FW_CFG_MACHINE_ID = 0x06, + FW_CFG_KERNEL_ADDR = 0x07, + FW_CFG_KERNEL_SIZE = 0x08, + FW_CFG_KERNEL_CMDLINE = 0x09, + FW_CFG_INITRD_ADDR = 0x0a, + FW_CFG_INITRD_SIZE = 0x0b, + FW_CFG_BOOT_DEVICE = 0x0c, + FW_CFG_NUMA = 0x0d, + FW_CFG_BOOT_MENU = 0x0e, + FW_CFG_MAX_CPUS = 0x0f, + FW_CFG_KERNEL_ENTRY = 0x10, + FW_CFG_KERNEL_DATA = 0x11, + FW_CFG_INITRD_DATA = 0x12, + FW_CFG_CMDLINE_ADDR = 0x13, + FW_CFG_CMDLINE_SIZE = 0x14, + FW_CFG_CMDLINE_DATA = 0x15, + FW_CFG_SETUP_ADDR = 0x16, + FW_CFG_SETUP_SIZE = 0x17, + FW_CFG_SETUP_DATA = 0x18, + FW_CFG_FILE_DIR = 0x19, + FW_CFG_FILE_FIRST = 0x20, + FW_CFG_WRITE_CHANNEL = 0x4000, + FW_CFG_ARCH_LOCAL = 0x8000, + FW_CFG_INVALID = 0xffff, +}; + +#define FW_CFG_FILE_SLOTS 0x10 +#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) +#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) + +#define FW_CFG_MAX_FILE_PATH 56 + +#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') + +#define FW_CFG_DMA_ERROR (1 << 0) +#define FW_CFG_DMA_READ (1 << 1) +#define FW_CFG_DMA_SKIP (1 << 2) +#define FW_CFG_DMA_SELECT (1 << 3) + +#define FW_CFG_DMA_ENABLED (1 << 1) + +struct fw_cfg_file { + __be32 size; + __be16 select; + __be16 reserved; + char name[FW_CFG_MAX_FILE_PATH]; +}; + +struct fw_cfg_files { + __be32 count; + struct fw_cfg_file files[]; +}; + +struct fw_cfg_dma_access { + __be32 control; + __be32 length; + __be64 address; +}; + +/** + * Initialize QEMU fw_cfg interface + */ +void qemu_fwcfg_init(void); + +/** + * Get system cpu number + * + * @return: cpu number in system + */ +int qemu_fwcfg_online_cpus(void); + +#endif diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c index 4959edf11b..25546638cf 100644 --- a/arch/x86/lib/fsp/cmd_fsp.c +++ b/arch/x86/lib/fsp/cmd_fsp.c @@ -69,7 +69,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("---|----------|-----------|------|-"); printf("------------------------------------------\n"); while (!end_of_hob(hdr)) { - printf("%-2d | %08x | ", i, (unsigned int)hdr); + printf("%02x | %08x | ", i, (unsigned int)hdr); type = hdr->type; if (type == HOB_TYPE_UNUSED) desc = "*Unused*"; @@ -79,7 +79,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) desc = hob_type[type]; else desc = "*Invalid*"; - printf("%-9s | %-4d | ", desc, hdr->len); + printf("%-9s | %04x | ", desc, hdr->len); if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC || type == HOB_TYPE_GUID_EXT) { diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 5276ce6ab1..8479af1d7e 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -90,8 +90,8 @@ int x86_fsp_init(void) /* * The second time we enter here, adjust the size of malloc() * pool before relocation. Given gd->malloc_base was adjusted - * after the call to board_init_f_mem() in arch/x86/cpu/start.S, - * we should fix up gd->malloc_limit here. + * after the call to board_init_f_init_reserve() in arch/x86/ + * cpu/start.S, we should fix up gd->malloc_limit here. */ gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN; } diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 1d48ff4a8e..875c96a8f1 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -87,42 +87,28 @@ struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void) return (struct fsp_header *)fsp; } -void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list) +void fsp_continue(u32 status, void *hob_list) { - u32 stack_len; - u32 stack_base; - u32 stack_top; - post_code(POST_MRC); assert(status == 0); - /* Get the migrated stack in normal memory */ - stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len); - assert(stack_base != 0); - stack_top = stack_base + stack_len - sizeof(u32); - - /* - * Old stack base is stored at the very end of the stack top, - * use it to calculate the migrated shared data base - */ - shared_data = (struct shared_data *)(stack_base + - ((u32)shared_data - *(u32 *)stack_top)); - /* The boot loader main function entry */ fsp_init_done(hob_list); } void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) { - struct shared_data shared_data; + struct fsp_config_data config_data; fsp_init_f init; struct fsp_init_params params; struct fspinit_rtbuf rt_buf; - struct vpd_region *fsp_vpd; struct fsp_header *fsp_hdr; struct fsp_init_params *params_ptr; +#ifdef CONFIG_FSP_USE_UPD + struct vpd_region *fsp_vpd; struct upd_region *fsp_upd; +#endif #ifdef CONFIG_DEBUG_UART setup_early_uart(); @@ -134,14 +120,11 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) panic("Invalid FSP header"); } - fsp_upd = &shared_data.fsp_upd; - memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); - - /* Reserve a gap in stack top */ - rt_buf.common.stack_top = (u32 *)stack_top - 32; - rt_buf.common.boot_mode = boot_mode; - rt_buf.common.upd_data = fsp_upd; + config_data.common.fsp_hdr = fsp_hdr; + config_data.common.stack_top = stack_top; + config_data.common.boot_mode = boot_mode; +#ifdef CONFIG_FSP_USE_UPD /* Get VPD region start */ fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base + fsp_hdr->cfg_region_off); @@ -149,15 +132,20 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) /* Verify the VPD data region is valid */ assert(fsp_vpd->sign == VPD_IMAGE_ID); + fsp_upd = &config_data.fsp_upd; + /* Copy default data from Flash */ memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset), sizeof(struct upd_region)); /* Verify the UPD data region is valid */ assert(fsp_upd->terminator == UPD_TERMINATOR); +#endif - /* Override any UPD setting if required */ - update_fsp_upd(fsp_upd); + memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); + + /* Override any configuration if required */ + update_fsp_configs(&config_data, &rt_buf); memset(¶ms, 0, sizeof(struct fsp_init_params)); params.nvs_buf = nvs_buf; @@ -167,28 +155,24 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init); params_ptr = ¶ms; - shared_data.fsp_hdr = fsp_hdr; - shared_data.stack_top = (u32 *)stack_top; - post_code(POST_PRE_MRC); /* Load GDT for FSP */ setup_fsp_gdt(); /* - * Use ASM code to ensure the register value in EAX & ECX - * will be passed into BlContinuationFunc + * Use ASM code to ensure the register value in EAX & EDX + * will be passed into fsp_continue */ asm volatile ( "pushl %0;" "call *%%eax;" ".global asm_continuation;" "asm_continuation:;" - "movl %%ebx, %%eax;" /* shared_data */ - "movl 4(%%esp), %%edx;" /* status */ - "movl 8(%%esp), %%ecx;" /* hob_list */ + "movl 4(%%esp), %%eax;" /* status */ + "movl 8(%%esp), %%edx;" /* hob_list */ "jmp fsp_continue;" - : : "m"(params_ptr), "a"(init), "b"(&shared_data) + : : "m"(params_ptr), "a"(init) ); /* diff --git a/arch/x86/lib/gcc.c b/arch/x86/lib/gcc.c index 497ad75b7a..3c70d790d4 100644 --- a/arch/x86/lib/gcc.c +++ b/arch/x86/lib/gcc.c @@ -3,18 +3,7 @@ * * Copyright (C) 2009 coresystems GmbH * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 or later of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0 */ #ifdef __GNUC__ |