summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/mx6/ddr.c22
-rw-r--r--arch/arm/mach-socfpga/clock_manager.c4
-rw-r--r--arch/arm/mach-socfpga/clock_manager_gen5.c6
-rw-r--r--arch/arm/mach-socfpga/reset_manager_arria10.c36
-rw-r--r--arch/mips/mach-ath79/ar934x/clk.c2
5 files changed, 34 insertions, 36 deletions
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 52a9a25904..f07f938c65 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -21,10 +21,10 @@ static void reset_read_data_fifos(void)
/* Reset data FIFOs twice. */
setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
}
static void precharge_all(const bool cs0_enable, const bool cs1_enable)
@@ -39,12 +39,12 @@ static void precharge_all(const bool cs0_enable, const bool cs1_enable)
*/
if (cs0_enable) { /* CS0 */
writel(0x04008050, &mmdc0->mdscr);
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+ wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
}
if (cs1_enable) { /* CS1 */
writel(0x04008058, &mmdc0->mdscr);
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+ wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
}
}
@@ -146,7 +146,7 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
* 7. Upon completion of this process the MMDC de-asserts
* the MPWLGCR[HW_WL_EN]
*/
- wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
/*
* 8. check for any errors: check both PHYs for x64 configuration,
@@ -278,7 +278,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
writel(0x00008028, &mmdc0->mdscr);
/* poll to make sure the con_ack bit was asserted */
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+ wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
/*
* Check MDMISC register CALIB_PER_CS to see which CS calibration
@@ -312,7 +312,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
* this bit until it clears to indicate completion of the write access.
*/
setbits_le32(&mmdc0->mpswdar0, 1);
- wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
/* Set the RD_DL_ABS# bits to their default values
* (will be calibrated later in the read delay-line calibration).
@@ -359,7 +359,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
/* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
- wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
/*
* Check to see if any errors were encountered during calibration
@@ -423,7 +423,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
* setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
* no error bits were set.
*/
- wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
/* check both PHYs for x64 configuration, if x32, check only PHY0 */
if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
@@ -477,7 +477,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
* by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
* Also, ensure that no error bits were set.
*/
- wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
/* Check both PHYs for x64 configuration, if x32, check only PHY0 */
if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
@@ -526,7 +526,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
writel(0x0, &mmdc0->mdscr); /* CS0 */
/* Poll to make sure the con_ack bit is clear */
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
/*
* Print out the registers that were updated as a result
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index cb6ae03696..c740c9f648 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -37,8 +37,8 @@ void cm_wait_for_lock(u32 mask)
/* function to poll in the fsm busy bit */
int cm_wait_for_fsm(void)
{
- return wait_for_bit(__func__, (const u32 *)&clock_manager_base->stat,
- CLKMGR_STAT_BUSY, false, 20000, false);
+ return wait_for_bit_le32(&clock_manager_base->stat,
+ CLKMGR_STAT_BUSY, false, 20000, false);
}
int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
index 31fd51097a..a23f3fc5d0 100644
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -37,15 +37,13 @@ static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
int ret;
/* poll until phase is zero */
- ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,
- false, 20000, false);
+ ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
if (ret)
return ret;
writel(value, reg_address);
- return wait_for_bit(__func__, (const u32 *)reg_address, mask,
- false, 20000, false);
+ return wait_for_bit_le32(reg_address, mask, false, 20000, false);
}
/*
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index ae16897494..54f0ddb255 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -222,8 +222,8 @@ int socfpga_reset_deassert_bridges_handoff(void)
clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
/* Poll until all idleack to 0, timeout at 1000ms */
- return wait_for_bit(__func__, &sysmgr_regs->noc_idleack, mask_noc,
- false, 1000, false);
+ return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
+ false, 1000, false);
}
void socfpga_reset_assert_fpga_connected_peripherals(void)
@@ -343,26 +343,26 @@ int socfpga_bridges_reset(void)
writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
/* Poll until all idleack to 1 */
- ret = wait_for_bit(__func__, &sysmgr_regs->noc_idleack,
- ALT_SYSMGR_NOC_H2F_SET_MSK |
- ALT_SYSMGR_NOC_LWH2F_SET_MSK |
- ALT_SYSMGR_NOC_F2H_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
- true, 10000, false);
+ ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
+ ALT_SYSMGR_NOC_H2F_SET_MSK |
+ ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+ ALT_SYSMGR_NOC_F2H_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+ true, 10000, false);
if (ret)
return ret;
/* Poll until all idlestatus to 1 */
- ret = wait_for_bit(__func__, &sysmgr_regs->noc_idlestatus,
- ALT_SYSMGR_NOC_H2F_SET_MSK |
- ALT_SYSMGR_NOC_LWH2F_SET_MSK |
- ALT_SYSMGR_NOC_F2H_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
- true, 10000, false);
+ ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
+ ALT_SYSMGR_NOC_H2F_SET_MSK |
+ ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+ ALT_SYSMGR_NOC_F2H_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+ true, 10000, false);
if (ret)
return ret;
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index 9b41d3de60..ba2243c9be 100644
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -90,7 +90,7 @@ static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
setbits_be32(pll_reg_base + 0x8, BIT(30));
udelay(5);
- wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);
+ wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);
clrbits_be32(pll_reg_base + 0x8, BIT(30));
udelay(5);
generated by cgit (git 2.34.1) at 2024-12-27 10:28:41 +0000