diff options
Diffstat (limited to 'arch')
61 files changed, 482 insertions, 552 deletions
diff --git a/arch/arm/dts/da850-evm-u-boot.dtsi b/arch/arm/dts/da850-evm-u-boot.dtsi index d9afc5edf4..d588628641 100644 --- a/arch/arm/dts/da850-evm-u-boot.dtsi +++ b/arch/arm/dts/da850-evm-u-boot.dtsi @@ -39,3 +39,7 @@ &spi1 { u-boot,dm-spl; }; + +&gpio { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi index b372d06ca9..d50775c173 100644 --- a/arch/arm/dts/da850-lcdk-u-boot.dtsi +++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi @@ -28,3 +28,7 @@ &serial2 { u-boot,dm-spl; }; + +&gpio { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 6d31735362..51b6e018bd 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -43,3 +43,7 @@ &noc { u-boot,dm-pre-reloc; }; + +&gpio7 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi index eccc069368..251fbdee71 100644 --- a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi @@ -3,7 +3,7 @@ * Copyright 2015 Google, Inc */ -#include "rk3288-u-boot.dtsi" +#include "rk3288-veyron-u-boot.dtsi" &dmc { rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi new file mode 100644 index 0000000000..899fe6e7a0 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2015 Google, Inc + */ + +#include "rk3288-u-boot.dtsi" + +&gpio7 { + u-boot,dm-pre-reloc; +}; + diff --git a/arch/arm/dts/uniphier-ld11-global.dts b/arch/arm/dts/uniphier-ld11-global.dts index 7968d52435..670e1a76db 100644 --- a/arch/arm/dts/uniphier-ld11-global.dts +++ b/arch/arm/dts/uniphier-ld11-global.dts @@ -30,6 +30,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/dts/uniphier-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts index b8f6273484..693171f82f 100644 --- a/arch/arm/dts/uniphier-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ld11-ref.dts @@ -29,6 +29,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index e0737ac7f0..104d56d625 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -129,6 +129,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -140,11 +142,13 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; + clocks = <&peri_clk 12>; + resets = <&peri_rst 12>; }; serial0: serial@54006800 { @@ -566,6 +570,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-ld11-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/dts/uniphier-ld20-global.dts b/arch/arm/dts/uniphier-ld20-global.dts index 9ca692ed1b..2c00008266 100644 --- a/arch/arm/dts/uniphier-ld20-global.dts +++ b/arch/arm/dts/uniphier-ld20-global.dts @@ -30,6 +30,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts index 406244a5c8..eeb976e789 100644 --- a/arch/arm/dts/uniphier-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -29,6 +29,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 59e4191dfc..a5cd026838 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -234,6 +234,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -245,33 +247,39 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; + clocks = <&peri_clk 12>; + resets = <&peri_rst 12>; }; spi2: spi@54006200 { compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006200 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 229 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; + clocks = <&peri_clk 13>; + resets = <&peri_rst 13>; }; spi3: spi@54006300 { compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006300 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 230 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi3>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; + clocks = <&peri_clk 14>; + resets = <&peri_rst 14>; }; serial0: serial@54006800 { @@ -664,6 +672,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-ld20-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index 1eebc7fa3b..897162d5f5 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -67,6 +67,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; diff --git a/arch/arm/dts/uniphier-ld6b-ref.dts b/arch/arm/dts/uniphier-ld6b-ref.dts index 3d9080ee7a..f1a3b29bac 100644 --- a/arch/arm/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ld6b-ref.dts @@ -29,6 +29,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts index 92cc48dd86..64246fad32 100644 --- a/arch/arm/dts/uniphier-pro4-ace.dts +++ b/arch/arm/dts/uniphier-pro4-ace.dts @@ -26,6 +26,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts index 06065eb36c..4967db58c5 100644 --- a/arch/arm/dts/uniphier-pro4-ref.dts +++ b/arch/arm/dts/uniphier-pro4-ref.dts @@ -30,6 +30,7 @@ i2c5 = &i2c5; i2c6 = &i2c6; usb0 = &usb0; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index d006b45f7a..9dae4e9b23 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -75,6 +75,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -426,6 +428,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pro4-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index ba7e224b38..8fc8433a3c 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -160,6 +160,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -171,11 +173,13 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; + clocks = <&peri_clk 11>; /* common with spi0 */ + resets = <&peri_rst 12>; }; serial0: serial@54006800 { @@ -408,6 +412,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pro5-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts index e27fd4f2a5..8e9ac579aa 100644 --- a/arch/arm/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/dts/uniphier-pxs2-gentil.dts @@ -26,6 +26,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/dts/uniphier-pxs2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts index 23fe42b740..8eacc7bdec 100644 --- a/arch/arm/dts/uniphier-pxs2-vodka.dts +++ b/arch/arm/dts/uniphier-pxs2-vodka.dts @@ -24,6 +24,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 8d968d3681..899ff379c9 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -173,6 +173,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -184,11 +186,13 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; + clocks = <&peri_clk 12>; + resets = <&peri_rst 12>; }; serial0: serial@54006800 { @@ -508,6 +512,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pxs2-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts index 1965e4dfe4..1dacbf4fb0 100644 --- a/arch/arm/dts/uniphier-pxs3-ref.dts +++ b/arch/arm/dts/uniphier-pxs3-ref.dts @@ -27,6 +27,10 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c6 = &i2c6; + spi0 = &spi0; + spi1 = &spi1; + ethernet0 = ð0; + ethernet1 = ð1; }; memory@80000000 { @@ -39,6 +43,14 @@ interrupts = <4 8>; }; +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + &serial0 { status = "okay"; }; @@ -116,3 +128,19 @@ &nand { status = "okay"; }; + +&pinctrl_ether_rgmii { + tx { + pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1", + "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL"; + drive-strength = <9>; + }; +}; + +&pinctrl_ether1_rgmii { + tx { + pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1", + "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL"; + drive-strength = <9>; + }; +}; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index ed079c1711..bf3b1eae87 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "socionext,uniphier-pxs3"; @@ -42,6 +43,7 @@ clocks = <&sys_clk 33>; enable-method = "psci"; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -51,6 +53,7 @@ clocks = <&sys_clk 33>; enable-method = "psci"; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -60,6 +63,7 @@ clocks = <&sys_clk 33>; enable-method = "psci"; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -69,6 +73,7 @@ clocks = <&sys_clk 33>; enable-method = "psci"; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; }; @@ -136,6 +141,37 @@ <1 10 4>; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu-crit { + temperature = <110000>; /* 110C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu-alert { + temperature = <100000>; /* 100C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -157,6 +193,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -168,11 +206,13 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; + clocks = <&peri_clk 12>; + resets = <&peri_rst 12>; }; serial0: serial@54006800 { @@ -462,6 +502,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pxs3-aidet"; reg = <0x5fc20000 0x200>; @@ -496,6 +544,13 @@ watchdog { compatible = "socionext,uniphier-wdt"; }; + + pvtctl: pvtctl { + compatible = "socionext,uniphier-pxs3-thermal"; + interrupts = <0 3 4>; + #thermal-sensor-cells = <0>; + socionext,tmod-calibration = <0x0f22 0x68ee>; + }; }; eth0: ethernet@65000000 { diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index 393157eb14..93ddebbae4 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -67,6 +67,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h new file mode 100644 index 0000000000..9ac16f599e --- /dev/null +++ b/arch/arm/include/asm/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARM_MMU_H +#define __ASM_ARM_MMU_H + +void init_addr_map(void); + +#endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index b8c1b4ea74..37c1bfd726 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -207,7 +207,7 @@ int __asm_invalidate_l3_icache(void); void __asm_switch_ttbr(u64 new_ttbr); /* - * Switch from EL3 to EL2 for ARMv8 + * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8 * * @args: For loading 64-bit OS, fdt address. * For loading 32-bit OS, zero. @@ -222,7 +222,7 @@ void __asm_switch_ttbr(u64 new_ttbr); void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, u64 arg4, u64 entry_point, u64 es_flag); /* - * Switch from EL2 to EL1 for ARMv8 + * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8 * * @args: For loading 64-bit OS, fdt address. * For loading 32-bit OS, zero. @@ -248,11 +248,12 @@ void flush_l3_cache(void); void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); /* - *Issue a secure monitor call in accordance with ARM "SMC Calling convention", + * smc_call() - issue a secure monitor call + * + * Issue a secure monitor call in accordance with ARM "SMC Calling convention", * DEN0028A * * @args: input and output arguments - * */ void smc_call(struct pt_regs *args); @@ -521,10 +522,12 @@ enum { #endif /** + * mmu_page_table_flush() - register an update to page tables + * * Register an update to the page tables, and flush the TLB * - * \param start start address of update in page table - * \param stop stop address of update in page table + * @start: start address of update in page table + * @stop: stop address of update in page table */ void mmu_page_table_flush(unsigned long start, unsigned long stop); @@ -585,11 +588,26 @@ s32 psci_features(u32 function_id, u32 psci_fid); void save_boot_params_ret(void); /** + * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping + * + * Change the virt/phys mapping and cache settings for a region. + * + * @virt: virtual start address of memory region to change + * @phys: physical address for the memory region to set + * @size: size of memory region to change + * @option: dcache option to select + */ +void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys, + size_t size, enum dcache_option option); + +/** + * mmu_set_region_dcache_behaviour() - set cache settings + * * Change the cache settings for a region. * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select + * @start: start address of memory region to change + * @size: size of memory region to change + * @option: dcache option to select */ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 1da2e92fe2..39717610d4 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -25,7 +25,8 @@ __weak void arm_init_domains(void) { } -void set_section_dcache(int section, enum dcache_option option) +static void set_section_phys(int section, phys_addr_t phys, + enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -37,7 +38,7 @@ void set_section_dcache(int section, enum dcache_option option) #endif /* Add the page offset */ - value |= ((u32)section << MMU_SECTION_SHIFT); + value |= phys; /* Add caching bits */ value |= option; @@ -46,13 +47,18 @@ void set_section_dcache(int section, enum dcache_option option) page_table[section] = value; } +void set_section_dcache(int section, enum dcache_option option) +{ + set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option); +} + __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) { debug("%s: Warning: not implemented\n", __func__); } -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option) +void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, + size_t size, enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -74,8 +80,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size, option); #endif - for (upto = start; upto < end; upto++) - set_section_dcache(upto, option); + for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE) + set_section_phys(upto, phys, option); /* * Make sure range is cache line aligned @@ -90,6 +96,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, mmu_page_table_flush(startpt, stoppt); } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + mmu_set_region_dcache_behaviour_phys(start, start, size, option); +} + __weak void dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index c033ed6d16..8122d2f98e 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -220,7 +220,7 @@ static const struct at91_port_platdata at91sam9260_plat[] = { }; U_BOOT_DEVICES(at91sam9260_gpios) = { - { "gpio_at91", &at91sam9260_plat[0] }, - { "gpio_at91", &at91sam9260_plat[1] }, - { "gpio_at91", &at91sam9260_plat[2] }, + { "atmel_at91rm9200_gpio", &at91sam9260_plat[0] }, + { "atmel_at91rm9200_gpio", &at91sam9260_plat[1] }, + { "atmel_at91rm9200_gpio", &at91sam9260_plat[2] }, }; diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c index 89cbeafa20..08ca3edd78 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c @@ -176,9 +176,9 @@ static const struct at91_port_platdata at91sam9260_plat[] = { }; U_BOOT_DEVICES(at91sam9260_gpios) = { - { "gpio_at91", &at91sam9260_plat[0] }, - { "gpio_at91", &at91sam9260_plat[1] }, - { "gpio_at91", &at91sam9260_plat[2] }, - { "gpio_at91", &at91sam9260_plat[3] }, - { "gpio_at91", &at91sam9260_plat[4] }, + { "atmel_at91rm9200_gpio", &at91sam9260_plat[0] }, + { "atmel_at91rm9200_gpio", &at91sam9260_plat[1] }, + { "atmel_at91rm9200_gpio", &at91sam9260_plat[2] }, + { "atmel_at91rm9200_gpio", &at91sam9260_plat[3] }, + { "atmel_at91rm9200_gpio", &at91sam9260_plat[4] }, }; diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index e6eb904e7f..b3287ce8bc 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae39852f..4ccaf69693 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -8,4 +8,12 @@ extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +#ifdef CONFIG_TARGET_RPI_4_32B +#include <addr_map.h> +#define phys_to_virt addrmap_phys_to_virt +#define virt_to_phys addrmap_virt_to_phys +#endif +#endif + #endif diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 60e226ce1d..2ae2d3d97c 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette { } body; }; +#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 + +struct bcm2835_mbox_tag_pci_dev_addr { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 dev_addr; + } req; + struct { + } resp; + } body; +}; + /* * Pass a raw u32 message to the VC, and receive a raw u32 back. * diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h index 4afb08631b..e45c1bf010 100644 --- a/arch/arm/mach-bcm283x/include/mach/msg.h +++ b/arch/arm/mach-bcm283x/include/mach/msg.h @@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, int pixel_order, int alpha_mode, ulong *fb_basep, ulong *fb_sizep, int *pitchp); +/** + * bcm2711_load_vl805_firmware() - get vl805's firmware loaded + * + * @return 0 if OK, -EIO on error + */ +int bcm2711_notify_vl805_reset(void); + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index f4d00d892d..f2a5411623 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -12,10 +12,15 @@ #include <dm/device.h> #include <fdt_support.h> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL + #ifdef CONFIG_ARM64 #include <asm/armv8/mmu.h> -static struct mm_region bcm283x_mem_map[] = { +#define MEM_MAP_MAX_ENTRIES (4) + +static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, @@ -35,11 +40,11 @@ static struct mm_region bcm283x_mem_map[] = { } }; -static struct mm_region bcm2711_mem_map[] = { +static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, - .size = 0xfe000000UL, + .size = 0xfc000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -50,6 +55,13 @@ static struct mm_region bcm2711_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* List terminator */ 0, } @@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) { int i; - for (i = 0; i < 2; i++) { + for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) { mem_map[i].virt = pd[i].virt; mem_map[i].phys = pd[i].phys; mem_map[i].size = pd[i].size; @@ -134,6 +146,27 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE +#ifdef CONFIG_TARGET_RPI_4_32B +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL +#include <addr_map.h> +#include <asm/system.h> + +void init_addr_map(void) +{ + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + DCACHE_OFF); + + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */ + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0); + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */ + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1); +} +#endif + void enable_caches(void) { dcache_enable(); diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c index 94b75283f8..347aece3cd 100644 --- a/arch/arm/mach-bcm283x/msg.c +++ b/arch/arm/mach-bcm283x/msg.c @@ -7,6 +7,7 @@ #include <memalign.h> #include <phys2bus.h> #include <asm/arch/mbox.h> +#include <linux/delay.h> struct msg_set_power_state { struct bcm2835_mbox_hdr hdr; @@ -40,6 +41,12 @@ struct msg_setup { u32 end_tag; }; +struct msg_notify_vl805_reset { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_pci_dev_addr dev_addr; + u32 end_tag; +}; + int bcm2835_power_on_module(u32 module) { ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1); @@ -151,3 +158,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, return 0; } + +/* + * On the Raspberry Pi 4, after a PCI reset, VL805's (the xHCI chip) firmware + * may either be loaded directly from an EEPROM or, if not present, by the + * SoC's VideoCore. This informs VideoCore that VL805 needs its firmware + * loaded. + */ +int bcm2711_notify_vl805_reset(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset, + msg_notify_vl805_reset, 1); + int ret; + + BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset); + BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr, + NOTIFY_XHCI_RESET); + + /* + * The pci device address is expected like this: + * + * PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12 + * + * But since RPi4's PCIe setup is hardwired, we know the address in + * advance. + */ + msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, + &msg_notify_vl805_reset->hdr); + if (ret) { + printf("bcm2711: Faild to load vl805's firmware, %d\n", ret); + return -EIO; + } + + udelay(200); + + return 0; +} + diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c index 8a0eceb178..daf74a0e2d 100644 --- a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c @@ -13,8 +13,8 @@ static const struct udevice_id rk3328_syscon_ids[] = { { } }; -U_BOOT_DRIVER(syscon_rk3328) = { - .name = "rk3328_syscon", +U_BOOT_DRIVER(rockchip_rk3328_grf) = { + .name = "rockchip_rk3328_grf", .id = UCLASS_SYSCON, .of_match = rk3328_syscon_ids, }; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 0722e4a891..cbf0120adc 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -147,7 +147,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, /* Try bootm for legacy and FIT format image */ if (genimg_get_format((void *)uimage) != IMAGE_FORMAT_INVALID) do_bootm(cmdtp, 0, 4, bootm_argv); - else if CONFIG_IS_ENABLED(CMD_BOOTZ) + else if (CONFIG_IS_ENABLED(CMD_BOOTZ)) do_bootz(cmdtp, 0, 4, bootm_argv); } diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index bfb445a602..3a8eee7b84 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -3,24 +3,15 @@ if ARCH_UNIPHIER config SYS_CONFIG_NAME default "uniphier" -config ARCH_UNIPHIER_32BIT - bool - select ARCH_SUPPORT_PSCI - select ARMV7_NONSEC - select CPU_V7A - select CPU_V7_HAS_NONSEC - choice prompt "UniPhier SoC select" - default ARCH_UNIPHIER_V7_MULTI - -config ARCH_UNIPHIER_LD4_SLD8 - bool "UniPhier LD4/sLD8 SoCs" - select ARCH_UNIPHIER_32BIT config ARCH_UNIPHIER_V7_MULTI - bool "UniPhier Pro4/Pro5/PXs2/LD6b SoCs" - select ARCH_UNIPHIER_32BIT + bool "UniPhier V7 SoCs" + select ARCH_SUPPORT_PSCI + select ARMV7_NONSEC + select CPU_V7A + select CPU_V7_HAS_NONSEC config ARCH_UNIPHIER_V8_MULTI bool "UniPhier V8 SoCs" @@ -32,32 +23,38 @@ endchoice config ARCH_UNIPHIER_LD4 bool "Enable UniPhier LD4 SoC support" - depends on ARCH_UNIPHIER_LD4_SLD8 + depends on ARCH_UNIPHIER_V7_MULTI + depends on !SPL || SPL_TEXT_BASE = 0x00040000 default y config ARCH_UNIPHIER_SLD8 bool "Enable UniPhier sLD8 SoC support" - depends on ARCH_UNIPHIER_LD4_SLD8 + depends on ARCH_UNIPHIER_V7_MULTI + depends on !SPL || SPL_TEXT_BASE = 0x00040000 default y config ARCH_UNIPHIER_PRO4 bool "Enable UniPhier Pro4 SoC support" depends on ARCH_UNIPHIER_V7_MULTI + depends on !SPL || SPL_TEXT_BASE = 0x00100000 default y config ARCH_UNIPHIER_PRO5 bool "Enable UniPhier Pro5 SoC support" depends on ARCH_UNIPHIER_V7_MULTI + depends on !SPL || SPL_TEXT_BASE = 0x00100000 default y config ARCH_UNIPHIER_PXS2 bool "Enable UniPhier Pxs2 SoC support" depends on ARCH_UNIPHIER_V7_MULTI + depends on !SPL || SPL_TEXT_BASE = 0x00100000 default y config ARCH_UNIPHIER_LD6B bool "Enable UniPhier LD6b SoC support" depends on ARCH_UNIPHIER_V7_MULTI + depends on !SPL || SPL_TEXT_BASE = 0x00100000 default y config ARCH_UNIPHIER_LD11 @@ -78,7 +75,7 @@ config ARCH_UNIPHIER_PXS3 config CACHE_UNIPHIER bool "Enable the UniPhier L2 cache controller" - depends on ARCH_UNIPHIER_32BIT + depends on ARCH_UNIPHIER_V7_MULTI default y select SYS_CACHE_SHIFT_7 help @@ -86,6 +83,7 @@ config CACHE_UNIPHIER config MICRO_SUPPORT_CARD bool "Use Micro Support Card" + depends on UNIPHIER_SYSTEM_BUS help This option provides support for the expansion board, available on some UniPhier reference boards. @@ -118,5 +116,5 @@ config CMD_DDRMPHY_DUMP training; it is useful for the evaluation of DDR Multi PHY training. config SYS_SOC - default "uniphier-v7" if ARCH_UNIPHIER_LD4_SLD8 || ARCH_UNIPHIER_V7_MULTI + default "uniphier-v7" if ARCH_UNIPHIER_V7_MULTI endif diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 769778cf50..38b6d904f4 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -22,12 +22,10 @@ endif obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o obj-y += pinctrl-glue.o obj-$(CONFIG_MMC) += mmc-first-dev.o -obj-$(CONFIG_NAND_DENALI) += nand-reset.o obj-y += fdt-fixup.o endif -obj-y += sbc/ obj-y += soc-info.o obj-y += boot-device/ obj-y += clk/ diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile index c569551120..750c4f756e 100644 --- a/arch/arm/mach-uniphier/arm64/Makefile +++ b/arch/arm/mach-uniphier/arm64/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += mem_map.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += lowlevel_init.o diff --git a/arch/arm/mach-uniphier/arm64/lowlevel_init.S b/arch/arm/mach-uniphier/arm64/lowlevel_init.S deleted file mode 100644 index f4e5cbbbd1..0000000000 --- a/arch/arm/mach-uniphier/arm64/lowlevel_init.S +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Socionext Inc. - */ - -#include <linux/linkage.h> - -ENTRY(lowlevel_init) - /* LD20 needs the following code to boot. I do not know why. */ - mrs x0, sctlr_el1 - msr sctlr_el1, x0 - ret -ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index 4f9cd6e722..30e4e23a64 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -13,6 +13,33 @@ #include "micro-support-card.h" #include "soc-info.h" +#define PC0CTRL 0x598000c0 + +#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) +static void uniphier_ld4_sbc_init(void) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); +} +#endif + +#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || \ + defined(CONFIG_ARCH_UNIPHIER_LD6B) || \ + defined(CONFIG_ARCH_UNIPHIER_LD11) || \ + defined(CONFIG_ARCH_UNIPHIER_LD20) || \ + defined(CONFIG_ARCH_UNIPHIER_PXS3) +static void uniphier_pxs2_sbc_init(void) +{ + /* necessary for ROM boot ?? */ + /* system bus output enable */ + writel(0x17, PC0CTRL); +} +#endif + #ifdef CONFIG_ARCH_UNIPHIER_LD20 static void uniphier_ld20_misc_init(void) { @@ -45,7 +72,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PRO4) { .soc_id = UNIPHIER_PRO4_ID, - .sbc_init = uniphier_sbc_init_savepin, .pll_init = uniphier_pro4_pll_init, .clk_init = uniphier_pro4_clk_init, }, @@ -60,7 +86,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PRO5) { .soc_id = UNIPHIER_PRO5_ID, - .sbc_init = uniphier_sbc_init_savepin, .clk_init = uniphier_pro5_clk_init, }, #endif @@ -81,7 +106,7 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) { .soc_id = UNIPHIER_LD11_ID, - .sbc_init = uniphier_ld11_sbc_init, + .sbc_init = uniphier_pxs2_sbc_init, .pll_init = uniphier_ld11_pll_init, .clk_init = uniphier_ld11_clk_init, }, @@ -89,7 +114,7 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD20) { .soc_id = UNIPHIER_LD20_ID, - .sbc_init = uniphier_ld11_sbc_init, + .sbc_init = uniphier_pxs2_sbc_init, .pll_init = uniphier_ld20_pll_init, .clk_init = uniphier_ld20_clk_init, .misc_init = uniphier_ld20_misc_init, @@ -118,7 +143,8 @@ int board_init(void) return -EINVAL; } - initdata->sbc_init(); + if (initdata->sbc_init) + initdata->sbc_init(); support_card_init(); @@ -137,14 +163,6 @@ int board_init(void) if (initdata->misc_init) initdata->misc_init(); - led_puts("U3"); - - support_card_late_init(); - - led_puts("U4"); - - uniphier_nand_reset_assert(); - led_puts("Uboo"); return 0; diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 69a35f5fb8..98ff34cfa7 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -14,11 +14,18 @@ #include <linux/log2.h> #include "../init.h" -#include "../sbc/sbc-regs.h" #include "../sg-regs.h" #include "../soc-info.h" #include "boot-device.h" +#define SBBASE0 0x58c00100 +#define SBBASE_BANK_ENABLE BIT(0) + +static int uniphier_sbc_boot_is_swapped(void) +{ + return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); +} + struct uniphier_boot_device_info { unsigned int soc_id; unsigned int boot_device_sel_shift; diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 622303786c..dd978c0208 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -34,34 +34,6 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd); int uniphier_pro5_init(const struct uniphier_board_data *bd); int uniphier_pxs2_init(const struct uniphier_board_data *bd); -#if defined(CONFIG_MICRO_SUPPORT_CARD) -void uniphier_sbc_init_admulti(void); -void uniphier_sbc_init_savepin(void); -void uniphier_ld4_sbc_init(void); -void uniphier_pxs2_sbc_init(void); -void uniphier_ld11_sbc_init(void); -#else -static inline void uniphier_sbc_init_admulti(void) -{ -} - -static inline void uniphier_sbc_init_savepin(void) -{ -} - -static inline void uniphier_ld4_sbc_init(void) -{ -} - -static inline void uniphier_pxs2_sbc_init(void) -{ -} - -static inline void uniphier_ld11_sbc_init(void) -{ -} -#endif - void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd); int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd); @@ -103,13 +75,6 @@ int uniphier_have_internal_stm(void); int uniphier_boot_from_backend(void); int uniphier_pin_init(const char *pinconfig_name); -#ifdef CONFIG_NAND_DENALI -void uniphier_nand_reset_assert(void); -#else -static inline void uniphier_nand_reset_assert(void) -{ -} -#endif #ifdef CONFIG_ARM64 void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size); #else diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c index b09ec54e1f..dbd156ffce 100644 --- a/arch/arm/mach-uniphier/micro-support-card.c +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -5,8 +5,7 @@ * Author: Masahiro Yamada <yamada.masahiro@socionext.com> */ -#include <config.h> -#include <dm/of.h> +#include <dm.h> #include <fdt_support.h> #include <linux/ctype.h> #include <linux/delay.h> @@ -91,6 +90,17 @@ static int support_card_show_revision(void) void support_card_init(void) { + struct udevice *dev; + int ret; + + /* The system bus must be initialized for access to the support card. */ + ret = uclass_get_device_by_driver(UCLASS_SIMPLE_BUS, + DM_GET_DRIVER(uniphier_system_bus_driver), + &dev); + if (ret) + return; + + /* Check DT to see if this board has the support card. */ support_card_detect(); if (!support_card_found) @@ -107,102 +117,6 @@ void support_card_init(void) support_card_show_revision(); } -#if defined(CONFIG_MTD_NOR_FLASH) - -#include <mtd/cfi_flash.h> - -struct memory_bank { - phys_addr_t base; - unsigned long size; -}; - -static int mem_is_flash(const struct memory_bank *mem) -{ - const int loop = 128; - u32 *scratch_addr; - u32 saved_value; - int ret = 1; - int i; - - /* just in case, use the tail of the memory bank */ - scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop, - sizeof(u32) * loop, MAP_NOCACHE); - - for (i = 0; i < loop; i++, scratch_addr++) { - saved_value = readl(scratch_addr); - writel(~saved_value, scratch_addr); - if (readl(scratch_addr) != saved_value) { - /* We assume no memory or SRAM here. */ - writel(saved_value, scratch_addr); - ret = 0; - break; - } - } - - unmap_physmem(scratch_addr, MAP_NOCACHE); - - return ret; -} - -/* {address, size} */ -static const struct memory_bank memory_banks[] = { - {0x42000000, 0x01f00000}, -}; - -static const struct memory_bank -*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; - -phys_addr_t cfi_flash_bank_addr(int i) -{ - return flash_banks_list[i]->base; -} - -unsigned long cfi_flash_bank_size(int i) -{ - return flash_banks_list[i]->size; -} - -static void detect_num_flash_banks(void) -{ - const struct memory_bank *memory_bank, *end; - - cfi_flash_num_flash_banks = 0; - - memory_bank = memory_banks; - end = memory_bank + ARRAY_SIZE(memory_banks); - - for (; memory_bank < end; memory_bank++) { - if (cfi_flash_num_flash_banks >= - CONFIG_SYS_MAX_FLASH_BANKS_DETECT) - break; - - if (mem_is_flash(memory_bank)) { - flash_banks_list[cfi_flash_num_flash_banks] = - memory_bank; - - debug("flash bank found: base = 0x%lx, size = 0x%lx\n", - (unsigned long)memory_bank->base, - (unsigned long)memory_bank->size); - cfi_flash_num_flash_banks++; - } - } - - debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); -} -#else /* CONFIG_MTD_NOR_FLASH */ -static void detect_num_flash_banks(void) -{ -}; -#endif /* CONFIG_MTD_NOR_FLASH */ - -void support_card_late_init(void) -{ - if (!support_card_found) - return; - - detect_num_flash_banks(); -} - static const u8 ledval_num[] = { 0x7e, /* 0 */ 0x0c, /* 1 */ diff --git a/arch/arm/mach-uniphier/nand-reset.c b/arch/arm/mach-uniphier/nand-reset.c deleted file mode 100644 index 11cadaabd8..0000000000 --- a/arch/arm/mach-uniphier/nand-reset.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 or later -/* - * Copyright (C) 2020 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - */ - -#include <linux/errno.h> -#include <dm.h> -#include <dm/uclass-internal.h> -#include <reset.h> - -#include "init.h" - -/* - * Assert the Denali NAND controller reset if found. - * - * On LD4, the bootstrap process starts running after power-on reset regardless - * of the boot mode, here the pin-mux is not necessarily set up for NAND, then - * the controller is stuck. Assert the controller reset here, and should be - * deasserted in the driver after the pin-mux is correctly handled. For other - * SoCs, the bootstrap runs only when the boot mode selects ONFi, but it is yet - * effective when the boot swap is on. So, the reset should be asserted anyway. - */ -void uniphier_nand_reset_assert(void) -{ - struct udevice *dev; - struct reset_ctl_bulk resets; - int ret; - - ret = uclass_find_first_device(UCLASS_MTD, &dev); - if (ret || !dev) - return; - - /* make sure this is the Denali NAND controller */ - if (strcmp(dev->driver->name, "denali-nand-dt")) - return; - - ret = reset_get_bulk(dev, &resets); - if (ret) - return; - - reset_assert_bulk(&resets); -} diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile deleted file mode 100644 index 6c698a3922..0000000000 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -obj-y += sbc-boot.o - -ifndef CONFIG_SPL_BUILD -obj-y += sbc.o - -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += sbc-pxs2.o -endif diff --git a/arch/arm/mach-uniphier/sbc/sbc-boot.c b/arch/arm/mach-uniphier/sbc/sbc-boot.c deleted file mode 100644 index ec22b453e0..0000000000 --- a/arch/arm/mach-uniphier/sbc/sbc-boot.c +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright (C) 2011-2014 Panasonic Corporation -// Copyright (C) 2015-2019 Socionext Inc. - -#include <linux/io.h> - -#include "sbc-regs.h" - -int uniphier_sbc_boot_is_swapped(void) -{ - return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); -} diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld11.c b/arch/arm/mach-uniphier/sbc/sbc-ld11.c deleted file mode 100644 index a0162e1cc8..0000000000 --- a/arch/arm/mach-uniphier/sbc/sbc-ld11.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016-2017 Socionext Inc. - */ - -#include <spl.h> -#include <linux/io.h> - -#include "../init.h" -#include "sbc-regs.h" - -void uniphier_ld11_sbc_init(void) -{ - if (!uniphier_sbc_is_enabled()) - return; - - uniphier_sbc_init_savepin(); - - /* necessary for ROM boot ?? */ - /* system bus output enable */ - writel(0x17, PC0CTRL); - - /* pins for NAND and System Bus are multiplexed */ - if (spl_boot_device() != BOOT_DEVICE_NAND) - uniphier_pin_init("system-bus"); -} diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ld4.c deleted file mode 100644 index 72e9743c8f..0000000000 --- a/arch/arm/mach-uniphier/sbc/sbc-ld4.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011-2015 Panasonic Corporation - * Copyright (C) 2015-2017 Socionext Inc. - */ - -#include <linux/io.h> - -#include "../init.h" -#include "sbc-regs.h" - -void uniphier_ld4_sbc_init(void) -{ - u32 tmp; - - if (!uniphier_sbc_is_enabled()) - return; - - uniphier_sbc_init_savepin(); - - /* system bus output enable */ - tmp = readl(PC0CTRL); - tmp &= 0xfffffcff; - writel(tmp, PC0CTRL); -} diff --git a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c deleted file mode 100644 index 3275f22ce9..0000000000 --- a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016-2017 Socionext Inc. - */ - -#include <linux/io.h> - -#include "../init.h" -#include "sbc-regs.h" - -void uniphier_pxs2_sbc_init(void) -{ - if (!uniphier_sbc_is_enabled()) - return; - - uniphier_sbc_init_savepin(); - - /* necessary for ROM boot ?? */ - /* system bus output enable */ - writel(0x17, PC0CTRL); - - uniphier_pin_init("system-bus"); /* PXs3 */ -} diff --git a/arch/arm/mach-uniphier/sbc/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h deleted file mode 100644 index 1e9618653f..0000000000 --- a/arch/arm/mach-uniphier/sbc/sbc-regs.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * UniPhier SBC (System Bus Controller) registers - * - * Copyright (C) 2011-2014 Panasonic Corporation - * Copyright (C) 2015-2016 Socionext Inc. - */ - -#ifndef ARCH_SBC_REGS_H -#define ARCH_SBC_REGS_H - -#define SBBASE_BASE 0x58c00100 -#define SBBASE(x) (SBBASE_BASE + (x) * 0x10) - -#define SBBASE0 (SBBASE(0)) -#define SBBASE1 (SBBASE(1)) -#define SBBASE2 (SBBASE(2)) -#define SBBASE3 (SBBASE(3)) -#define SBBASE4 (SBBASE(4)) -#define SBBASE5 (SBBASE(5)) -#define SBBASE6 (SBBASE(6)) -#define SBBASE7 (SBBASE(7)) - -#define SBBASE_BANK_ENABLE (0x00000001) - -#define SBCTRL_BASE 0x58c00200 -#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4) - -#define SBCTRL00 SBCTRL(0, 0) -#define SBCTRL01 SBCTRL(0, 1) -#define SBCTRL02 SBCTRL(0, 2) -#define SBCTRL03 SBCTRL(0, 3) -#define SBCTRL04 (SBCTRL_BASE + 0x100) - -#define SBCTRL10 SBCTRL(1, 0) -#define SBCTRL11 SBCTRL(1, 1) -#define SBCTRL12 SBCTRL(1, 2) -#define SBCTRL13 SBCTRL(1, 3) -#define SBCTRL14 (SBCTRL_BASE + 0x110) - -#define SBCTRL20 SBCTRL(2, 0) -#define SBCTRL21 SBCTRL(2, 1) -#define SBCTRL22 SBCTRL(2, 2) -#define SBCTRL23 SBCTRL(2, 3) -#define SBCTRL24 (SBCTRL_BASE + 0x120) - -#define SBCTRL30 SBCTRL(3, 0) -#define SBCTRL31 SBCTRL(3, 1) -#define SBCTRL32 SBCTRL(3, 2) -#define SBCTRL33 SBCTRL(3, 3) -#define SBCTRL34 (SBCTRL_BASE + 0x130) - -#define SBCTRL40 SBCTRL(4, 0) -#define SBCTRL41 SBCTRL(4, 1) -#define SBCTRL42 SBCTRL(4, 2) -#define SBCTRL43 SBCTRL(4, 3) -#define SBCTRL44 (SBCTRL_BASE + 0x140) - -#define SBCTRL50 SBCTRL(5, 0) -#define SBCTRL51 SBCTRL(5, 1) -#define SBCTRL52 SBCTRL(5, 2) -#define SBCTRL53 SBCTRL(5, 3) -#define SBCTRL54 (SBCTRL_BASE + 0x150) - -#define SBCTRL60 SBCTRL(6, 0) -#define SBCTRL61 SBCTRL(6, 1) -#define SBCTRL62 SBCTRL(6, 2) -#define SBCTRL63 SBCTRL(6, 3) -#define SBCTRL64 (SBCTRL_BASE + 0x160) - -#define SBCTRL70 SBCTRL(7, 0) -#define SBCTRL71 SBCTRL(7, 1) -#define SBCTRL72 SBCTRL(7, 2) -#define SBCTRL73 SBCTRL(7, 3) -#define SBCTRL74 (SBCTRL_BASE + 0x170) - -#define PC0CTRL 0x598000c0 - -int uniphier_sbc_boot_is_swapped(void); -int uniphier_sbc_is_enabled(void); - -#endif /* ARCH_SBC_REGS_H */ diff --git a/arch/arm/mach-uniphier/sbc/sbc.c b/arch/arm/mach-uniphier/sbc/sbc.c deleted file mode 100644 index 2100f49a08..0000000000 --- a/arch/arm/mach-uniphier/sbc/sbc.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011-2015 Panasonic Corporation - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - */ - -#include <linux/io.h> -#include <asm/global_data.h> - -#include "../init.h" -#include "sbc-regs.h" - -#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000 -#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500 -#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020 - -#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000 -#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500 -#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010 - -/* slower but LED works */ -#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000 -#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00 -#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009 -#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110 - -/* faster but LED does not work */ -#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000 -#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700 -/* NOR flash needs more wait counts than SRAM */ -#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009 -#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210 - -int uniphier_sbc_is_enabled(void) -{ - DECLARE_GLOBAL_DATA_PTR; - const void *fdt = gd->fdt_blob; - int offset; - - offset = fdt_node_offset_by_compatible(fdt, 0, - "socionext,uniphier-system-bus"); - if (offset < 0) - return 0; - - return fdtdec_get_is_enabled(fdt, offset); -} - -static void __uniphier_sbc_init(int savepin) -{ - /* - * Only CS1 is connected to support card. - * BKSZ[1:0] should be set to "01". - */ - if (savepin) { - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); - } else { - writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); - } - - if (uniphier_sbc_boot_is_swapped()) { - /* - * Boot Swap On: boot from external NOR/SRAM - * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. - * - * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank - * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals - */ - writel(0x0000bc01, SBBASE0); - } else { - /* - * Boot Swap Off: boot from mask ROM - * 0x40000000-0x41ffffff: mask ROM - * 0x42000000-0x43efffff: memory bank (31MB) - * 0x43f00000-0x43ffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } -} - -void uniphier_sbc_init_admulti(void) -{ - __uniphier_sbc_init(0); -} - -void uniphier_sbc_init_savepin(void) -{ - __uniphier_sbc_init(1); -} diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 2a08533c4b..65f988e736 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -15,6 +15,16 @@ config SANDBOX64 select PHYS_64BIT select HOST_64BIT +config SANDBOX_RAM_SIZE_MB + int "RAM size in MiB" + default 128 + range 64 4095 if !SANDBOX64 + range 64 268435456 if SANDBOX64 + help + Memory size of the sandbox in MiB. The default value is 128 MiB. + The minimum value is 64 MiB. The maximum value is 4095 MiB for the + 32bit sandbox. + config SANDBOX_SPL bool "Enable SPL for sandbox" select SUPPORT_SPL diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 1f794123b3..34b6fff7e7 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -378,7 +378,10 @@ int state_init(void) state->ram_size = CONFIG_SYS_SDRAM_SIZE; state->ram_buf = os_malloc(state->ram_size); - assert(state->ram_buf); + if (!state->ram_buf) { + printf("Out of memory\n"); + os_exit(1); + } state_reset_for_test(state); /* diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds index de65b01b33..c60eb109b1 100644 --- a/arch/sandbox/cpu/u-boot-spl.lds +++ b/arch/sandbox/cpu/u-boot-spl.lds @@ -20,4 +20,4 @@ SECTIONS __bss_start = .; } -INSERT BEFORE .data; +INSERT AFTER .data; diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 705645d714..1bfad305f1 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -73,7 +73,7 @@ struct sandbox_state { char **argv; /* Command line arguments */ const char *jumped_fname; /* Jumped from previous U_Boot */ uint8_t *ram_buf; /* Emulated RAM buffer */ - unsigned int ram_size; /* Size of RAM buffer */ + unsigned long ram_size; /* Size of RAM buffer */ const char *ram_buf_fname; /* Filename to use for RAM buffer */ bool ram_buf_rm; /* Remove RAM buffer file after read */ bool write_ram_buf; /* Write RAM buffer on exit */ diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 11621256ae..3aa2a55676 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -3,6 +3,7 @@ # Copyright 2019 Google LLC obj-$(CONFIG_SPL_BUILD) += cpu_spl.o +obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o obj-y += cpu_common.o @@ -11,7 +12,6 @@ obj-y += cpu.o obj-y += punit.o obj-y += fsp_bindings.o ifdef CONFIG_SPL_BUILD -obj-y += spl.o obj-y += fsp_m.o endif endif diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 435e50edad..d27324cb4e 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -363,6 +363,11 @@ static void setup_cpu_features(void) : : "i" (em_rst), "i" (mp_ne_set) : "eax"); } +void cpu_reinit_fpu(void) +{ + asm ("fninit\n"); +} + static void setup_identity(void) { /* identify CPU via cpuid and store the decoded info into gd->arch */ diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 3e5d56d075..bd3f44014c 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -43,6 +43,14 @@ int x86_cpu_reinit_f(void); */ int x86_cpu_init_tpl(void); +/** + * cpu_reinit_fpu() - Reinit the FPU if something is wrong with it + * + * The FSP-M code can leave registers in use in the FPU. This functions reinits + * it so that the FPU can be used safely + */ +void cpu_reinit_fpu(void); + int cpu_init_f(void); void setup_gdt(struct global_data *id, u64 *gdt_addr); /* diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 6e23f3c95f..e8c1e07af1 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -117,6 +117,16 @@ err: return ret; } +static int fsp_video_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + + /* Set the maximum supported resolution */ + plat->size = 2560 * 1600 * 4; + + return 0; +} + static const struct udevice_id fsp_video_ids[] = { { .compatible = "fsp-fb" }, { } @@ -126,7 +136,9 @@ U_BOOT_DRIVER(fsp_video) = { .name = "fsp_video", .id = UCLASS_VIDEO, .of_match = fsp_video_ids, + .bind = fsp_video_bind, .probe = fsp_video_probe, + .flags = DM_FLAG_PRE_RELOC, }; static struct pci_device_id fsp_video_supported[] = { diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c index 1a758147b0..faf9c29aef 100644 --- a/arch/x86/lib/fsp2/fsp_meminit.c +++ b/arch/x86/lib/fsp2/fsp_meminit.c @@ -85,6 +85,7 @@ int fsp_memory_init(bool s3wake, bool use_spi_flash) func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init); ret = func(&upd, &hob); bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_M); + cpu_reinit_fpu(); if (ret) return log_msg_ret("SDRAM init fail\n", ret); |