diff options
Diffstat (limited to 'arch')
35 files changed, 148 insertions, 87 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 595c951ed2..9b9b78eddd 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -237,4 +237,5 @@ void prcm_init() enable_basic_clocks(); scale_vcores(); setup_dplls(); + timer_init(); } diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index ed9ba7b5d3..0456263d6e 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -111,6 +111,8 @@ void save_omap_boot_params(void) (boot_device <= MMC_BOOT_DEVICES_END)) { switch (boot_device) { case BOOT_DEVICE_MMC1: + boot_mode = MMCSD_MODE_FS; + break; case BOOT_DEVICE_MMC2: boot_mode = MMCSD_MODE_RAW; break; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index d580a43b41..a9b12a43ad 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num) /* * DDR controller 0 & 1 are on memory complex 0 - * DDR controler 2 is on memory complext 1 + * DDR controller 2 is on memory complext 1 */ #ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num >= 2) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index deb44a895f..c3cc8199ca 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -214,7 +214,9 @@ WEAK(lowlevel_init) ldr x1, =GICC_BASE bl gic_init_secure_percpu #endif +#endif +#ifndef CONFIG_ARMV8_MULTIENTRY branch_if_master x0, x1, 2f /* diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index d2ab3b3669..bdd93248fb 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -83,5 +83,6 @@ }; &usb1 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index c208628f35..d34a784eec 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -68,7 +68,7 @@ SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE $(call if_changed,mkimage) MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ - -e $(CONFIG_SYS_TEXT_BASE) -C none + -e $(CONFIG_SYS_TEXT_BASE) -C none -T firmware u-boot.uim: u-boot.bin FORCE $(call if_changed,mkimage) diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c index 54b021cfed..b77548821d 100644 --- a/arch/arm/imx-common/cache.c +++ b/arch/arm/imx-common/cache.c @@ -43,6 +43,12 @@ void v7_outer_cache_enable(void) /* + * Must disable the L2 before changing the latency parameters + * and auxiliary control register. + */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + /* * Set bit 22 in the auxiliary control register. If this bit * is cleared, PL310 treats Normal Shared Non-cacheable * accesses as Cacheable no-allocate. @@ -59,9 +65,6 @@ void v7_outer_cache_enable(void) } #endif - /* Must disable the L2 before changing the latency parameters */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - writel(0x132, &pl310->pl310_tag_latency_ctrl); writel(0x132, &pl310->pl310_data_latency_ctrl); diff --git a/arch/arm/include/asm/arch-tegra/gpu.h b/arch/arm/include/asm/arch-tegra/gpu.h index 4423386f28..6be9f6157b 100644 --- a/arch/arm/include/asm/arch-tegra/gpu.h +++ b/arch/arm/include/asm/arch-tegra/gpu.h @@ -26,7 +26,7 @@ int tegra_gpu_enable_node(void *blob, const char *gpupath); #else /* CONFIG_OF_LIBFDT */ -static inline int tegra_gpu_enable_node(void *blob, const char *gpupath) +static inline int tegra_gpu_enable_node(void *blob, const char *compat) { return 0; } diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 30e7939d8e..423fc70111 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -59,26 +59,7 @@ #ifndef __ASSEMBLY__ #include <linux/types.h> #include <asm/io.h> - -/* - * CP15 Barrier instructions - * Please note that we have separate barrier instructions in ARMv7 - * However, we use the CP15 based instructtions because we use - * -march=armv5 in U-Boot - */ -#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) -#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) -#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) - -#ifdef __ARM_ARCH_7A__ -#define ISB asm volatile ("isb" : : : "memory") -#define DSB asm volatile ("dsb" : : : "memory") -#define DMB asm volatile ("dmb" : : : "memory") -#else -#define ISB CP15ISB -#define DSB CP15DSB -#define DMB CP15DMB -#endif +#include <asm/barriers.h> /* * Workaround for ARM errata # 798870 diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h new file mode 100644 index 0000000000..37870f9d71 --- /dev/null +++ b/arch/arm/include/asm/barriers.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * + * ARM and ARM64 barrier instructions + * split from armv7.h to allow sharing between ARM and ARM64 + * + * Original copyright in armv7.h was: + * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com> + * + * Much of the original barrier code was contributed by: + * Valentine Barshak <valentine.barshak@cogentembedded.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __BARRIERS_H__ +#define __BARRIERS_H__ + +#ifndef __ASSEMBLY__ + +#ifndef CONFIG_ARM64 +/* + * CP15 Barrier instructions + * Please note that we have separate barrier instructions in ARMv7 + * However, we use the CP15 based instructtions because we use + * -march=armv5 in U-Boot + */ +#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) +#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) +#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) + +#endif /* !CONFIG_ARM64 */ + +#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64) +#define ISB asm volatile ("isb sy" : : : "memory") +#define DSB asm volatile ("dsb sy" : : : "memory") +#define DMB asm volatile ("dmb sy" : : : "memory") +#else +#define ISB CP15ISB +#define DSB CP15DSB +#define DMB CP15DMB +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BARRIERS_H__ */ diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index cf10a53ec6..4614d2657c 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com> + * Copyright (c) 2015 Andreas Bießmann <andreas@biessmann.org> * * Copyright (c) 2011 The Chromium OS Authors. * (C) Copyright 2002-2006 diff --git a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c index 9b9800ad9a..f139b9167d 100644 --- a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c +++ b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c @@ -2,7 +2,7 @@ * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c] * * (C) Copyright 2011 - * Andreas Bießmann <andreas.devel@googlemail.com> + * Andreas Bießmann <andreas@biessmann.org> * * (C) Copyright 2007-2008 * Stelian Pop <stelian@popies.net> diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c index b0f411b1c3..926d1c9fe8 100644 --- a/arch/arm/mach-at91/arm920t/cpu.c +++ b/arch/arm/mach-at91/arm920t/cpu.c @@ -2,7 +2,7 @@ * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c] * * (C) Copyright 2011 - * Andreas Bießmann, andreas.devel@googlemail.com + * Andreas Bießmann, andreas@biessmann.org * (C) Copyright 2010 * Reinhard Meyer, reinhard.meyer@emk-elektronik.de * (C) Copyright 2009 diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index 71330cb26d..2e21282335 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -561,14 +561,14 @@ static void dram_all_config(const struct dram_info *dram, &sdram_params->ch[chan]; sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); - sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan); sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); - sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); + sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0; sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); - sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); - sys_reg |= (2 >>info->dbw) << SYS_REG_DBW_SHIFT(chan); + sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan); + sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan); dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); } @@ -720,13 +720,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu) rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK); col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK) ; + bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0; cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK); cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK); - bw = (2 >> (sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK); + bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK; row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index dd05e14c05..5cbd8a4325 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -172,7 +172,7 @@ static int socfpga_eth_reset(void) #else static int socfpga_eth_reset(void) { - return 0 + return 0; }; #endif diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 50318d2eb6..20b430f859 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <asm/barriers.h> #include <asm/io.h> #include <asm/arch/dram.h> @@ -31,6 +32,7 @@ bool mctl_mem_matches(u32 offset) /* Try to write different values to RAM at two addresses */ writel(0, CONFIG_SYS_SDRAM_BASE); writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); + DSB; /* Check if the same value is actually observed when reading back */ return readl(CONFIG_SYS_SDRAM_BASE) == readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index ac274e17e8..141d6e1cb5 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -404,16 +404,22 @@ ulong board_get_usable_ram_top(ulong total_size) */ int ft_system_setup(void *blob, bd_t *bd) { - const char *gpu_path = -#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) - "/gpu@0,57000000"; -#else - NULL; + const char *gpu_compats[] = { +#if defined(CONFIG_TEGRA124) + "nvidia,gk20a", +#endif +#if defined(CONFIG_TEGRA210) + "nvidia,gm20b", #endif + }; + int i, ret; /* Enable GPU node if GPU setup has been performed */ - if (gpu_path != NULL) - return tegra_gpu_enable_node(blob, gpu_path); + for (i = 0; i < ARRAY_SIZE(gpu_compats); i++) { + ret = tegra_gpu_enable_node(blob, gpu_compats[i]); + if (ret) + return ret; + } return 0; } diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 0dbddd45d4..74b64a620c 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -33,16 +33,17 @@ void tegra_gpu_config(void) #if defined(CONFIG_OF_LIBFDT) -int tegra_gpu_enable_node(void *blob, const char *gpupath) +int tegra_gpu_enable_node(void *blob, const char *compat) { int offset; - if (_configured) { - offset = fdt_path_offset(blob, gpupath); - if (offset > 0) { - fdt_status_okay(blob, offset); - debug("enabled GPU node %s\n", gpupath); - } + if (!_configured) + return 0; + + offset = fdt_node_offset_by_compatible(blob, -1, compat); + while (offset != -FDT_ERR_NOTFOUND) { + fdt_status_okay(blob, offset); + offset = fdt_node_offset_by_compatible(blob, offset, compat); } return 0; diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c index 100275e6cb..b092c1bde8 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c @@ -43,7 +43,7 @@ static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"}, {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"}, {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"}, - {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NOR, "NOR Boot (XECS1)"}, }; static int get_boot_mode_sel(void) diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index 48e478c5d1..b180f44ce8 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -114,7 +114,7 @@ static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( mmcsetn, 1, 1, do_mmcsetn, - "Set the first MMC (not SD) dev number to \"mmc_first_dev\" enviroment", + "Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment", "" ); #endif diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c index 37adb37a1f..5201a55940 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c @@ -21,6 +21,10 @@ int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd) writel(tmp, SC_RSTCTRL7); /* provide clocks */ + tmp = readl(SC_CLKCTRL4); + tmp |= SC_CLKCTRL4_PERI; + writel(tmp, SC_CLKCTRL4); + tmp = readl(SC_CLKCTRL7); tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30; diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile index dc4064c05b..a1039025ca 100644 --- a/arch/arm/mach-uniphier/early-pinctrl/Makefile +++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile @@ -3,3 +3,4 @@ # obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c new file mode 100644 index 0000000000..537deaf232 --- /dev/null +++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../init.h" +#include "../sg-regs.h" + +int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd) +{ + /* Comment format: PAD Name -> Function Name */ + sg_set_pinsel(0, 0, 8, 4); /* XECS1 -> XECS1 */ + sg_set_pinsel(1, 0, 8, 4); /* ERXW -> ERXW */ + sg_set_pinsel(2, 0, 8, 4); /* XERWE1 -> XERWE1 */ + sg_set_pinsel(6, 2, 8, 4); /* XNFRE -> XERWE0 */ + sg_set_pinsel(7, 2, 8, 4); /* XNFWE -> ES0 */ + sg_set_pinsel(8, 2, 8, 4); /* NFALE -> ES1 */ + sg_set_pinsel(9, 2, 8, 4); /* NFCLE -> ES2 */ + sg_set_pinsel(10, 2, 8, 4); /* NFD0 -> ED0 */ + sg_set_pinsel(11, 2, 8, 4); /* NFD1 -> ED1 */ + sg_set_pinsel(12, 2, 8, 4); /* NFD2 -> ED2 */ + sg_set_pinsel(13, 2, 8, 4); /* NFD3 -> ED3 */ + sg_set_pinsel(14, 2, 8, 4); /* NFD4 -> ED4 */ + sg_set_pinsel(15, 2, 8, 4); /* NFD5 -> ED5 */ + sg_set_pinsel(16, 2, 8, 4); /* NFD6 -> ED6 */ + sg_set_pinsel(17, 2, 8, 4); /* NFD7 -> ED7 */ + sg_set_iectrl_range(0, 2); + sg_set_iectrl_range(6, 17); + + return 0; +} diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c index 22c07fbfe1..6c5d58f856 100644 --- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c +++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c @@ -22,5 +22,7 @@ int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd) sg_set_pinsel(102, 2, 4, 4); /* TXD2 */ #endif + sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */ + return 0; } diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index f5b3fa836c..ab0a68d83d 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -37,7 +37,6 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd); #if defined(CONFIG_MICRO_SUPPORT_CARD) int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd); int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd); -int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd); int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd); int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd); #else @@ -53,11 +52,6 @@ static inline int uniphier_sbc_init_savepin( return 0; } -static inline int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd) -{ - return 0; -} - static inline int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd) { return 0; @@ -90,6 +84,7 @@ int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd); int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd); int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd); +int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd); int uniphier_ld4_umc_init(const struct uniphier_board_data *bd); int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c index 0ad264c9f1..660ad457dc 100644 --- a/arch/arm/mach-uniphier/init/init-ld20.c +++ b/arch/arm/mach-uniphier/init/init-ld20.c @@ -13,6 +13,8 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd) { uniphier_sbc_init_savepin(bd); + uniphier_pxs2_sbc_init(bd); + uniphier_ld20_early_pin_init(bd); support_card_reset(); diff --git a/arch/arm/mach-uniphier/init/init-sld3.c b/arch/arm/mach-uniphier/init/init-sld3.c index 473e0c8831..50fcbb09b8 100644 --- a/arch/arm/mach-uniphier/init/init-sld3.c +++ b/arch/arm/mach-uniphier/init/init-sld3.c @@ -15,7 +15,8 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd) uniphier_sld3_bcu_init(bd); uniphier_sbc_init_admulti(bd); - uniphier_sld3_sbc_init(bd); + + uniphier_sld3_early_pin_init(bd); support_card_reset(); @@ -34,8 +35,6 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd) led_puts("L2"); - uniphier_sld3_early_pin_init(bd); - led_puts("L3"); #ifdef CONFIG_SPL_SERIAL_SUPPORT diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index 3c1e92a54d..38da253975 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -2,11 +2,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += sbc-admulti.o sbc-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += sbc-admulti.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-savepin.o sbc-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += sbc-savepin.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o sbc-pxs2.o diff --git a/arch/arm/mach-uniphier/sbc/sbc-sld3.c b/arch/arm/mach-uniphier/sbc/sbc-sld3.c deleted file mode 100644 index ac9d0301be..0000000000 --- a/arch/arm/mach-uniphier/sbc/sbc-sld3.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd) -{ - sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */ - - return 0; -} diff --git a/arch/avr32/cpu/mmc.c b/arch/avr32/cpu/mmc.c index b7213e4e7a..26ba3a24e4 100644 --- a/arch/avr32/cpu/mmc.c +++ b/arch/avr32/cpu/mmc.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2004-2006 Atmel Corporation - * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlmail.com> + * Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/avr32/lib/bootm.c b/arch/avr32/lib/bootm.c index 1c26f1b36a..342b9e2c1c 100644 --- a/arch/avr32/lib/bootm.c +++ b/arch/avr32/lib/bootm.c @@ -174,7 +174,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima /* * allow the PREP bootm subcommand, it is required for bootm to work * - * TODO: Andreas Bießmann <andreas.devel@googlemail.com> refactor the + * TODO: Andreas Bießmann <andreas@biessmann.org> refactor the * do_bootm_linux() for avr32 */ if (flag & BOOTM_STATE_OS_PREP) diff --git a/arch/avr32/lib/dram_init.c b/arch/avr32/lib/dram_init.c index 5078e77f17..79c2455bd6 100644 --- a/arch/avr32/lib/dram_init.c +++ b/arch/avr32/lib/dram_init.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlemail.com> + * Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f852a1f1bb..fe37d1fa2d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -145,7 +145,7 @@ config MIPS_BOOT_ENV_LEGACY Enable this option if you want U-Boot to hand over the Yamon-style environment to the kernel. Information like memory size, initrd address and size will be prepared as zero-terminated key/value list. - The address of the enviroment is stored in register $a2. + The address of the environment is stored in register $a2. config MIPS_BOOT_FDT bool "Hand over a flattened device tree to Linux kernel" diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c index 916451a2b0..455136c68c 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c @@ -1151,7 +1151,7 @@ phys_size_t initdram(int board_type) dram_size *= ranks; debug("dram_size = %lu\n", dram_size); - /* Start the SDRAM controler */ + /* Start the SDRAM controller */ mtsdram(DDR0_02, DDR0_02_START_ENCODE(1)); denali_wait_for_dlllock(); diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c index 1985f0348d..7eccfe0e30 100644 --- a/arch/powerpc/lib/stack.c +++ b/arch/powerpc/lib/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com> + * Copyright (c) 2015 Andreas Bießmann <andreas@biessmann.org> * * Copyright (c) 2011 The Chromium OS Authors. * (C) Copyright 2002-2006 |